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Differential D156381

Revert "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
ClosedPublic

Authored by vitalybuka on Jul 26 2023, 4:00 PM.

Details

Reviewers
arsenm
alexfh
cdevadas
yassingh
Group Reviewers
Restricted Project
Commits
rGa496c8be6e63: Revert "[CodeGen]Allow targets to use target specific COPY instructions for…
Summary

And dependent commits.

Details in D150388.

This reverts commit 825b7f0ca5f2211ec3c93139f98d1e24048c225c.
This reverts commit 7a98f084c4d121244ef7286bc6503b6a181d446e.
This reverts commit b4a62b1fa546312d882fa12dfdcd015177d66826.
This reverts commit b7836d856206ec39509d42529f958c920368166b.

No conflicts in the code, few tests had conflicts in autogenerated CHECKs:
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll

Diff Detail

Event Timeline

vitalybuka created this revision.Jul 26 2023, 4:00 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 4:00 PM
Herald added subscribers: foad, kerbowa, pengfei and 9 others. · View Herald Transcript
vitalybuka requested review of this revision.Jul 26 2023, 4:00 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 4:00 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
vitalybuka added reviewers: arsenm, alexfh.Jul 26 2023, 4:01 PM
Herald added a subscriber: wdng. · View Herald TranscriptJul 26 2023, 4:01 PM
vitalybuka edited the summary of this revision. (Show Details)Jul 26 2023, 4:03 PM
Herald added subscribers: dmgreen, tpr. · View Herald TranscriptJul 26 2023, 4:03 PM
vitalybuka edited the summary of this revision. (Show Details)Jul 26 2023, 4:04 PM
vitalybuka edited the summary of this revision. (Show Details)Jul 26 2023, 4:12 PM
vitalybuka mentioned this in D156346: CodeGen: Disable isCopyInstrImpl if there are implicit operands.Jul 26 2023, 4:31 PM
alexfh accepted this revision.Jul 26 2023, 5:53 PM

This is the right approach to solve the problems discussed in D150388. Looking at the attempt to fix forward (https://reviews.llvm.org/D156346), I wish we insisted on a revert from the start. Looks good.

This revision is now accepted and ready to land.Jul 26 2023, 5:53 PM
alexfh added reviewers: cdevadas, yassingh.Jul 26 2023, 6:38 PM
Harbormaster completed remote builds in B248395: Diff 544546.Jul 26 2023, 8:09 PM
yassingh added a reviewer: Restricted Project.Jul 26 2023, 10:05 PM
This revision was landed with ongoing or failed builds.Jul 26 2023, 10:13 PM
Closed by commit rGa496c8be6e63: Revert "[CodeGen]Allow targets to use target specific COPY instructions for… (authored by vitalybuka). · Explain Why
This revision was automatically updated to reflect the committed changes.
vitalybuka added a commit: rGa496c8be6e63: Revert "[CodeGen]Allow targets to use target specific COPY instructions for….
arsenm added a reverting change: rG4d42e8b5d1fa: Reapply "[CodeGen]Allow targets to use target specific COPY instructions for….Jul 31 2023, 5:15 PM

Large Diff

This large diff affects 106 files. Files without inline comments have been collapsed. Expand All Files

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Diff 544546

llvm/include/llvm/CodeGen/TargetInstrInfo.h

llvm/lib/CodeGen/CalcSpillWeights.cpp

llvm/lib/CodeGen/InlineSpiller.cpp

llvm/lib/CodeGen/LiveRangeEdit.cpp

llvm/lib/CodeGen/LiveRangeShrink.cpp

llvm/lib/CodeGen/RegAllocGreedy.cpp

llvm/lib/CodeGen/SplitKit.h

llvm/lib/CodeGen/SplitKit.cpp

llvm/lib/CodeGen/TargetInstrInfo.cpp

llvm/lib/Target/AMDGPU/AMDGPU.h

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

llvm/lib/Target/AMDGPU/CMakeLists.txt

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

llvm/lib/Target/AMDGPU/SIInstrInfo.h

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/lib/Target/AMDGPU/SIInstructions.td

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll

llvm/test/CodeGen/AMDGPU/amdpal-callable.ll

llvm/test/CodeGen/AMDGPU/bf16.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll

llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll

llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

llvm/test/CodeGen/AMDGPU/collapse-endcf.ll

llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll

llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir

llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll

llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll

llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir

llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir

llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll

llvm/test/CodeGen/AMDGPU/indirect-call.ll

llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/nested-calls.ll

llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll

llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll

llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll

llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll

llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll

llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll

llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir

llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll

llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll

llvm/test/CodeGen/AMDGPU/sibling-call.ll

llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir

llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll

llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir

llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir

llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll

llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll

llvm/test/CodeGen/AMDGPU/spill192.mir

llvm/test/CodeGen/AMDGPU/spill224.mir

llvm/test/CodeGen/AMDGPU/spill288.mir

llvm/test/CodeGen/AMDGPU/spill320.mir

llvm/test/CodeGen/AMDGPU/spill352.mir

llvm/test/CodeGen/AMDGPU/spill384.mir

llvm/test/CodeGen/AMDGPU/stack-realign.ll

llvm/test/CodeGen/AMDGPU/swdev380865.ll

llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll

llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll

llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll

llvm/test/CodeGen/AMDGPU/wave32.ll

llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll

llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll

llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir

llvm/test/CodeGen/Mips/madd-msub.ll

llvm/test/CodeGen/X86/GlobalISel/add-ext.ll

llvm/test/CodeGen/X86/dagcombine-cse.ll

llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll