- User Since
- Apr 29 2019, 11:13 PM (25 w, 18 h)
Added the MIR test.
Avoiding RPO traversal. PHI uses can be circular in some cases.
A minor change in the test case.
Used RPO traversal instead of default MBB traversal + reduced the unit-test.
Fri, Oct 18
Thu, Oct 17
Tue, Oct 8
Sun, Oct 6
incorporated the suggestions + rebase
Tue, Oct 1
You are right, we need to redesign the function shouldRetainSkips, especially in computing the cost. It is not guaranteed that the order of 'From' to 'To' blocks is a fall-through.
There could essentially be a nested control-flow which makes the cost computation a little complex. We can only approximate the number of instructions in the region.
We have talked about it earlier and trying to make the current design more close to how SIInsertSkip works now.
Fri, Sep 27
Thu, Sep 26
Jul 23 2019
Jul 22 2019
Jul 18 2019
updated test/CodeGenOpenCL/builtins-generic-amdgcn.cl to vaildate the address space.
Jul 16 2019
Used TLI.getFrameIndexTy. Thanks.
Jul 12 2019
Added alloca address space.
Jul 11 2019
Jul 10 2019
Jul 9 2019
Jul 5 2019
reused the existing register class' parameters for the new class.
Also ran clang-format to fix the long lines.
Jul 1 2019
Updated the document, AMDGPUUsage.rst with the new metadata information.
Parameterized the existing operand class 'SOP1_1' to accommodate different register classes.
Added explicit check for the register pair in return instruction, 's_setpc_b64' (for nested-calls.ll test)
Jun 28 2019
Jun 27 2019
Jun 25 2019
The compiler generates metadata for the first 48 bytes. I compiled a sample code and verified it. The backend does nothing for the extra bytes now.
I will soon submit the backend patch to generate the new metadata.
Jun 10 2019
simplified the check in the test case.
May 22 2019
Moved the test to CodeGenCUDA directory.