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cdevadas (Christudasan Devadasan)
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User Since
Apr 29 2019, 11:13 PM (160 w, 3 d)

Recent Activity

Wed, May 11

cdevadas added inline comments to D125378: [Attribute] Introduce shuffle attribute to be used for __shfl_sync like cross-lane APIs.
Wed, May 11, 6:37 AM · Restricted Project, Restricted Project, Restricted Project

Sun, May 1

cdevadas added inline comments to D124192: [AMDGPU] Callee must always spill writelane VGPRs.
Sun, May 1, 11:38 PM · Restricted Project, Restricted Project

Fri, Apr 29

cdevadas added inline comments to D124192: [AMDGPU] Callee must always spill writelane VGPRs.
Fri, Apr 29, 11:03 AM · Restricted Project, Restricted Project

Wed, Apr 27

cdevadas updated the diff for D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.

Addressed the review comments.

Wed, Apr 27, 8:30 PM · Restricted Project, Restricted Project
cdevadas added inline comments to D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.
Wed, Apr 27, 8:24 PM · Restricted Project, Restricted Project

Apr 27 2022

cdevadas updated the diff for D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.

Fixed the review comments.
Moved UpdateLaneVGPRDomInstr lambda into a separate function.
Implemented getClearedProperties to clear certain MF properties.
Tes pre-commit + rebase.
Fixed the tied operand cases in certain tests.

Apr 27 2022, 4:32 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.
Apr 27 2022, 3:53 AM · Restricted Project, Restricted Project

Apr 26 2022

cdevadas added inline comments to D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.
Apr 26 2022, 9:22 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124195: [AMDGPU] Separate out custom SGPR spills to VGPR during PEI.
Apr 26 2022, 3:45 AM · Restricted Project, Restricted Project
cdevadas updated the diff for D124193: [AMDGPU] Add WWM reserved VGPRs to lane VGPRs list.

Removed the unwanted comment.

Apr 26 2022, 3:45 AM · Restricted Project, Restricted Project
cdevadas updated the diff for D124192: [AMDGPU] Callee must always spill writelane VGPRs.

Removed unwanted struct declarations.

Apr 26 2022, 3:42 AM · Restricted Project, Restricted Project
cdevadas committed rG8f9dd5e608c0: [AMDGPU] Vector register spill test cleanup (NFC) (authored by cdevadas).
[AMDGPU] Vector register spill test cleanup (NFC)
Apr 26 2022, 12:49 AM · Restricted Project, Restricted Project

Apr 25 2022

cdevadas committed rG16d87efc2ab5: [AMDGPU] Lit test pre-commit changes (NFC) (authored by cdevadas).
[AMDGPU] Lit test pre-commit changes (NFC)
Apr 25 2022, 8:55 AM · Restricted Project, Restricted Project
cdevadas committed rG9f631cf7c650: [AMDGPU] Regenerate lit test pattern (NFC). (authored by cdevadas).
[AMDGPU] Regenerate lit test pattern (NFC).
Apr 25 2022, 8:45 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124195: [AMDGPU] Separate out custom SGPR spills to VGPR during PEI.
Apr 25 2022, 4:20 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124194: [AMDGPU] Correctly set `IsKill` flag for VGPR custom spills in the prolog.
Apr 25 2022, 4:17 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124193: [AMDGPU] Add WWM reserved VGPRs to lane VGPRs list.
Apr 25 2022, 4:15 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D124192: [AMDGPU] Callee must always spill writelane VGPRs.
Apr 25 2022, 4:14 AM · Restricted Project, Restricted Project

Apr 21 2022

cdevadas updated the summary of D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.
Apr 21 2022, 12:21 PM · Restricted Project, Restricted Project
cdevadas requested review of D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs.
Apr 21 2022, 12:18 PM · Restricted Project, Restricted Project
cdevadas requested review of D124195: [AMDGPU] Separate out custom SGPR spills to VGPR during PEI.
Apr 21 2022, 12:16 PM · Restricted Project, Restricted Project
cdevadas requested review of D124194: [AMDGPU] Correctly set `IsKill` flag for VGPR custom spills in the prolog.
Apr 21 2022, 12:16 PM · Restricted Project, Restricted Project
cdevadas requested review of D124193: [AMDGPU] Add WWM reserved VGPRs to lane VGPRs list.
Apr 21 2022, 12:15 PM · Restricted Project, Restricted Project
cdevadas requested review of D124192: [AMDGPU] Callee must always spill writelane VGPRs.
Apr 21 2022, 12:15 PM · Restricted Project, Restricted Project

Apr 20 2022

cdevadas added inline comments to D123525: [AMDGPU] On gfx908, reserve VGPR for AGPR copy based on register budget..
Apr 20 2022, 6:45 PM · Restricted Project, Restricted Project
cdevadas committed rG0d4a49b0f1f7: [AMDGPU] Regenerate lit test pattern (NFC). (authored by cdevadas).
[AMDGPU] Regenerate lit test pattern (NFC).
Apr 20 2022, 10:38 AM · Restricted Project, Restricted Project

Apr 17 2022

cdevadas committed rG34a68037ddb4: [AMDGPU][SIFrameLowering] Refactor custom SGPR spills (NFC). (authored by cdevadas).
[AMDGPU][SIFrameLowering] Refactor custom SGPR spills (NFC).
Apr 17 2022, 1:47 AM · Restricted Project, Restricted Project
cdevadas closed D123666: [AMDGPU][SIFrameLowering] Refactor custom SGPR spills (NFC)..
Apr 17 2022, 1:47 AM · Restricted Project, Restricted Project

Apr 13 2022

cdevadas requested review of D123666: [AMDGPU][SIFrameLowering] Refactor custom SGPR spills (NFC)..
Apr 13 2022, 2:58 AM · Restricted Project, Restricted Project

Apr 12 2022

cdevadas added inline comments to D123651: [AMDGPU][NFC] Organize code around reserving VGPR32 for AGPR copy..
Apr 12 2022, 11:04 PM · Restricted Project, Restricted Project

Apr 8 2022

cdevadas committed rG2c46d067e12c: [AMDGPU][SIMachineFunctionInfo] Code cleanup (NFC). (authored by cdevadas).
[AMDGPU][SIMachineFunctionInfo] Code cleanup (NFC).
Apr 8 2022, 7:13 AM · Restricted Project, Restricted Project

Mar 23 2022

cdevadas added inline comments to D122286: [AMDGPU] Add missing testcase for SGPR to AGPR copy.
Mar 23 2022, 3:43 AM · Restricted Project, Restricted Project

Mar 17 2022

cdevadas added inline comments to D121770: [AMDGPU] Select buffer_atomic_cmpswap* in tblgen.
Mar 17 2022, 9:07 AM · Restricted Project, Restricted Project

Mar 16 2022

cdevadas closed D121795: [AMDGPU][SIFoldOperands] Consider the alignment constraints.

6dd21d1db14f1589f93cb14e572320eaab823f16

Mar 16 2022, 8:01 PM · Restricted Project, Restricted Project
cdevadas committed rG6dd21d1db14f: [AMDGPU][SIFoldOperands] Consider the alignment constraints (authored by cdevadas).
[AMDGPU][SIFoldOperands] Consider the alignment constraints
Mar 16 2022, 7:59 PM · Restricted Project
cdevadas committed rGaf717d4acac8: [AMDGPU][MachineVerifier] Alignment check for fp32 packed math instructions (authored by cdevadas).
[AMDGPU][MachineVerifier] Alignment check for fp32 packed math instructions
Mar 16 2022, 7:57 PM · Restricted Project
cdevadas closed D121794: [AMDGPU][MachineVerifier] Alignment check for fp32 packed math instructions.
Mar 16 2022, 7:57 PM · Restricted Project, Restricted Project
cdevadas requested review of D121795: [AMDGPU][SIFoldOperands] Consider the alignment constraints.
Mar 16 2022, 5:53 AM · Restricted Project, Restricted Project
cdevadas requested review of D121794: [AMDGPU][MachineVerifier] Alignment check for fp32 packed math instructions.
Mar 16 2022, 5:49 AM · Restricted Project, Restricted Project

Mar 14 2022

cdevadas accepted D121491: [AMDGPU] Restrict machine copy propagation from creating unaligned classes.

LGTM except for the typo.

Mar 14 2022, 1:30 PM · Restricted Project, Restricted Project

Mar 12 2022

cdevadas added a comment to D121491: [AMDGPU] Restrict machine copy propagation from creating unaligned classes.

In general, invoking adjustAllocatableRegClass post-regalloc doesn't sound good to me.
I'm in favor of the code that you added to get the aligned regclasses.
But what's the need to adjust the AV operands beforehand? They'll meet the condition as we have the _align2 versions for the superclasses available now.

Mar 12 2022, 12:59 AM · Restricted Project, Restricted Project

Mar 7 2022

cdevadas committed rG0d849b8249e8: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users (authored by cdevadas).
AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users
Mar 7 2022, 8:44 PM · Restricted Project
cdevadas closed D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..
Mar 7 2022, 8:44 PM · Restricted Project, Restricted Project

Mar 4 2022

cdevadas updated the diff for D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..

Used existing 'SIInstrInfo::getRegClass' function to get the RC at OpIdx.

Mar 4 2022, 10:32 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..
Mar 4 2022, 10:03 AM · Restricted Project, Restricted Project
cdevadas added inline comments to D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..
Mar 4 2022, 6:14 AM · Restricted Project, Restricted Project
cdevadas updated the diff for D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..

Addressed Jay's suggestion.

Mar 4 2022, 4:34 AM · Restricted Project, Restricted Project

Mar 3 2022

cdevadas updated the diff for D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..

Removed variadic instruction check.
Desc.OpInfo[OpIdx].RegClass == -1 will catch those invalid cases.

Mar 3 2022, 5:29 PM · Restricted Project, Restricted Project

Mar 2 2022

cdevadas updated the diff for D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..

Used a better name for the function.

Mar 2 2022, 7:05 PM · Restricted Project, Restricted Project
cdevadas added a comment to D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..

What's the reasoning for this? Won't this break chains of REG_SEQUENCE? In particular I do expect to see some REG_SEQUENCE (REG_SEQUENCE), (REG_SEQUENCE) patterns

Mar 2 2022, 8:27 AM · Restricted Project, Restricted Project
cdevadas requested review of D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users..
Mar 2 2022, 6:51 AM · Restricted Project, Restricted Project

Feb 25 2022

cdevadas requested review of D120566: [OpenCL][AMDGPU]: Do not allow a call to kernel.
Feb 25 2022, 6:47 AM · Restricted Project

Jan 29 2022

cdevadas added a comment to D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908.

I guess disallowing direct agpr -> agpr copy for gfx908 early from instruction selection would be a better fix. I am anyway working on a patch to avoid direct sgpr -> agpr copies. In that way, we could avoid Scavenger altogether while lowering COPY instructions.

Note though copies are created in many passes.

Jan 29 2022, 6:16 AM · Restricted Project

Jan 28 2022

cdevadas added a comment to D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908.

Anyway, inability to run kernels at maximum occupancy is a show stopper itself.

This is practically impossible if you are using mfma instructions anyway

This might be OK, but consider two things: 1) you are not checking agprs are unused (easy to fix) 2) there are some mfma instructions which only need a128. I don't believe there are kernels which fit that budget, but I cannot blidnly deny it too.

I.e. I would prefer to fail compilation rather than reserving v32.

Jan 28 2022, 11:07 AM · Restricted Project

Jan 17 2022

cdevadas committed rG56a5d78893e6: [AMDGPU] Disable optimizeEndCf at -O0 (authored by cdevadas).
[AMDGPU] Disable optimizeEndCf at -O0
Jan 17 2022, 11:51 PM
cdevadas closed D116819: [AMDGPU] Disable optimizeEndCf at -O0.
Jan 17 2022, 11:50 PM · Restricted Project

Jan 10 2022

cdevadas added a comment to D116819: [AMDGPU] Disable optimizeEndCf at -O0.

I think this is an extreme interpretation of optnone. This is a minor optimization which happens as part of lowering. The fact we do this as a separate step is just an artifact of how we happen to lower control flow. It's not strictly true that no optimizations occur at -O0, especially if they are cheap and provide benefit

I assume it is good to have a way to disable it with -O0 just for bug bisecting.

Jan 10 2022, 11:21 AM · Restricted Project

Jan 7 2022

cdevadas added inline comments to D116819: [AMDGPU] Disable optimizeEndCf at -O0.
Jan 7 2022, 5:42 PM · Restricted Project
cdevadas requested review of D116819: [AMDGPU] Disable optimizeEndCf at -O0.
Jan 7 2022, 9:32 AM · Restricted Project

Jan 5 2022

cdevadas committed rG50b5b367c1ae: [AMDGPU] Iterate LoweredEndCf in the reverse order (authored by cdevadas).
[AMDGPU] Iterate LoweredEndCf in the reverse order
Jan 5 2022, 9:28 PM
cdevadas closed D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.
Jan 5 2022, 9:27 PM · Restricted Project
cdevadas updated the diff for D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.

Pre-committed the regenerated test collapse-endcf.mir separately.
Rebased the test case and autogenerated the pattern for the new test.

Jan 5 2022, 9:37 AM · Restricted Project
cdevadas committed rGe7b89f322204: [AMDGPU] Regenerate test checks in collapse-endcf.mir. NFC (authored by cdevadas).
[AMDGPU] Regenerate test checks in collapse-endcf.mir. NFC
Jan 5 2022, 9:20 AM

Jan 3 2022

cdevadas updated the diff for D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.

Incorporated Jay's suggestion.

Jan 3 2022, 10:44 PM · Restricted Project
cdevadas added a comment to D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.

What was the effect of inserting multiple branch instructions? Did it fail MIR verification?

Jan 3 2022, 4:21 AM · Restricted Project

Dec 25 2021

cdevadas updated the diff for D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.

lit test clean up.

Dec 25 2021, 1:55 AM · Restricted Project

Dec 24 2021

cdevadas requested review of D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order.
Dec 24 2021, 1:54 PM · Restricted Project

Dec 20 2021

cdevadas added a comment to D115996: [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info.

Can we rip out this special "spill" handling since D109301 @cdevadas

I has unsolved problem with partial tuple spill. There is no partial copy.

I'm not sure how we are going to handle this partial copy differently.
The equivalent for partial-copy during regalloc would be possible only if the tryInstructionSplit inserts partial copy followed by the InlineSpiller handling the leftover tuple spills.
Currently, the former doesn't handle partial copy and the latter doesn't insert subrange tuple spills/restores.
Even if they are equipped to handle partial copy and spill, how do these independent functions communicate each other the exact tuple subrange that the other suppose to handle?

Dec 20 2021, 10:39 AM · Restricted Project

Dec 10 2021

cdevadas closed D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Merged D115439 with cf58b9ce98043d4c9af5ffb5b47a18009b145b5b

Dec 10 2021, 2:16 AM · Restricted Project
cdevadas committed rGcf58b9ce9804: [AMDGPU] Add AV class spill pseudo instructions (authored by cdevadas).
[AMDGPU] Add AV class spill pseudo instructions
Dec 10 2021, 12:14 AM
cdevadas closed D115439: [AMDGPU] Add AV class spill pseudo instructions.
Dec 10 2021, 12:13 AM · Restricted Project

Dec 9 2021

cdevadas updated the diff for D115439: [AMDGPU] Add AV class spill pseudo instructions.

Considered the max size for AV spills the same as AGPRs.

Dec 9 2021, 8:36 AM · Restricted Project
cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

This might have caused all OpenMP offload tests (with math) to fail for gfx908/90a. @arsenm has a reproducer.

Dec 9 2021, 3:51 AM · Restricted Project
cdevadas requested review of D115439: [AMDGPU] Add AV class spill pseudo instructions.
Dec 9 2021, 3:50 AM · Restricted Project

Dec 1 2021

cdevadas committed rG399b7de0ea34: [AMDGPU] Add a regclass flag for scalar registers (authored by cdevadas).
[AMDGPU] Add a regclass flag for scalar registers
Dec 1 2021, 8:41 PM
cdevadas closed D110053: [AMDGPU] Add a regclass flag for scalar registers.
Dec 1 2021, 8:40 PM · Restricted Project
cdevadas updated the diff for D110053: [AMDGPU] Add a regclass flag for scalar registers.

Rebase after D110762

Dec 1 2021, 1:36 AM · Restricted Project

Nov 29 2021

cdevadas committed rG5297cbf04532: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc (authored by cdevadas).
[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc
Nov 29 2021, 7:22 PM
cdevadas closed D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.
Nov 29 2021, 7:22 PM · Restricted Project

Nov 25 2021

cdevadas committed rG654c89d85a51: [AMDGPU] Make vector superclasses allocatable (authored by cdevadas).
[AMDGPU] Make vector superclasses allocatable
Nov 25 2021, 9:50 PM
cdevadas closed D109300: [AMDGPU] Make vector superclasses allocatable.
Nov 25 2021, 9:50 PM · Restricted Project

Nov 24 2021

cdevadas updated the diff for D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Suggestions addressed.

Nov 24 2021, 10:51 PM · Restricted Project
cdevadas updated the diff for D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Addressed the review comments.

Nov 24 2021, 9:11 AM · Restricted Project

Nov 21 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

The combination of Regcoalescer, superclass copy (tryInstructionSplit), and Spiller during regalloc introduce a superclass spill at extreme pressure situations.
Lit test llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll demonstrates that.
This mostly happens for gfx908 where we need a copy for AGPR to VGPR. I didn’t see this happening for gfx90a.

Nov 21 2021, 11:03 PM · Restricted Project

Nov 17 2021

cdevadas updated the diff for D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Retained SpillVGPRToAGPR implementation at frame lowering to handle the partial tuple spills to registers that are missed during regalloc.
Fixed a broken case in function spillVGPRtoAGPR.
Added more tests.

Nov 17 2021, 11:42 AM · Restricted Project

Nov 16 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

In fact restoring into av superclass also seems problematic. I believe we have agreed all the code here only work correctly if we have no actual av registers past selection.

Nov 16 2021, 1:43 AM · Restricted Project

Nov 15 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

You cannot optimize it in pre-emit peephole as it will create new hazards which will not be handled.

I missed your comment earlier, sorry.
Yes, trying to optimize them at late phases would be risky. It should be done no later than Post-RA scheduler.
But I am not sure we can correctly optimize the subreg tuple copies when strict alignment constraints exist.
I guess, after virtregrewriter the sub-registers are no longer tied together. Correct me if I'm wrong.

Nov 15 2021, 3:30 AM · Restricted Project

Nov 10 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Recently added lit test llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll has extreme pressure situations and the regalloc ends up inserting copies between virtual registers of identical regclasses.
It’s due to the allocator’s choice to spill the AGPRs and later restore them into its superclass.

Nov 10 2021, 4:57 AM · Restricted Project

Nov 5 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

I still do not think we can do it without solving partial spill/copy issue. At least not for wide tuples.

Even today we don't generate partial spills.
I am not sure how this patch is going to add any incremental impact on existing partial spill behavior.

What do you mean? The code you are removing does it and spill-to-agpr-partial.mir in particular tests it.

Nov 5 2021, 1:50 AM · Restricted Project

Nov 4 2021

cdevadas added a comment to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

I still do not think we can do it without solving partial spill/copy issue. At least not for wide tuples.

Nov 4 2021, 12:53 PM · Restricted Project
cdevadas updated the diff for D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.

Rebase + converted AV spills into VGPR spills by introducing appropriate copies in between.
Added a test case for AV spills.

Nov 4 2021, 12:17 PM · Restricted Project
cdevadas added inline comments to D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc.
Nov 4 2021, 5:37 AM · Restricted Project

Oct 31 2021

cdevadas updated the diff for D109300: [AMDGPU] Make vector superclasses allocatable.

Removed the workaround post-Selection that forced a Vreg class for the occurrences of AV classes. With D112323, we no longer choose AV superclasses during instruction selection. They either become a Vreg class or an Areg class.

Oct 31 2021, 3:01 AM · Restricted Project

Oct 30 2021

cdevadas committed rGaa2d3b59ce75: GlobalISel/Utils: Use incoming regbank while constraining the superclasses (authored by cdevadas).
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
Oct 30 2021, 4:22 AM
cdevadas closed D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.
Oct 30 2021, 4:22 AM · Restricted Project

Oct 29 2021

cdevadas updated the diff for D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.

Addressed review comments.
(Used getAllocatableClass + a fix in getConstrainedRegClassForOperand to avoid a crash if regbank is not yet selected)

Oct 29 2021, 1:05 PM · Restricted Project

Oct 22 2021

cdevadas updated the diff for D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.

Comments addressed.

Oct 22 2021, 11:59 AM · Restricted Project
cdevadas added a comment to D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.

It's not accurate to say it would lead to incorrect codegen, we would just prefer to pick the classes beforehand rather than let the allocator decide until it needs to split live ranges

Oct 22 2021, 11:17 AM · Restricted Project
cdevadas added a comment to D109300: [AMDGPU] Make vector superclasses allocatable.

Should we restrain the MIOperand regclasses based on the incoming regbank when the corresponding RC in the instruction definition is its superclass?

Yes, I'm surprised this doesn't happen already. Just the instruction definition can be ambiguous

Oct 22 2021, 9:49 AM · Restricted Project
cdevadas requested review of D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses.
Oct 22 2021, 9:09 AM · Restricted Project