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cdevadas (Christudasan Devadasan)
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User Since
Apr 29 2019, 11:13 PM (25 w, 18 h)

Recent Activity

Today

cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Added the MIR test.

Tue, Oct 22, 10:46 AM · Restricted Project

Yesterday

cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Avoiding RPO traversal. PHI uses can be circular in some cases.

Mon, Oct 21, 10:23 PM · Restricted Project
cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

A minor change in the test case.

Mon, Oct 21, 9:30 AM · Restricted Project
cdevadas updated the diff for D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..

Used RPO traversal instead of default MBB traversal + reduced the unit-test.

Mon, Oct 21, 9:22 AM · Restricted Project

Fri, Oct 18

cdevadas added inline comments to D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..
Fri, Oct 18, 11:16 AM · Restricted Project
cdevadas created D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies..
Fri, Oct 18, 10:11 AM · Restricted Project

Thu, Oct 17

cdevadas committed rL375200: Request commit access for cdevadas.
Request commit access for cdevadas
Thu, Oct 17, 10:21 PM

Tue, Oct 8

cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Tue, Oct 8, 10:09 AM · Restricted Project

Sun, Oct 6

cdevadas updated the diff for D68092: [AMDGPU] Invert the handling of skip insertion..

incorporated the suggestions + rebase

Sun, Oct 6, 8:30 AM · Restricted Project

Tue, Oct 1

cdevadas added a comment to D68092: [AMDGPU] Invert the handling of skip insertion..

You are right, we need to redesign the function shouldRetainSkips, especially in computing the cost. It is not guaranteed that the order of 'From' to 'To' blocks is a fall-through.
There could essentially be a nested control-flow which makes the cost computation a little complex. We can only approximate the number of instructions in the region.
We have talked about it earlier and trying to make the current design more close to how SIInsertSkip works now.

Tue, Oct 1, 6:17 AM · Restricted Project

Fri, Sep 27

cdevadas added inline comments to D68092: [AMDGPU] Invert the handling of skip insertion..
Fri, Sep 27, 6:05 AM · Restricted Project

Thu, Sep 26

cdevadas retitled D68092: [AMDGPU] Invert the handling of skip insertion. from Invert the handling of skip insertion. to [AMDGPU] Invert the handling of skip insertion..
Thu, Sep 26, 10:38 AM · Restricted Project
cdevadas created D68092: [AMDGPU] Invert the handling of skip insertion..
Thu, Sep 26, 10:37 AM · Restricted Project

Jul 23 2019

cdevadas committed rG7282d68314e9: moved the skip branch insertion code for correctness upfront during CF lowering (authored by cdevadas).
moved the skip branch insertion code for correctness upfront during CF lowering
Jul 23 2019, 5:56 AM

Jul 22 2019

cdevadas committed rG8c5e6fa6575a: Updated the signature for some stack related intrinsics (CLANG) (authored by cdevadas).
Updated the signature for some stack related intrinsics (CLANG)
Jul 22 2019, 5:54 AM
cdevadas committed rL366683: Updated the signature for some stack related intrinsics (CLANG).
Updated the signature for some stack related intrinsics (CLANG)
Jul 22 2019, 5:50 AM
cdevadas closed D64563: Updated the signature for some stack related intrinsics (CLANG).
Jul 22 2019, 5:50 AM · Restricted Project, Restricted Project
cdevadas committed rG006cf8c03d77: Added address-space mangling for stack related intrinsics (authored by cdevadas).
Added address-space mangling for stack related intrinsics
Jul 22 2019, 5:47 AM
cdevadas committed rL366679: Added address-space mangling for stack related intrinsics.
Added address-space mangling for stack related intrinsics
Jul 22 2019, 5:46 AM
cdevadas closed D64561: Add address-space mangling for stack related intrinsics.
Jul 22 2019, 5:46 AM · Restricted Project

Jul 18 2019

cdevadas updated the diff for D64563: Updated the signature for some stack related intrinsics (CLANG).

updated test/CodeGenOpenCL/builtins-generic-amdgcn.cl to vaildate the address space.

Jul 18 2019, 12:19 PM · Restricted Project, Restricted Project

Jul 16 2019

cdevadas updated the diff for D64561: Add address-space mangling for stack related intrinsics.

Used TLI.getFrameIndexTy. Thanks.

Jul 16 2019, 6:20 AM · Restricted Project

Jul 12 2019

cdevadas updated the diff for D64563: Updated the signature for some stack related intrinsics (CLANG).

Added alloca address space.

Jul 12 2019, 5:45 AM · Restricted Project, Restricted Project
cdevadas updated the diff for D64561: Add address-space mangling for stack related intrinsics.

Added allocaAddressSpace.

Jul 12 2019, 5:42 AM · Restricted Project

Jul 11 2019

cdevadas created D64563: Updated the signature for some stack related intrinsics (CLANG).
Jul 11 2019, 6:04 AM · Restricted Project, Restricted Project
cdevadas created D64561: Add address-space mangling for stack related intrinsics.
Jul 11 2019, 5:57 AM · Restricted Project

Jul 10 2019

cdevadas committed rG18ba9d60771c: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and… (authored by cdevadas).
[AMDGPU] Increased the number of implicit argument bytes for both OpenCL and…
Jul 10 2019, 8:13 AM
cdevadas committed rL365643: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and….
[AMDGPU] Increased the number of implicit argument bytes for both OpenCL and…
Jul 10 2019, 8:10 AM
cdevadas closed D63756: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and HIP (CLANG)..
Jul 10 2019, 8:10 AM · Restricted Project, Restricted Project

Jul 9 2019

cdevadas committed rGb2d24bd5400d: [AMDGPU] Created a sub-register class for the return address operand in the… (authored by cdevadas).
[AMDGPU] Created a sub-register class for the return address operand in the…
Jul 9 2019, 9:51 AM
cdevadas committed rL365512: [AMDGPU] Created a sub-register class for the return address operand in the….
[AMDGPU] Created a sub-register class for the return address operand in the…
Jul 9 2019, 9:48 AM
cdevadas closed D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction..
Jul 9 2019, 9:48 AM · Restricted Project

Jul 5 2019

cdevadas added a comment to D63756: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and HIP (CLANG)..

The backend changes, D63886 are in the upstream now with revision rL365217.
Please review this patch.

Jul 5 2019, 8:54 PM · Restricted Project, Restricted Project
cdevadas committed rG652ad423bb54: [NFC] A test commit to check the access permission. Removed a blank line. (authored by cdevadas).
[NFC] A test commit to check the access permission. Removed a blank line.
Jul 5 2019, 10:10 AM
cdevadas committed rL365223: [NFC] A test commit to check the access permission. Removed a blank line..
[NFC] A test commit to check the access permission. Removed a blank line.
Jul 5 2019, 10:07 AM
cdevadas updated the diff for D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction..

reused the existing register class' parameters for the new class.
Also ran clang-format to fix the long lines.

Jul 5 2019, 8:27 AM · Restricted Project

Jul 1 2019

cdevadas updated the diff for D63886: [AMDGPU] Added a new metadata for multi grid sync implicit argument..

Updated the document, AMDGPUUsage.rst with the new metadata information.

Jul 1 2019, 11:30 PM · Restricted Project
cdevadas updated the diff for D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction..

Parameterized the existing operand class 'SOP1_1' to accommodate different register classes.
Added explicit check for the register pair in return instruction, 's_setpc_b64' (for nested-calls.ll test)

Jul 1 2019, 2:58 AM · Restricted Project

Jun 28 2019

cdevadas added a comment to D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction..

Hi Matt,

Jun 28 2019, 3:33 AM · Restricted Project
cdevadas created D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction..
Jun 28 2019, 3:26 AM · Restricted Project

Jun 27 2019

cdevadas added a comment to D63756: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and HIP (CLANG)..

I have created the review for adding the metadata in the backend. https://reviews.llvm.org/D63886
Marking the current review depended on D63886.

Jun 27 2019, 9:50 AM · Restricted Project, Restricted Project
cdevadas created D63886: [AMDGPU] Added a new metadata for multi grid sync implicit argument..
Jun 27 2019, 9:29 AM · Restricted Project

Jun 25 2019

cdevadas added a comment to D63756: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and HIP (CLANG)..

Hi Sam,
The compiler generates metadata for the first 48 bytes. I compiled a sample code and verified it. The backend does nothing for the extra bytes now.
I will soon submit the backend patch to generate the new metadata.

Jun 25 2019, 8:52 AM · Restricted Project, Restricted Project
cdevadas created D63765: [AMDGPU] Fix Livereg computation during epilogue insertion.
Jun 25 2019, 6:27 AM · Restricted Project
cdevadas created D63756: [AMDGPU] Increased the number of implicit argument bytes for both OpenCL and HIP (CLANG)..
Jun 25 2019, 1:00 AM · Restricted Project, Restricted Project

Jun 10 2019

cdevadas updated the diff for D62244: [AMDGPU] Enable the implicit arguments for HIP (CLANG).

simplified the check in the test case.

Jun 10 2019, 10:29 PM · Restricted Project, Restricted Project

May 22 2019

cdevadas updated the diff for D62244: [AMDGPU] Enable the implicit arguments for HIP (CLANG).

Moved the test to CodeGenCUDA directory.

May 22 2019, 10:30 PM · Restricted Project, Restricted Project
cdevadas created D62244: [AMDGPU] Enable the implicit arguments for HIP (CLANG).
May 22 2019, 4:08 AM · Restricted Project, Restricted Project