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Differential D156144

[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
ClosedPublic

Authored by craig.topper on Jul 24 2023, 10:23 AM.

Details

Reviewers
asb
wangpc
mgudim
reames
Commits
rG5ff5dac8528a: [RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
Summary

If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 through the
select to enable more optimizations.

We could generalize this to other binary operators with identical
conditions, but those are usually caught before we legalize the select.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 24 2023, 10:23 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2023, 10:23 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 27 others. · View Herald Transcript
craig.topper requested review of this revision.Jul 24 2023, 10:23 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2023, 10:23 AM
Herald added subscribers: eopXD, MaskRay. · View Herald Transcript
craig.topper added a child revision: D156153: [RISCV] Generalize combineAddOfBooleanXor to support any boolean not just setcc..Jul 24 2023, 10:42 AM
Harbormaster completed remote builds in B247732: Diff 543620.Jul 24 2023, 5:32 PM
asb accepted this revision.Jul 25 2023, 6:01 AM

LGTM.

This revision is now accepted and ready to land.Jul 25 2023, 6:01 AM
This revision was landed with ongoing or failed builds.Jul 25 2023, 9:03 AM
Closed by commit rG5ff5dac8528a: [RISCV] Add simple DAG combine to pull xor with 1 through select_cc. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG5ff5dac8528a: [RISCV] Add simple DAG combine to pull xor with 1 through select_cc..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
13 lines
test/
CodeGen/
RISCV/
60 lines
12 lines
4 lines
24 lines

Diff 543620

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===// //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 12,881 Lines • ▼ Show 20 Lines if (!Subtarget.hasShortForwardBranchOpt()) {
isNullConstant(RHS)) { isNullConstant(RHS)) {
// freeze it to be safe. // freeze it to be safe.
LHS = DAG.getFreeze(LHS); LHS = DAG.getFreeze(LHS);
SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, ISD::CondCode::SETEQ); SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, ISD::CondCode::SETEQ);
return DAG.getNode(ISD::ADD, DL, VT, LHS, C); return DAG.getNode(ISD::ADD, DL, VT, LHS, C);
} }
} }
// If both true/false are an xor with 1, pull through the select.
// This can occur after op legalization if both operands are setccs that
// require an xor to invert.
// FIXME: Generalize to other binary ops with identical operand?
if (TrueV.getOpcode() == ISD::XOR && FalseV.getOpcode() == ISD::XOR &&
TrueV.getOperand(1) == FalseV.getOperand(1) &&
isOneConstant(TrueV.getOperand(1)) &&
TrueV.hasOneUse() && FalseV.hasOneUse()) {
SDValue NewSel = DAG.getNode(RISCVISD::SELECT_CC, DL, VT, LHS, RHS, CC,
TrueV.getOperand(0), FalseV.getOperand(0));
return DAG.getNode(ISD::XOR, DL, VT, NewSel, TrueV.getOperand(1));
}
return SDValue(); return SDValue();
} }
case RISCVISD::BR_CC: { case RISCVISD::BR_CC: {
SDValue LHS = N->getOperand(1); SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2); SDValue RHS = N->getOperand(2);
SDValue CC = N->getOperand(3); SDValue CC = N->getOperand(3);
SDLoc DL(N); SDLoc DL(N);
▲ Show 20 Lines • Show All 4,560 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/atomic-rmw.ll

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Show First 20 Lines • Show All 15,013 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB205_5 ; RV32I-NEXT: j .LBB205_5
; RV32I-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB205_5: # %atomicrmw.start ; RV32I-NEXT: .LBB205_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB205_1 ; RV32I-NEXT: beqz a0, .LBB205_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB205_1 ; RV32I-NEXT: j .LBB205_1
; RV32I-NEXT: .LBB205_7: # %atomicrmw.end ; RV32I-NEXT: .LBB205_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
Show All 35 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB205_5 ; RV32IA-NEXT: j .LBB205_5
; RV32IA-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB205_1 ; RV32IA-NEXT: beqz a0, .LBB205_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB205_1 ; RV32IA-NEXT: j .LBB205_1
; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB206_5 ; RV32I-NEXT: j .LBB206_5
; RV32I-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB206_5: # %atomicrmw.start ; RV32I-NEXT: .LBB206_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB206_1 ; RV32I-NEXT: beqz a0, .LBB206_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB206_1 ; RV32I-NEXT: j .LBB206_1
; RV32I-NEXT: .LBB206_7: # %atomicrmw.end ; RV32I-NEXT: .LBB206_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB206_5 ; RV32IA-NEXT: j .LBB206_5
; RV32IA-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB206_1 ; RV32IA-NEXT: beqz a0, .LBB206_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB206_1 ; RV32IA-NEXT: j .LBB206_1
; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB207_5 ; RV32I-NEXT: j .LBB207_5
; RV32I-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB207_5: # %atomicrmw.start ; RV32I-NEXT: .LBB207_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB207_1 ; RV32I-NEXT: beqz a0, .LBB207_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB207_1 ; RV32I-NEXT: j .LBB207_1
; RV32I-NEXT: .LBB207_7: # %atomicrmw.end ; RV32I-NEXT: .LBB207_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
Show All 35 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB207_5 ; RV32IA-NEXT: j .LBB207_5
; RV32IA-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB207_1 ; RV32IA-NEXT: beqz a0, .LBB207_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB207_1 ; RV32IA-NEXT: j .LBB207_1
; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB208_5 ; RV32I-NEXT: j .LBB208_5
; RV32I-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB208_5: # %atomicrmw.start ; RV32I-NEXT: .LBB208_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB208_1 ; RV32I-NEXT: beqz a0, .LBB208_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB208_1 ; RV32I-NEXT: j .LBB208_1
; RV32I-NEXT: .LBB208_7: # %atomicrmw.end ; RV32I-NEXT: .LBB208_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
Show All 35 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB208_5 ; RV32IA-NEXT: j .LBB208_5
; RV32IA-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB208_1 ; RV32IA-NEXT: beqz a0, .LBB208_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB208_1 ; RV32IA-NEXT: j .LBB208_1
; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB209_5 ; RV32I-NEXT: j .LBB209_5
; RV32I-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB209_5: # %atomicrmw.start ; RV32I-NEXT: .LBB209_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB209_1 ; RV32I-NEXT: beqz a0, .LBB209_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB209_1 ; RV32I-NEXT: j .LBB209_1
; RV32I-NEXT: .LBB209_7: # %atomicrmw.end ; RV32I-NEXT: .LBB209_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB209_5 ; RV32IA-NEXT: j .LBB209_5
; RV32IA-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB209_1 ; RV32IA-NEXT: beqz a0, .LBB209_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB209_1 ; RV32IA-NEXT: j .LBB209_1
; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB215_5 ; RV32I-NEXT: j .LBB215_5
; RV32I-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB215_5: # %atomicrmw.start ; RV32I-NEXT: .LBB215_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB215_1 ; RV32I-NEXT: beqz a0, .LBB215_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB215_1 ; RV32I-NEXT: j .LBB215_1
; RV32I-NEXT: .LBB215_7: # %atomicrmw.end ; RV32I-NEXT: .LBB215_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB215_5 ; RV32IA-NEXT: j .LBB215_5
; RV32IA-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB215_1 ; RV32IA-NEXT: beqz a0, .LBB215_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB215_1 ; RV32IA-NEXT: j .LBB215_1
; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB216_5 ; RV32I-NEXT: j .LBB216_5
; RV32I-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB216_5: # %atomicrmw.start ; RV32I-NEXT: .LBB216_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB216_1 ; RV32I-NEXT: beqz a0, .LBB216_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB216_1 ; RV32I-NEXT: j .LBB216_1
; RV32I-NEXT: .LBB216_7: # %atomicrmw.end ; RV32I-NEXT: .LBB216_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB216_5 ; RV32IA-NEXT: j .LBB216_5
; RV32IA-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB216_1 ; RV32IA-NEXT: beqz a0, .LBB216_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB216_1 ; RV32IA-NEXT: j .LBB216_1
; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB217_5 ; RV32I-NEXT: j .LBB217_5
; RV32I-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB217_5: # %atomicrmw.start ; RV32I-NEXT: .LBB217_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB217_1 ; RV32I-NEXT: beqz a0, .LBB217_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB217_1 ; RV32I-NEXT: j .LBB217_1
; RV32I-NEXT: .LBB217_7: # %atomicrmw.end ; RV32I-NEXT: .LBB217_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB217_5 ; RV32IA-NEXT: j .LBB217_5
; RV32IA-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB217_1 ; RV32IA-NEXT: beqz a0, .LBB217_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB217_1 ; RV32IA-NEXT: j .LBB217_1
; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB218_5 ; RV32I-NEXT: j .LBB218_5
; RV32I-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB218_5: # %atomicrmw.start ; RV32I-NEXT: .LBB218_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB218_1 ; RV32I-NEXT: beqz a0, .LBB218_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB218_1 ; RV32I-NEXT: j .LBB218_1
; RV32I-NEXT: .LBB218_7: # %atomicrmw.end ; RV32I-NEXT: .LBB218_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
Show All 35 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB218_5 ; RV32IA-NEXT: j .LBB218_5
; RV32IA-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB218_1 ; RV32IA-NEXT: beqz a0, .LBB218_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB218_1 ; RV32IA-NEXT: j .LBB218_1
; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB219_5 ; RV32I-NEXT: j .LBB219_5
; RV32I-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB219_5: # %atomicrmw.start ; RV32I-NEXT: .LBB219_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB219_1 ; RV32I-NEXT: beqz a0, .LBB219_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB219_1 ; RV32I-NEXT: j .LBB219_1
; RV32I-NEXT: .LBB219_7: # %atomicrmw.end ; RV32I-NEXT: .LBB219_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
Show All 35 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB219_5 ; RV32IA-NEXT: j .LBB219_5
; RV32IA-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB219_1 ; RV32IA-NEXT: beqz a0, .LBB219_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB219_1 ; RV32IA-NEXT: j .LBB219_1
; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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llvm/test/CodeGen/RISCV/atomic-signext.ll

Show First 20 Lines • Show All 3,312 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB44_5 ; RV32I-NEXT: j .LBB44_5
; RV32I-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB44_5: # %atomicrmw.start ; RV32I-NEXT: .LBB44_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB44_1 ; RV32I-NEXT: beqz a0, .LBB44_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_7: # %atomicrmw.end ; RV32I-NEXT: .LBB44_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB44_5 ; RV32IA-NEXT: j .LBB44_5
; RV32IA-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB44_1 ; RV32IA-NEXT: beqz a0, .LBB44_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB44_1 ; RV32IA-NEXT: j .LBB44_1
; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB46_5 ; RV32I-NEXT: j .LBB46_5
; RV32I-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB46_5: # %atomicrmw.start ; RV32I-NEXT: .LBB46_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: bnez a0, .LBB46_1 ; RV32I-NEXT: beqz a0, .LBB46_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_7: # %atomicrmw.end ; RV32I-NEXT: .LBB46_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB46_5 ; RV32IA-NEXT: j .LBB46_5
; RV32IA-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4 ; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: bnez a0, .LBB46_1 ; RV32IA-NEXT: beqz a0, .LBB46_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB46_1 ; RV32IA-NEXT: j .LBB46_1
; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
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llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

Show First 20 Lines • Show All 472 Lines • ▼ Show 20 Lines
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_1: # %atomicrmw.start ; RV32I-NEXT: .LBB3_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32I-NEXT: sltu a0, a5, s1 ; RV32I-NEXT: sltu a0, a5, s1
; RV32I-NEXT: .LBB3_2: # %atomicrmw.start ; RV32I-NEXT: .LBB3_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a1, a4, 1 ; RV32I-NEXT: addi a1, a4, 1
; RV32I-NEXT: seqz a2, a1 ; RV32I-NEXT: seqz a2, a1
; RV32I-NEXT: add a3, a5, a2 ; RV32I-NEXT: add a3, a5, a2
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: li a5, 5 ; RV32I-NEXT: li a5, 5
Show All 36 Lines
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB3_3 ; RV32IA-NEXT: j .LBB3_3
; RV32IA-NEXT: .LBB3_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB3_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32IA-NEXT: sltu a0, a5, s1 ; RV32IA-NEXT: sltu a0, a5, s1
; RV32IA-NEXT: .LBB3_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB3_2: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a1, a4, 1 ; RV32IA-NEXT: addi a1, a4, 1
; RV32IA-NEXT: seqz a2, a1 ; RV32IA-NEXT: seqz a2, a1
; RV32IA-NEXT: add a3, a5, a2 ; RV32IA-NEXT: add a3, a5, a2
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a0, a0, -1 ; RV32IA-NEXT: addi a0, a0, -1
; RV32IA-NEXT: and a2, a0, a1 ; RV32IA-NEXT: and a2, a0, a1
; RV32IA-NEXT: and a3, a0, a3 ; RV32IA-NEXT: and a3, a0, a3
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: li a4, 5 ; RV32IA-NEXT: li a4, 5
; RV32IA-NEXT: li a5, 5 ; RV32IA-NEXT: li a5, 5
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llvm/test/CodeGen/RISCV/condops.ll

Show First 20 Lines • Show All 1,258 Lines • ▼ Show 20 Lines
} }
define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setge: ; RV32I-LABEL: setge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB24_2 ; RV32I-NEXT: beq a1, a3, .LBB24_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a1, a3 ; RV32I-NEXT: slt a0, a1, a3
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB24_3
; RV32I-NEXT: beqz a0, .LBB24_3
; RV32I-NEXT: j .LBB24_4 ; RV32I-NEXT: j .LBB24_4
; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: sltu a0, a0, a2 ; RV32I-NEXT: sltu a0, a0, a2
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB24_4
; RV32I-NEXT: bnez a0, .LBB24_4
; RV32I-NEXT: .LBB24_3: ; RV32I-NEXT: .LBB24_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB24_4: ; RV32I-NEXT: .LBB24_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
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} }
define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setle: ; RV32I-LABEL: setle:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB26_2 ; RV32I-NEXT: beq a1, a3, .LBB26_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a3, a1 ; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB26_3
; RV32I-NEXT: beqz a0, .LBB26_3
; RV32I-NEXT: j .LBB26_4 ; RV32I-NEXT: j .LBB26_4
; RV32I-NEXT: .LBB26_2: ; RV32I-NEXT: .LBB26_2:
; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB26_4
; RV32I-NEXT: bnez a0, .LBB26_4
; RV32I-NEXT: .LBB26_3: ; RV32I-NEXT: .LBB26_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB26_4: ; RV32I-NEXT: .LBB26_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
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} }
define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setuge: ; RV32I-LABEL: setuge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB28_2 ; RV32I-NEXT: beq a1, a3, .LBB28_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a1, a3 ; RV32I-NEXT: sltu a0, a1, a3
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB28_3
; RV32I-NEXT: beqz a0, .LBB28_3
; RV32I-NEXT: j .LBB28_4 ; RV32I-NEXT: j .LBB28_4
; RV32I-NEXT: .LBB28_2: ; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: sltu a0, a0, a2 ; RV32I-NEXT: sltu a0, a0, a2
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB28_4
; RV32I-NEXT: bnez a0, .LBB28_4
; RV32I-NEXT: .LBB28_3: ; RV32I-NEXT: .LBB28_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB28_4: ; RV32I-NEXT: .LBB28_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
} }
define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setule: ; RV32I-LABEL: setule:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB30_2 ; RV32I-NEXT: beq a1, a3, .LBB30_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a3, a1 ; RV32I-NEXT: sltu a0, a3, a1
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: bnez a0, .LBB30_3
; RV32I-NEXT: beqz a0, .LBB30_3
; RV32I-NEXT: j .LBB30_4 ; RV32I-NEXT: j .LBB30_4
; RV32I-NEXT: .LBB30_2: ; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: beqz a0, .LBB30_4
; RV32I-NEXT: bnez a0, .LBB30_4
; RV32I-NEXT: .LBB30_3: ; RV32I-NEXT: .LBB30_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB30_4: ; RV32I-NEXT: .LBB30_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
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