[RISCV] Enable multiversion function

[BeMg]

Summary

Emit the IFUNC resovler for function multi-version

[BeMg]

Rebase and update testcase

clang/include/clang/Basic/TargetInfo.h

   /// Determine whether the given target feature is read only.
   bool isReadOnlyFeature(StringRef Feature) const {
     return ReadOnlyFeatures.count(Feature);
   }
 
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
   bool supportsMultiVersioning() const {
-    return getTriple().isX86() || getTriple().isAArch64();
+    return getTriple().isX86() || getTriple().isAArch64() || getTriple().isRISCV();
   }
 
   /// Identify whether this target supports IFuncs.
   bool supportsIFunc() const {
     return getTriple().isOSBinFormatELF() &&
            ((getTriple().isOSLinux() && !getTriple().isMusl()) ||
             getTriple().isOSFreeBSD());
   }

clang/lib/CodeGen/CodeGenFunction.h

public:
   void EmitMultiVersionResolver(llvm::Function *Resolver,
                                 ArrayRef<MultiVersionResolverOption> Options);
   void
   EmitX86MultiVersionResolver(llvm::Function *Resolver,
                               ArrayRef<MultiVersionResolverOption> Options);
   void
   EmitAArch64MultiVersionResolver(llvm::Function *Resolver,
                                   ArrayRef<MultiVersionResolverOption> Options);
+  void
+  EmitRISCVMultiVersionResolver(llvm::Function *Resolver,
+                                ArrayRef<MultiVersionResolverOption> Options);
+  llvm::Value *EmitRISCVCheckFeatureFunc(std::string currFeats);
 
 private:
   QualType getVarArgType(const Expr *Arg);
 
   void EmitDeclMetadata();
 
   BlockByrefHelpers *buildByrefHelpers(llvm::StructType &byrefType,
                                   const AutoVarEmission &emission);

clang/lib/CodeGen/CodeGenFunction.cpp

void CodeGenFunction::EmitMultiVersionResolver(
   switch (ArchType) {
   case llvm::Triple::x86:
   case llvm::Triple::x86_64:
     EmitX86MultiVersionResolver(Resolver, Options);
     return;
   case llvm::Triple::aarch64:
     EmitAArch64MultiVersionResolver(Resolver, Options);
     return;
-
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    EmitRISCVMultiVersionResolver(Resolver, Options);
+    return;
   default:
     assert(false && "Only implemented for x86 and AArch64 targets");
   }
 }
 
 void CodeGenFunction::EmitAArch64MultiVersionResolver(
     llvm::Function *Resolver, ArrayRef<MultiVersionResolverOption> Options) {
   assert(!Options.empty() && "No multiversion resolver options found");
void CodeGenFunction::EmitX86MultiVersionResolver(
   Builder.SetInsertPoint(CurBlock);
   llvm::CallInst *TrapCall = EmitTrapCall(llvm::Intrinsic::trap);
   TrapCall->setDoesNotReturn();
   TrapCall->setDoesNotThrow();
   Builder.CreateUnreachable();
   Builder.ClearInsertionPoint();
 }
 
+static std::string
+mergeRISCVTargetFeature(const std::vector<std::string> &Features) {
+  if (Features.empty())
+    return std::string();
+
+  std::string Rst = "";
+  for (unsigned i = 0; i < Features.size(); i++) {
+    Rst += Features[i].substr(1); // Remove prefix +/-
+    if (i != Features.size() - 1)
+      Rst += ";";
+  }
+  return Rst;
+}
+
+llvm::Value *
+CodeGenFunction::EmitRISCVCheckFeatureFunc(std::string CurrFeatStr) {
+  llvm::Constant *FeatStr = Builder.CreateGlobalString(CurrFeatStr);
+  llvm::Type *Args[] = {Int8PtrTy};
+  llvm::FunctionType *FTy =
+      llvm::FunctionType::get(Builder.getInt1Ty(), Args, /*Variadic*/ false);
+  llvm::FunctionCallee Func =
+      CGM.CreateRuntimeFunction(FTy, "__riscv_ifunc_select");
+  cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true);
+  cast<llvm::GlobalValue>(Func.getCallee())
+      ->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+  return Builder.CreateCall(Func, FeatStr);
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+    llvm::Function *Resolver, ArrayRef<MultiVersionResolverOption> Options) {
+  bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+
+  std::vector<MultiVersionResolverOption> CurrOptions(Options);
+
+  llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+  Builder.SetInsertPoint(CurBlock);
+
+  bool HasDefault = false;
+  int DefaultIndex = 0;
+  // Check the each candidate function.
+  for (unsigned Index = 0; Index < CurrOptions.size(); Index++) {
+    Builder.SetInsertPoint(CurBlock);
+
+    std::string CurrFeatStr = mergeRISCVTargetFeature(
+        getContext()
+            .getTargetInfo()
+            .parseTargetAttr(CurrOptions[Index].Conditions.Features[0])
+            .Features);
+
+    if (!CurrFeatStr.empty()) {
+      llvm::Value *Condition = EmitRISCVCheckFeatureFunc(CurrFeatStr);
+      llvm::BasicBlock *RetBlock = createBasicBlock("resolver_return", Resolver);
+      CGBuilderTy RetBuilder(*this, RetBlock);
+      CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder, CurrOptions[Index].Function,
+                                      SupportsIFunc);
+      CurBlock = createBasicBlock("resolver_else", Resolver);
+      Builder.CreateCondBr(Condition, RetBlock, CurBlock);
+    } else {
+      HasDefault = true;
+      DefaultIndex = Index;
+    }
+  }
+
+  // Finally, emit the default one.
+  if (HasDefault) {
+    Builder.SetInsertPoint(CurBlock);
+    CreateMultiVersionResolverReturn(
+        CGM, Resolver, Builder, CurrOptions[DefaultIndex].Function, SupportsIFunc);
+    return;
+  }
+
+  // If no generic/default, emit an unreachable.
+  Builder.SetInsertPoint(CurBlock);
+  llvm::CallInst *TrapCall = EmitTrapCall(llvm::Intrinsic::trap);
+  TrapCall->setDoesNotReturn();
+  TrapCall->setDoesNotThrow();
+  Builder.CreateUnreachable();
+  Builder.ClearInsertionPoint();
+}
+
 // Loc - where the diagnostic will point, where in the source code this
 //  alignment has failed.
 // SecondaryLoc - if present (will be present if sufficiently different from
 //  Loc), the diagnostic will additionally point a "Note:" to this location.
 //  It should be the location where the __attribute__((assume_aligned))
 //  was written e.g.
 void CodeGenFunction::emitAlignmentAssumptionCheck(
     llvm::Value *Ptr, QualType Ty, SourceLocation Loc,

clang/lib/CodeGen/CodeGenModule.cpp

if (FD->isTargetMultiVersion()) {
                 Func = GetAddrOfFunction(CurGD, Ty, /*ForVTable=*/false,
                                          /*DontDefer=*/false, ForDefinition);
               }
               assert(Func && "This should have just been created");
             }
             if (CurFD->getMultiVersionKind() == MultiVersionKind::Target) {
               const auto *TA = CurFD->getAttr<TargetAttr>();
               llvm::SmallVector<StringRef, 8> Feats;
+              if (getTarget().getTriple().isRISCV())
+                Feats.push_back(TA->getFeaturesStr());
+              else
                 TA->getAddedFeatures(Feats);
               Options.emplace_back(cast<llvm::Function>(Func),
                                    TA->getArchitecture(), Feats);
             } else {
               const auto *TVA = CurFD->getAttr<TargetVersionAttr>();
               llvm::SmallVector<StringRef, 8> Feats;
               TVA->getFeatures(Feats);
               Options.emplace_back(cast<llvm::Function>(Func),
                                    /*Architecture*/ "", Feats);

clang/test/CodeGen/RISCV/riscv-fmv.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei \
+// RUN:  -target-feature +m -target-feature +a               \
+// RUN:  -target-feature +f -target-feature +d               \
+// RUN:  -emit-llvm %s -o - | FileCheck %s                   \
+// RUN:  --check-prefix=CHECK-IR
+
+__attribute__((target("arch=+v"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb"))) void test1(void) {}
+__attribute__((target("arch=+v,+zbb,+zicond1p0"))) void test1(void) {}
+__attribute__((target("arch=rv64gc"))) void test1(void) {}
+__attribute__((target("default"))) void test1(void) {}
+
+__attribute__((target("default"))) void test2(void) {}
+
+void test3() { test1(); test2(); }
+
+// CHECK-IR: $test1.resolver = comdat any
+// CHECK-IR: $test2.resolver = comdat any
+
+// CHECK-IR: @0 = private unnamed_addr constant [2 x i8] c"v\00", align 1
+// CHECK-IR: @1 = private unnamed_addr constant [6 x i8] c"v;zbb\00", align 1
+// CHECK-IR: @2 = private unnamed_addr constant [26 x i8] c"v;zbb;experimental-zicond\00", align 1
+// CHECK-IR: @3 = private unnamed_addr constant [25 x i8] c"m;a;f;d;c;zicsr;zifencei\00", align 1
+
+
+// CHECK-IR-LABEL: define dso_local void @test1.v
+// CHECK-IR-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.zbb_v
+// CHECK-IR-SAME: () #[[ATTR1:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.experimental-zicond_zbb_v
+// CHECK-IR-SAME: () #[[ATTR2:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1.zifencei_zicsr_m_f_d_c_a
+// CHECK-IR-SAME: () #[[ATTR3:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test1
+// CHECK-IR-SAME: () #[[ATTR4:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test2
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define dso_local void @test3
+// CHECK-IR-SAME: () #[[ATTR4]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    call void @test1.resolver()
+// CHECK-IR-NEXT:    call void @test2.resolver()
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define weak_odr void @test1.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB0:[0-9]+]])
+// CHECK-IR-NEXT:    br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK-IR:       resolver_return:
+// CHECK-IR-NEXT:    musttail call void @test1.v()
+// CHECK-IR-NEXT:    ret void
+// CHECK-IR:       resolver_else:
+// CHECK-IR-NEXT:    [[TMP1:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB1:[0-9]+]])
+// CHECK-IR-NEXT:    br i1 [[TMP1]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
+// CHECK-IR:       resolver_return1:
+// CHECK-IR-NEXT:    musttail call void @test1.zbb_v()
+// CHECK-IR-NEXT:    ret void
+// CHECK-IR:       resolver_else2:
+// CHECK-IR-NEXT:    [[TMP2:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB2:[0-9]+]])
+// CHECK-IR-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
+// CHECK-IR:       resolver_return3:
+// CHECK-IR-NEXT:    musttail call void @test1.experimental-zicond_zbb_v()
+// CHECK-IR-NEXT:    ret void
+// CHECK-IR:       resolver_else4:
+// CHECK-IR-NEXT:    [[TMP3:%.*]] = call i1 @__riscv_ifunc_select(ptr @[[GLOB3:[0-9]+]])
+// CHECK-IR-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
+// CHECK-IR:       resolver_return5:
+// CHECK-IR-NEXT:    musttail call void @test1.zifencei_zicsr_m_f_d_c_a()
+// CHECK-IR-NEXT:    ret void
+// CHECK-IR:       resolver_else6:
+// CHECK-IR-NEXT:    musttail call void @test1()
+// CHECK-IR-NEXT:    ret void
+//
+//
+// CHECK-IR-LABEL: define weak_odr void @test2.resolver() comdat {
+// CHECK-IR-NEXT:  resolver_entry:
+// CHECK-IR-NEXT:    musttail call void @test2()
+// CHECK-IR-NEXT:    ret void
+//