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BeMg (Piyou Chen)
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User Since
Aug 15 2022, 1:04 AM (24 w, 3 d)

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Yesterday

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Use D141993 as DetectDeadLane user interface

Wed, Feb 1, 10:02 PM · Restricted Project, Restricted Project

Sun, Jan 22

BeMg accepted D141993: [CodeGen] Split some functionality from DetectDeadLanes into its own class to be reused. NFCi.

LGTM

Sun, Jan 22, 5:41 AM · Restricted Project, Restricted Project

Mon, Jan 9

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

rebaseY

Mon, Jan 9, 8:43 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.

Use do while

Mon, Jan 9, 8:42 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

rebase

Mon, Jan 9, 3:01 AM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.
  1. ModifySubRegisterOperandStatus -> modifySubRegisterOperandStatus
  2. if not change anything, skip computeSubRegisterLaneBitInfo
  3. Add comment
Mon, Jan 9, 2:53 AM · Restricted Project, Restricted Project

Wed, Jan 4

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

rebase

Wed, Jan 4, 11:43 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.

Split runOnce function into ModifySubRegisterOperandStatus and computeSubRegisterLaneBitInfo

Wed, Jan 4, 11:36 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Update std::unique_ptr<VRegInfo> with std::unique_ptr<VRegInfo[]>

Wed, Jan 4, 9:26 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Move init undef pass after DetectDeadLanes
  2. Remove <map>
Wed, Jan 4, 8:55 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.

Add a parameter to control whether set Operand as undef/def

Wed, Jan 4, 8:53 PM · Restricted Project, Restricted Project
BeMg committed rG20a1dcf57295: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension (authored by BeMg).
[RISCV][NFC] Update RISCVUsage.rst for Svnapot extension
Wed, Jan 4, 7:12 PM · Restricted Project, Restricted Project
BeMg closed D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension.
Wed, Jan 4, 7:11 PM · Restricted Project, Restricted Project

Tue, Jan 3

BeMg retitled D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension from [RISCV] Update RISCVUsage.rst for Svnapot extension to [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension.
Tue, Jan 3, 11:42 PM · Restricted Project, Restricted Project
BeMg updated the diff for D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension.

Rebase

Tue, Jan 3, 11:34 PM · Restricted Project, Restricted Project
BeMg retitled D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension from Update RISCVUsage.rst for Svnapot extension to [RISCV] Update RISCVUsage.rst for Svnapot extension.
Tue, Jan 3, 11:25 PM · Restricted Project, Restricted Project

Jan 3 2023

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Add more subregister testcase

Jan 3 2023, 3:15 AM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.

rebase

Jan 3 2023, 2:52 AM · Restricted Project, Restricted Project
BeMg updated the diff for D137763: [RISCV] precommit test for D129735.

Update

Jan 3 2023, 2:44 AM · Restricted Project, Restricted Project
BeMg updated the diff for D137763: [RISCV] precommit test for D129735.

Add more subregister testcase

Jan 3 2023, 2:26 AM · Restricted Project, Restricted Project

Dec 27 2022

BeMg added inline comments to D140382: [CodeGen] Add user interface for DetectDeadLanes.
Dec 27 2022, 5:44 AM · Restricted Project, Restricted Project

Dec 22 2022

BeMg added inline comments to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
Dec 22 2022, 3:39 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Use unique_ptr for VRegInfo
  2. Only run once DetectDeadLanes for each function
  3. Remove Seen and PHINodeLaneBitRecord
  4. Only call getRegClass once
Dec 22 2022, 3:36 AM · Restricted Project, Restricted Project
BeMg updated the diff for D140382: [CodeGen] Add user interface for DetectDeadLanes.
  1. let runOnMachineFunction reuse getSubRegisterLaneBitInfo
  2. Move the variable
Dec 22 2022, 12:57 AM · Restricted Project, Restricted Project

Dec 21 2022

BeMg committed rG5370255ff18a: [RISCV] Merge Masked and unMasked RVV manual codegen (authored by BeMg).
[RISCV] Merge Masked and unMasked RVV manual codegen
Dec 21 2022, 8:37 PM · Restricted Project, Restricted Project
BeMg closed D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.
Dec 21 2022, 8:36 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.

rebase

Dec 21 2022, 1:35 AM · Restricted Project, Restricted Project

Dec 20 2022

BeMg updated the diff for D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.

Update format

Dec 20 2022, 9:14 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.

Update format

Dec 20 2022, 5:47 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.

Update format

Dec 20 2022, 5:35 PM · Restricted Project, Restricted Project
BeMg updated the diff for D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.

Update format

Dec 20 2022, 6:41 AM · Restricted Project, Restricted Project
BeMg retitled D140361: [RISCV] Merge Masked and unMasked RVV manual codegen from [WIP][RISCV] Merge Masked and unMasked RVV manual codegen to [RISCV] Merge Masked and unMasked RVV manual codegen.
Dec 20 2022, 6:28 AM · Restricted Project, Restricted Project
BeMg updated the summary of D140382: [CodeGen] Add user interface for DetectDeadLanes.
Dec 20 2022, 2:11 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Move DetectDeadLanes pass change into another patch

Dec 20 2022, 2:08 AM · Restricted Project, Restricted Project
BeMg requested review of D140382: [CodeGen] Add user interface for DetectDeadLanes.
Dec 20 2022, 2:06 AM · Restricted Project, Restricted Project
BeMg committed rG0d4c6506100b: [RISCV] Refactor RVV Policy by structure (authored by BeMg).
[RISCV] Refactor RVV Policy by structure
Dec 20 2022, 1:20 AM · Restricted Project, Restricted Project
BeMg closed D139995: [RISCV] Refactor RVV Policy by structure.
Dec 20 2022, 1:20 AM · Restricted Project, Restricted Project
BeMg updated the diff for D139995: [RISCV] Refactor RVV Policy by structure.

rebase

Dec 20 2022, 1:11 AM · Restricted Project, Restricted Project

Dec 19 2022

BeMg retitled D140361: [RISCV] Merge Masked and unMasked RVV manual codegen from [WIP][RISCV] Merge Masked and unMasked manual codegen to [WIP][RISCV] Merge Masked and unMasked RVV manual codegen.
Dec 19 2022, 6:41 PM · Restricted Project, Restricted Project
BeMg updated the summary of D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.
Dec 19 2022, 6:36 PM · Restricted Project, Restricted Project
BeMg requested review of D140361: [RISCV] Merge Masked and unMasked RVV manual codegen.
Dec 19 2022, 6:26 PM · Restricted Project, Restricted Project

Dec 17 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Reuse DetectDeadLanes pass info for undefined subregister

Dec 17 2022, 4:25 AM · Restricted Project, Restricted Project

Dec 16 2022

BeMg updated the diff for D139995: [RISCV] Refactor RVV Policy by structure.
  1. Use Undisturbed, Agnostic and Omit to represent Tail and Mask
  2. Replace getDefaultPolicyBits != 0 with !RVVI->isTUPolicy() && !RVVI->isTUMUPolicy()
  3. Use llvm_unreachable
Dec 16 2022, 6:54 PM · Restricted Project, Restricted Project

Dec 15 2022

BeMg updated the diff for D139995: [RISCV] Refactor RVV Policy by structure.
  1. Remove this->
  2. Remove Policy() in struct declarationx
Dec 15 2022, 7:25 PM · Restricted Project, Restricted Project

Dec 14 2022

BeMg added inline comments to D139995: [RISCV] Refactor RVV Policy by structure.
Dec 14 2022, 7:06 PM · Restricted Project, Restricted Project
BeMg added inline comments to D139995: [RISCV] Refactor RVV Policy by structure.
Dec 14 2022, 7:05 PM · Restricted Project, Restricted Project
BeMg updated the diff for D139995: [RISCV] Refactor RVV Policy by structure.
  1. Update policy constructor
  2. use emplace_back
  3. Fix miss WithoutIntrinsicMU in policy equal check
Dec 14 2022, 7:01 PM · Restricted Project, Restricted Project

Dec 13 2022

BeMg added reviewers for D139995: [RISCV] Refactor RVV Policy by structure: kito-cheng, craig.topper, reames, rogfer01, frasercrmck.
Dec 13 2022, 9:56 PM · Restricted Project, Restricted Project
BeMg updated the summary of D139995: [RISCV] Refactor RVV Policy by structure.
Dec 13 2022, 9:50 PM · Restricted Project, Restricted Project
BeMg requested review of D139995: [RISCV] Refactor RVV Policy by structure.
Dec 13 2022, 9:49 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

rebase

Dec 13 2022, 8:52 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. unsigned -> Register
  2. use const std::vector<MachineInstr *> & instead of call by value
Dec 13 2022, 8:14 PM · Restricted Project, Restricted Project
BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Ping

Dec 13 2022, 6:18 AM · Restricted Project, Restricted Project
BeMg added inline comments to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
Dec 13 2022, 6:18 AM · Restricted Project, Restricted Project

Nov 30 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Rplace PseudoRVVInitUndef with VLE in MIR test
  2. Move MIR test into precommit
Nov 30 2022, 9:45 PM · Restricted Project, Restricted Project
BeMg updated the diff for D137763: [RISCV] precommit test for D129735.

Add two MIR test

Nov 30 2022, 9:43 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Fix spell
  2. Update isVectorRegClass
Nov 30 2022, 3:15 AM · Restricted Project, Restricted Project
BeMg retitled D129735: [RISCV] Add new pass to transform undef to pseudo for vector values. from [RISCV] Add new pass to transform undef to pesudo for vector values. to [RISCV] Add new pass to transform undef to pseudo for vector values..
Nov 30 2022, 12:40 AM · Restricted Project, Restricted Project

Nov 28 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Update testcase

Nov 28 2022, 6:47 PM · Restricted Project, Restricted Project

Nov 21 2022

BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Handle Sub-register undef+early-clobber
Nov 21 2022, 2:44 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Record PHI node subregister change
  2. New INSERT_SUBREG insert before early-clobber instruciton
  3. Subreg index computation include PHI node
Nov 21 2022, 2:08 AM · Restricted Project, Restricted Project

Nov 9 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Update testcase

Nov 9 2022, 10:26 PM · Restricted Project, Restricted Project
BeMg updated the diff for D137763: [RISCV] precommit test for D129735.

Update

Nov 9 2022, 10:19 PM · Restricted Project, Restricted Project
BeMg added inline comments to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
Nov 9 2022, 9:27 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Change DenseMap into SmallPrtSet

Nov 9 2022, 9:25 PM · Restricted Project, Restricted Project
BeMg requested review of D137763: [RISCV] precommit test for D129735.
Nov 9 2022, 9:05 PM · Restricted Project, Restricted Project
BeMg retitled D129735: [RISCV] Add new pass to transform undef to pseudo for vector values. from [WIP][RISCV] Add new pass to transform undef to pesudo for vector values. to [RISCV] Add new pass to transform undef to pesudo for vector values..
Nov 9 2022, 5:13 PM · Restricted Project, Restricted Project

Nov 8 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Avoid infinite loop by DenseMap

Nov 8 2022, 11:21 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Handle subregister liveness situation

Nov 8 2022, 10:10 PM · Restricted Project, Restricted Project

Oct 26 2022

BeMg updated the summary of D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension.
Oct 26 2022, 11:18 PM · Restricted Project, Restricted Project
BeMg requested review of D136816: [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension.
Oct 26 2022, 11:16 PM · Restricted Project, Restricted Project
BeMg committed rG7d7940fd7761: [RISCV] add svinval extension (authored by BeMg).
[RISCV] add svinval extension
Oct 26 2022, 9:49 AM · Restricted Project, Restricted Project, Restricted Project
BeMg closed D136571: [RISCV] add svinval extension.
Oct 26 2022, 9:49 AM · Restricted Project, Restricted Project, Restricted Project

Oct 25 2022

BeMg updated the diff for D136571: [RISCV] add svinval extension.

rebase

Oct 25 2022, 11:37 PM · Restricted Project, Restricted Project, Restricted Project
BeMg updated the diff for D136571: [RISCV] add svinval extension.

Update RISCVUsage.rst

Oct 25 2022, 10:48 AM · Restricted Project, Restricted Project, Restricted Project
BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

I remember now. It only miscompiles with -riscv-enable-subreg-liveness

That produces

foo:                                    # @foo
        .cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
        vsetvli a0, zero, e16, mf4, ta, ma
        vid.v   v8
        vadd.vi v10, v8, 1
        vadd.vi v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
        vl1r.v  v9, (zero)
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v11, v9, v8
        vrgatherei16.vv v13, v9, v10
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v11, v11, v13
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v13, v9, v12 <- this instruction violates the early clobber constraint
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v9, v11, v13
        vs1r.v  v9, (zero)
        j       .LBB0_1
.Lfunc_end0:
        .size   foo, .Lfunc_end0-foo
        .cfi_endproc
                                        # -- End function                        
        .section        ".note.GNU-stack","",@progbits
Oct 25 2022, 4:47 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Replace Insert_subreg with PesudoInit when subreg liveness is enabled.

Oct 25 2022, 4:29 AM · Restricted Project, Restricted Project
BeMg updated the summary of D136571: [RISCV] add svinval extension.
Oct 25 2022, 3:12 AM · Restricted Project, Restricted Project, Restricted Project
BeMg updated the diff for D136571: [RISCV] add svinval extension.

Update RISCVUsage.html

Oct 25 2022, 3:06 AM · Restricted Project, Restricted Project, Restricted Project

Oct 24 2022

BeMg committed rGf8b8426861a7: [RISCV] Add Svnapot extension (authored by BeMg).
[RISCV] Add Svnapot extension
Oct 24 2022, 1:33 AM · Restricted Project, Restricted Project, Restricted Project
BeMg closed D136570: [RISCV] Add Svnapot extension.
Oct 24 2022, 1:33 AM · Restricted Project, Restricted Project, Restricted Project

Oct 23 2022

BeMg updated the diff for D136571: [RISCV] add svinval extension.

Reorder the def then use the same let Predicates

Oct 23 2022, 9:58 PM · Restricted Project, Restricted Project, Restricted Project
BeMg updated the diff for D136571: [RISCV] add svinval extension.

Use Requires<[HasStdSvinval]> instead of using let Predicates

Oct 23 2022, 9:10 PM · Restricted Project, Restricted Project, Restricted Project
BeMg added reviewers for D136571: [RISCV] add svinval extension: kito-cheng, craig.topper, asb.
Oct 23 2022, 8:55 PM · Restricted Project, Restricted Project, Restricted Project
BeMg added reviewers for D136570: [RISCV] Add Svnapot extension: kito-cheng, craig.topper, asb.
Oct 23 2022, 8:55 PM · Restricted Project, Restricted Project, Restricted Project
BeMg updated the diff for D136570: [RISCV] Add Svnapot extension.

Remove Predicate and AssemblerPredicate

Oct 23 2022, 8:44 PM · Restricted Project, Restricted Project, Restricted Project
BeMg updated the diff for D136570: [RISCV] Add Svnapot extension.

Update

Oct 23 2022, 8:38 PM · Restricted Project, Restricted Project, Restricted Project
BeMg requested review of D136571: [RISCV] add svinval extension.
Oct 23 2022, 8:31 PM · Restricted Project, Restricted Project, Restricted Project
BeMg requested review of D136570: [RISCV] Add Svnapot extension.
Oct 23 2022, 7:38 PM · Restricted Project, Restricted Project, Restricted Project

Oct 21 2022

BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Update the approach that finding the VR super class.
Oct 21 2022, 1:25 AM · Restricted Project, Restricted Project
BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Does this patch work for this test case

define internal void @foo() {
loopIR.preheader.i.i:
  %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
  %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
  %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
  %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
  br label %loopIR3.i.i

loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
  %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
  %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
  %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
  %v42 = and <vscale x 8 x i8> %v38, %v40
  %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
  %v60 = and <vscale x 8 x i8> %v42, %v46
  store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
  br label %loopIR3.i.i
}

declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()

declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) 

declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)

This IR doesn't generate the undef+early-clobber situation, so this pass will not work on it.

RA result will not break the early-clobber constraint in current compiler.

Corrsponding MachineInst before RA place below:

********** MACHINEINSTRS **********
# Machine code for function foo: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues

0B      bb.0.loopIR.preheader.i.i:
          successors: %bb.1(0x80000000); %bb.1(100.00%)

16B       dead %16:gpr = PseudoVSETVLIX0 $x0, 206, implicit-def $vl, implicit-def $vtype
32B       undef %0.sub_vrm1_0:vrm2 = PseudoVID_V_MF4 -1, 4, implicit $vl, implicit $vtype
64B       undef %1.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 1, -1, 4, implicit $vl, implicit $vtype
96B       undef %2.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 3, -1, 4, implicit $vl, implicit $vtype

128B    bb.1.loopIR3.i.i:
        ; predecessors: %bb.0, %bb.1
          successors: %bb.1(0x80000000); %bb.1(100.00%)

160B      %10:vr = VL1RE8_V $x0 :: (load unknown-size from `ptr addrspace(1) null`, align 8, addrspace 1)
176B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
192B      early-clobber %11:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %0:vrm2, 4, 3, implicit $vl, implicit $vtype
208B      early-clobber %12:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %1:vrm2, 4, 3, implicit $vl, implicit $vtype
224B      dead %17:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
240B      %13:vr = PseudoVAND_VV_M1 %11:vr, %12:vr, -1, 3, implicit $vl, implicit $vtype
256B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
272B      early-clobber %14:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %2:vrm2, 4, 3, implicit $vl, implicit $vtype
288B      dead %18:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
304B      %15:vr = PseudoVAND_VV_M1 %13:vr, %14:vr, -1, 3, implicit $vl, implicit $vtype
320B      VS1R_V %15:vr, $x0 :: (store unknown-size into `ptr addrspace(1) null`, align 4, addrspace 1)
336B      PseudoBR %bb.1

Generated assembly see the note inline.

foo:                                    # @foo
	.cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
	vsetvli	a0, zero, e16, mf4, ta, ma
	vid.v	v8
	vadd.vi	v10, v8, 1
	vadd.vi	v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
	vl1r.v	v14, (zero)
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v15, v14, v8  <- The v14 here is LMUL=2 so it's v14 and v15. This means writing v15 violated the early clobber constraint.
	vrgatherei16.vv	v16, v14, v10
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v15, v15, v16
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v16, v14, v12
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v14, v15, v16
	vs1r.v	v14, (zero)
	j	.LBB0_1
.Lfunc_end0:
	.size	foo, .Lfunc_end0-foo
	.cfi_endproc
                                        # -- End function
	.section	".note.GNU-stack","",@progbits
Oct 21 2022, 12:39 AM · Restricted Project, Restricted Project
BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
Oct 21 2022, 12:26 AM · Restricted Project, Restricted Project

Oct 20 2022

BeMg added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Does this patch work for this test case

define internal void @foo() {
loopIR.preheader.i.i:
  %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
  %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
  %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
  %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
  br label %loopIR3.i.i

loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
  %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
  %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
  %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
  %v42 = and <vscale x 8 x i8> %v38, %v40
  %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
  %v60 = and <vscale x 8 x i8> %v42, %v46
  store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
  br label %loopIR3.i.i
}

declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()

declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) 

declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)
Oct 20 2022, 11:13 PM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
  1. Add sub-register into switch case
  2. Update NeedZeroInit into NeedPesudoInit
Oct 20 2022, 11:01 PM · Restricted Project, Restricted Project
BeMg retitled D129735: [RISCV] Add new pass to transform undef to pseudo for vector values. from [WIP][RISCV] Add new pass to transform undef to zero-init for vector values. to [WIP][RISCV] Add new pass to transform undef to pesudo for vector values..
Oct 20 2022, 3:04 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Fix clang-format not found warning

Oct 20 2022, 3:02 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Fix clang-format not found warning

Oct 20 2022, 3:01 AM · Restricted Project, Restricted Project
BeMg updated the diff for D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

[RISCV] Add new pass to transform undef to pesudo for vector values.

Oct 20 2022, 2:58 AM · Restricted Project, Restricted Project
BeMg commandeered D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

Here is a new approach that using the pseudo instruction to replace the undef value and remove it in later pass.

Oct 20 2022, 2:54 AM · Restricted Project, Restricted Project