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[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
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Authored by craig.topper on Jul 17 2023, 5:58 PM.

Details

Summary

Instead of zero extending the inputs by masking. We can shift them
left instead. This is cheaper when we don't zext.w instruction.

This does make the case where the inputs are already zero extended
or freely zero extendable worse though.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 17 2023, 5:58 PM
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craig.topper requested review of this revision.Jul 17 2023, 5:58 PM
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wangpc accepted this revision.Jul 18 2023, 3:09 AM

LGTM.
Please add some regression tests (for example, change signext to zeroext) so that we can fix them later .

This revision is now accepted and ready to land.Jul 18 2023, 3:09 AM
This revision was landed with ongoing or failed builds.Jul 18 2023, 10:39 AM
This revision was automatically updated to reflect the committed changes.