[RISCV] Make selectSETCC return SDValue instead of bool. NFC

[craig.topper]

Summary

We can use a null SDValue for the 'false' case. This avoids the
need for an output parameter. This is consistent with other
SelectionDAG code.

[wangpc]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
 /// RISC-V doesn't have general instructions for integer setne/seteq, but we can
 /// check for equality with 0. This function emits nodes that convert the
 /// seteq/setne into something that can be compared with 0.
 /// Based on RISCVDAGToDAGISel::selectSETCC but modified to produce
 /// target-independent SelectionDAG nodes rather than machine nodes.
-static bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val,
+static SDValue selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
                            SelectionDAG &DAG) {
   assert(ISD::isIntEqualitySetCC(ExpectedCCVal) &&
          "Unexpected condition code!");
 
   // We're looking for a setcc.
   if (N->getOpcode() != ISD::SETCC)
-    return false;
+    return SDValue();
 
   // Must be an equality comparison.
   ISD::CondCode CCVal = cast<CondCodeSDNode>(N->getOperand(2))->get();
   if (CCVal != ExpectedCCVal)
-    return false;
+    return SDValue();
 
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
 
   if (!LHS.getValueType().isInteger())
-    return false;
+    return SDValue();
 
   // If the RHS side is 0, we don't need any extra instructions, return the LHS.
-  if (isNullConstant(RHS)) {
-    Val = LHS;
-    return true;
-  }
+  if (isNullConstant(RHS))
+    return LHS;
 
   SDLoc DL(N);
 
   if (auto *C = dyn_cast<ConstantSDNode>(RHS)) {
     int64_t CVal = C->getSExtValue();
     // If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
     // non-zero otherwise.
-    if (CVal == -2048) {
-      Val = DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS,
+    if (CVal == -2048)
+      return DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS,
                          DAG.getConstant(CVal, DL, N->getValueType(0)));
-      return true;
-    }
     // If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
     // LHS is equal to the RHS and non-zero otherwise.
-    if (isInt<12>(CVal) || CVal == 2048) {
-      Val = DAG.getNode(ISD::ADD, DL, N->getValueType(0), LHS,
+    if (isInt<12>(CVal) || CVal == 2048)
+      return DAG.getNode(ISD::ADD, DL, N->getValueType(0), LHS,
                          DAG.getConstant(-CVal, DL, N->getValueType(0)));
-      return true;
-    }
   }
 
   // If nothing else we can XOR the LHS and RHS to produce zero if they are
   // equal and a non-zero value if they aren't.
-  Val = DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS, RHS);
-  return true;
+  return DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS, RHS);
 }
 
 // Transform `binOp (select cond, x, c0), c1` where `c0` and `c1` are constants
 // into `select cond, binOp(x, c1), binOp(c0, c1)` if profitable.
 // For now we only consider transformation profitable if `binOp(c0, c1)` ends up
 // being `0` or `-1`. In such cases we can replace `select` with `and`.
 // TODO: Should we also do this if `binOp(c0, c1)` is cheaper to materialize
 // than `c0`?
if (VT.isVector()) {
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
   // When Zicond is present, emit CZERO_EQZ and CZERO_NEZ nodes to implement
   // the SELECT. Performing the lowering here allows for greater control over
   // when CZERO_{EQZ/NEZ} are used vs another branchless sequence or
   // RISCVISD::SELECT_CC node (branch-based select).
   if (Subtarget.hasStdExtZicond() && VT.isInteger()) {
-    SDValue NewCondV;
-    if (selectSETCC(CondV, ISD::SETNE, NewCondV, DAG)) {
+    if (SDValue NewCondV = selectSETCC(CondV, ISD::SETNE, DAG)) {
       if (isNullConstant(FalseV))
         // (select (riscv_setne c), t, 0) -> (czero_eqz t, c)
         return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, NewCondV);
       if (isNullConstant(TrueV))
         // (select (riscv_setne c), 0, f) -> (czero_nez f, c)
         return DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, NewCondV);
       // (select (riscv_setne c), t, f) -> (or (czero_eqz t, c), (czero_nez f,
       // c)
       return DAG.getNode(
           ISD::OR, DL, VT,
           DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, NewCondV),
           DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, NewCondV));
     }
-    if (selectSETCC(CondV, ISD::SETEQ, NewCondV, DAG)) {
+    if (SDValue NewCondV =  selectSETCC(CondV, ISD::SETEQ, DAG)) {
       if (isNullConstant(FalseV))
         // (select (riscv_seteq c), t, 0) -> (czero_nez t, c)
         return DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, TrueV, NewCondV);
       if (isNullConstant(TrueV))
         // (select (riscv_seteq c), 0, f) -> (czero_eqz f, c)
         return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, FalseV, NewCondV);
       // (select (riscv_seteq c), t, f) -> (or (czero_eqz f, c), (czero_nez t,
       // c)