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Differential D155288

[RISCV] Add a new select combine for when the condition is a setcc that will be inverted
Needs ReviewPublic

Authored by craig.topper on Jul 14 2023, 5:35 AM.

Details

Reviewers
reames
mgudim
asb
Summary

This is primarily motivated by improving codegen for zicond (fixing the code quality regressions knowingly introduced in D155083), but the combine is enabled regardless of the presence of zicond as it appears to be either neutral or provide minor benefits even without zicond.

Because we lower select early (due to it not being a legal operation), we miss out on some of the select combines that would kick in after other operations have been legalised - in this case if the condval is a setcc that will later be inverted when being legalised, the xori instruction can be removed just by flipping the TrueVal and FalseVal. This combine just performs that transformation.

Now that D155328 was committed, the primary benefit is for RV32.

Diff Detail

Event Timeline

asb created this revision.Jul 14 2023, 5:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2023, 5:35 AM
Herald added subscribers: jobnoorman, luke, wingo and 29 others. · View Herald Transcript
asb requested review of this revision.Jul 14 2023, 5:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2023, 5:35 AM
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asb edited the summary of this revision. (Show Details)Jul 14 2023, 5:36 AM
Harbormaster completed remote builds in B245364: Diff 540380.Jul 14 2023, 6:24 AM
mgudim added inline comments.Jul 14 2023, 10:32 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
12300

what about floating-point?

12301

is it better to use TLI.getCondCodeAction(...) == Expand?

mgudim added inline comments.Jul 14 2023, 11:12 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
12300

nvm, I understand why its limited to integers only.

craig.topper mentioned this in D155327: [RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC.Jul 14 2023, 12:13 PM
craig.topper mentioned this in D155328: [RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y is 0 or 1..
craig.topper mentioned this in rGfda45d9198c8: [RISCV] Add FP compare test to condops.ll to show a missed opportunity to….Jul 17 2023, 8:48 AM
craig.topper mentioned this in rG7dfe62327db8: [RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y….Jul 19 2023, 12:33 PM
asb updated this revision to Diff 542519.Jul 20 2023, 7:42 AM
asb edited the summary of this revision. (Show Details)

Rebase now D155328 landed.

Harbormaster completed remote builds in B246919: Diff 542519.Jul 20 2023, 10:45 AM
reames added a comment.Aug 16 2023, 1:42 PM

I happened to see a case which looked a lot like this on RV64 where the user was a branch (probably not a lowered select, but not 100% sure). Could we extend this to a SETCC feeding a BRCOND as well? Doing this during DAG (vs only lowering) might expose more CSE opportunities.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
12849

This seems to have a decent amount of overlap with translateSetCCForBranch which we do during lowering of both branch and select. Could we maybe reuse that set of transforms here?

craig.topper commandeered this revision.Aug 16 2023, 1:51 PM
craig.topper edited reviewers, added: asb; removed: craig.topper.

Commandeering so I can rebase with latest test diffs

craig.topper updated this revision to Diff 550876.Aug 16 2023, 1:51 PM

Rebase

craig.topper added a comment.Aug 16 2023, 2:13 PM

Looks like we're only seeing any benefit on forced-atomics.ll now? @reames can you share a reproducer for the BR_CC issue?

reames added a comment.Aug 16 2023, 2:45 PM
In D155288#4593318, @craig.topper wrote:

Looks like we're only seeing any benefit on forced-atomics.ll now? @reames can you share a reproducer for the BR_CC issue?

Will do. Will probably take me a couple days; I had been working only from a binary, and need to go figure out the build system for said benchmark.

Harbormaster completed remote builds in B253036: Diff 550876.Aug 16 2023, 3:32 PM
craig.topper added a comment.Aug 16 2023, 4:22 PM
This comment was removed by craig.topper.
craig.topper added a comment.Aug 16 2023, 5:25 PM

Ignore the bad comment I just deleted. I had the wrong window.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
25 lines
test/
CodeGen/
RISCV/
620 lines
124 lines
24 lines
28 lines
136 lines
116 lines
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92 lines
89 lines
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Diff 550876

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===// //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation -------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 12,283 Lines • ▼ Show 20 Lines auto invertIfNegative = [&Mask, &VL](SDValue &V) {
return false; return false;
}; };
bool NegA = invertIfNegative(A); bool NegA = invertIfNegative(A);
bool NegB = invertIfNegative(B); bool NegB = invertIfNegative(B);
bool NegC = invertIfNegative(C); bool NegC = invertIfNegative(C);
// If no operands are negated, we're done. // If no operands are negated, we're done.
mgudimUnsubmitted
Not Done
ReplyInline Actions

what about floating-point?

mgudim: what about floating-point?
mgudimUnsubmitted
Not Done
ReplyInline Actions

nvm, I understand why its limited to integers only.

mgudim: nvm, I understand why its limited to integers only.
if (!NegA && !NegB && !NegC) if (!NegA && !NegB && !NegC)
mgudimUnsubmitted
Not Done
ReplyInline Actions

is it better to use TLI.getCondCodeAction(...) == Expand?

mgudim: is it better to use `TLI.getCondCodeAction(...) == Expand`?
return SDValue(); return SDValue();
unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC); unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
if (N->isTargetStrictFPOpcode()) if (N->isTargetStrictFPOpcode())
return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(), return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
{N->getOperand(0), A, B, C, Mask, VL}); {N->getOperand(0), A, B, C, Mask, VL});
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask, return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
VL); VL);
▲ Show 20 Lines • Show All 508 Lines • ▼ Show 20 Linesstatic SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
SDValue BitWidthMinusOne = SDValue BitWidthMinusOne =
DAG.getConstant(BitWidth - 1, SDLoc(N), CountZeroes.getValueType()); DAG.getConstant(BitWidth - 1, SDLoc(N), CountZeroes.getValueType());
auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(), auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(),
CountZeroes, BitWidthMinusOne); CountZeroes, BitWidthMinusOne);
return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0)); return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0));
} }
static bool setCCWillBeInvertedWhenLegalized(SDValue V) {
assert(V.getOpcode() == ISD::SETCC && "Unexpected opcode.");
ISD::CondCode CCVal = cast<CondCodeSDNode>(V.getOperand(2))->get();
return V.getOperand(0).getValueType().isInteger() &&
(CCVal == ISD::SETGE || CCVal == ISD::SETLE || CCVal == ISD::SETUGE ||
CCVal == ISD::SETULE);
}
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) { const RISCVSubtarget &Subtarget) {
if (SDValue Folded = foldSelectOfCTTZOrCTLZ(N, DAG)) if (SDValue Folded = foldSelectOfCTTZOrCTLZ(N, DAG))
return Folded; return Folded;
if (Subtarget.hasShortForwardBranchOpt()) if (Subtarget.hasShortForwardBranchOpt())
return SDValue(); return SDValue();
SDValue CondVal = N->getOperand(0);
SDValue TrueVal = N->getOperand(1); SDValue TrueVal = N->getOperand(1);
SDValue FalseVal = N->getOperand(2); SDValue FalseVal = N->getOperand(2);
// If CondVal is a setcc that will be inverted when legalized, take
// advantage of the freedom to swap TrueVal and FalseVal and convert the
// setcc to one that is natively supported.
if (CondVal.getOpcode() == ISD::SETCC &&
setCCWillBeInvertedWhenLegalized(CondVal)) {
reamesUnsubmitted
Not Done
ReplyInline Actions

This seems to have a decent amount of overlap with translateSetCCForBranch which we do during lowering of both branch and select. Could we maybe reuse that set of transforms here?

reames: This seems to have a decent amount of overlap with translateSetCCForBranch which we do during…
SDLoc DL(N);
EVT VT = N->getValueType(0);
ISD::CondCode NewCCVal =
ISD::getSetCCInverse(cast<CondCodeSDNode>(CondVal.getOperand(2))->get(),
CondVal.getOperand(0).getValueType());
return DAG.getSelect(DL, VT,
DAG.getSetCC(DL, CondVal.getValueType(),
CondVal.getOperand(0),
CondVal.getOperand(1), NewCCVal),
FalseVal, TrueVal);
}
if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false)) if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false))
return V; return V;
return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true); return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true);
} }
// If we're concatenating a series of vector loads like // If we're concatenating a series of vector loads like
// concat_vectors (load v4i8, p+0), (load v4i8, p+n), (load v4i8, p+n*2) ... // concat_vectors (load v4i8, p+0), (load v4i8, p+n), (load v4i8, p+n*2) ...
// Then we can turn this into a strided load by widening the vector elements // Then we can turn this into a strided load by widening the vector elements
▲ Show 20 Lines • Show All 5,099 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/atomic-rmw.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,887 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB50_4 ; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB50_1 ; RV32I-NEXT: blt s2, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB50_4 ; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB50_1 ; RV64I-NEXT: blt s2, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB51_4 ; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB51_1 ; RV32I-NEXT: blt s2, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB51_4 ; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB51_1 ; RV64I-NEXT: blt s2, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB52_4 ; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB52_1 ; RV32I-NEXT: blt s2, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB52_4 ; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB52_1 ; RV64I-NEXT: blt s2, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB53_4 ; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB53_1 ; RV32I-NEXT: blt s2, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB53_4 ; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB53_1 ; RV64I-NEXT: blt s2, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB54_4 ; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB54_1 ; RV32I-NEXT: blt s2, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB54_4 ; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB54_1 ; RV64I-NEXT: blt s2, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB60_4 ; RV32I-NEXT: bnez a0, .LBB60_4
; RV32I-NEXT: .LBB60_2: # %atomicrmw.start ; RV32I-NEXT: .LBB60_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB60_1 ; RV32I-NEXT: bltu s2, a0, .LBB60_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB60_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB60_1 ; RV32I-NEXT: j .LBB60_1
; RV32I-NEXT: .LBB60_4: # %atomicrmw.end ; RV32I-NEXT: .LBB60_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB60_4 ; RV64I-NEXT: bnez a0, .LBB60_4
; RV64I-NEXT: .LBB60_2: # %atomicrmw.start ; RV64I-NEXT: .LBB60_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB60_1 ; RV64I-NEXT: bltu s2, a0, .LBB60_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB60_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB60_1 ; RV64I-NEXT: j .LBB60_1
; RV64I-NEXT: .LBB60_4: # %atomicrmw.end ; RV64I-NEXT: .LBB60_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB61_4 ; RV32I-NEXT: bnez a0, .LBB61_4
; RV32I-NEXT: .LBB61_2: # %atomicrmw.start ; RV32I-NEXT: .LBB61_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB61_1 ; RV32I-NEXT: bltu s2, a0, .LBB61_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB61_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB61_1 ; RV32I-NEXT: j .LBB61_1
; RV32I-NEXT: .LBB61_4: # %atomicrmw.end ; RV32I-NEXT: .LBB61_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB61_4 ; RV64I-NEXT: bnez a0, .LBB61_4
; RV64I-NEXT: .LBB61_2: # %atomicrmw.start ; RV64I-NEXT: .LBB61_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB61_1 ; RV64I-NEXT: bltu s2, a0, .LBB61_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB61_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB61_1 ; RV64I-NEXT: j .LBB61_1
; RV64I-NEXT: .LBB61_4: # %atomicrmw.end ; RV64I-NEXT: .LBB61_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB62_4 ; RV32I-NEXT: bnez a0, .LBB62_4
; RV32I-NEXT: .LBB62_2: # %atomicrmw.start ; RV32I-NEXT: .LBB62_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB62_1 ; RV32I-NEXT: bltu s2, a0, .LBB62_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB62_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB62_1 ; RV32I-NEXT: j .LBB62_1
; RV32I-NEXT: .LBB62_4: # %atomicrmw.end ; RV32I-NEXT: .LBB62_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB62_4 ; RV64I-NEXT: bnez a0, .LBB62_4
; RV64I-NEXT: .LBB62_2: # %atomicrmw.start ; RV64I-NEXT: .LBB62_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB62_1 ; RV64I-NEXT: bltu s2, a0, .LBB62_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB62_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB62_1 ; RV64I-NEXT: j .LBB62_1
; RV64I-NEXT: .LBB62_4: # %atomicrmw.end ; RV64I-NEXT: .LBB62_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB63_4 ; RV32I-NEXT: bnez a0, .LBB63_4
; RV32I-NEXT: .LBB63_2: # %atomicrmw.start ; RV32I-NEXT: .LBB63_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB63_1 ; RV32I-NEXT: bltu s2, a0, .LBB63_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB63_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB63_1 ; RV32I-NEXT: j .LBB63_1
; RV32I-NEXT: .LBB63_4: # %atomicrmw.end ; RV32I-NEXT: .LBB63_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB63_4 ; RV64I-NEXT: bnez a0, .LBB63_4
; RV64I-NEXT: .LBB63_2: # %atomicrmw.start ; RV64I-NEXT: .LBB63_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB63_1 ; RV64I-NEXT: bltu s2, a0, .LBB63_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB63_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB63_1 ; RV64I-NEXT: j .LBB63_1
; RV64I-NEXT: .LBB63_4: # %atomicrmw.end ; RV64I-NEXT: .LBB63_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB64_4 ; RV32I-NEXT: bnez a0, .LBB64_4
; RV32I-NEXT: .LBB64_2: # %atomicrmw.start ; RV32I-NEXT: .LBB64_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB64_1 ; RV32I-NEXT: bltu s2, a0, .LBB64_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB64_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB64_1 ; RV32I-NEXT: j .LBB64_1
; RV32I-NEXT: .LBB64_4: # %atomicrmw.end ; RV32I-NEXT: .LBB64_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB64_4 ; RV64I-NEXT: bnez a0, .LBB64_4
; RV64I-NEXT: .LBB64_2: # %atomicrmw.start ; RV64I-NEXT: .LBB64_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB64_1 ; RV64I-NEXT: bltu s2, a0, .LBB64_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB64_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB64_1 ; RV64I-NEXT: j .LBB64_1
; RV64I-NEXT: .LBB64_4: # %atomicrmw.end ; RV64I-NEXT: .LBB64_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB115_4 ; RV32I-NEXT: bnez a0, .LBB115_4
; RV32I-NEXT: .LBB115_2: # %atomicrmw.start ; RV32I-NEXT: .LBB115_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB115_1 ; RV32I-NEXT: blt s2, a0, .LBB115_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB115_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB115_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB115_1 ; RV32I-NEXT: j .LBB115_1
; RV32I-NEXT: .LBB115_4: # %atomicrmw.end ; RV32I-NEXT: .LBB115_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB115_4 ; RV64I-NEXT: bnez a0, .LBB115_4
; RV64I-NEXT: .LBB115_2: # %atomicrmw.start ; RV64I-NEXT: .LBB115_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB115_1 ; RV64I-NEXT: blt s2, a0, .LBB115_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB115_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB115_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB115_1 ; RV64I-NEXT: j .LBB115_1
; RV64I-NEXT: .LBB115_4: # %atomicrmw.end ; RV64I-NEXT: .LBB115_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB116_4 ; RV32I-NEXT: bnez a0, .LBB116_4
; RV32I-NEXT: .LBB116_2: # %atomicrmw.start ; RV32I-NEXT: .LBB116_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB116_1 ; RV32I-NEXT: blt s2, a0, .LBB116_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB116_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB116_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB116_1 ; RV32I-NEXT: j .LBB116_1
; RV32I-NEXT: .LBB116_4: # %atomicrmw.end ; RV32I-NEXT: .LBB116_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB116_4 ; RV64I-NEXT: bnez a0, .LBB116_4
; RV64I-NEXT: .LBB116_2: # %atomicrmw.start ; RV64I-NEXT: .LBB116_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB116_1 ; RV64I-NEXT: blt s2, a0, .LBB116_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB116_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB116_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB116_1 ; RV64I-NEXT: j .LBB116_1
; RV64I-NEXT: .LBB116_4: # %atomicrmw.end ; RV64I-NEXT: .LBB116_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB117_4 ; RV32I-NEXT: bnez a0, .LBB117_4
; RV32I-NEXT: .LBB117_2: # %atomicrmw.start ; RV32I-NEXT: .LBB117_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB117_1 ; RV32I-NEXT: blt s2, a0, .LBB117_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB117_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB117_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB117_1 ; RV32I-NEXT: j .LBB117_1
; RV32I-NEXT: .LBB117_4: # %atomicrmw.end ; RV32I-NEXT: .LBB117_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB117_4 ; RV64I-NEXT: bnez a0, .LBB117_4
; RV64I-NEXT: .LBB117_2: # %atomicrmw.start ; RV64I-NEXT: .LBB117_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB117_1 ; RV64I-NEXT: blt s2, a0, .LBB117_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB117_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB117_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB117_1 ; RV64I-NEXT: j .LBB117_1
; RV64I-NEXT: .LBB117_4: # %atomicrmw.end ; RV64I-NEXT: .LBB117_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB118_4 ; RV32I-NEXT: bnez a0, .LBB118_4
; RV32I-NEXT: .LBB118_2: # %atomicrmw.start ; RV32I-NEXT: .LBB118_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB118_1 ; RV32I-NEXT: blt s2, a0, .LBB118_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB118_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB118_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB118_1 ; RV32I-NEXT: j .LBB118_1
; RV32I-NEXT: .LBB118_4: # %atomicrmw.end ; RV32I-NEXT: .LBB118_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB118_4 ; RV64I-NEXT: bnez a0, .LBB118_4
; RV64I-NEXT: .LBB118_2: # %atomicrmw.start ; RV64I-NEXT: .LBB118_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB118_1 ; RV64I-NEXT: blt s2, a0, .LBB118_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB118_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB118_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB118_1 ; RV64I-NEXT: j .LBB118_1
; RV64I-NEXT: .LBB118_4: # %atomicrmw.end ; RV64I-NEXT: .LBB118_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB119_4 ; RV32I-NEXT: bnez a0, .LBB119_4
; RV32I-NEXT: .LBB119_2: # %atomicrmw.start ; RV32I-NEXT: .LBB119_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB119_1 ; RV32I-NEXT: blt s2, a0, .LBB119_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB119_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB119_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB119_1 ; RV32I-NEXT: j .LBB119_1
; RV32I-NEXT: .LBB119_4: # %atomicrmw.end ; RV32I-NEXT: .LBB119_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB119_4 ; RV64I-NEXT: bnez a0, .LBB119_4
; RV64I-NEXT: .LBB119_2: # %atomicrmw.start ; RV64I-NEXT: .LBB119_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB119_1 ; RV64I-NEXT: blt s2, a0, .LBB119_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB119_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB119_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB119_1 ; RV64I-NEXT: j .LBB119_1
; RV64I-NEXT: .LBB119_4: # %atomicrmw.end ; RV64I-NEXT: .LBB119_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB125_4 ; RV32I-NEXT: bnez a0, .LBB125_4
; RV32I-NEXT: .LBB125_2: # %atomicrmw.start ; RV32I-NEXT: .LBB125_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB125_1 ; RV32I-NEXT: bltu s3, a0, .LBB125_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB125_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB125_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB125_1 ; RV32I-NEXT: j .LBB125_1
; RV32I-NEXT: .LBB125_4: # %atomicrmw.end ; RV32I-NEXT: .LBB125_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB125_4 ; RV64I-NEXT: bnez a0, .LBB125_4
; RV64I-NEXT: .LBB125_2: # %atomicrmw.start ; RV64I-NEXT: .LBB125_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB125_1 ; RV64I-NEXT: bltu s3, a0, .LBB125_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB125_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB125_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB125_1 ; RV64I-NEXT: j .LBB125_1
; RV64I-NEXT: .LBB125_4: # %atomicrmw.end ; RV64I-NEXT: .LBB125_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB126_4 ; RV32I-NEXT: bnez a0, .LBB126_4
; RV32I-NEXT: .LBB126_2: # %atomicrmw.start ; RV32I-NEXT: .LBB126_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB126_1 ; RV32I-NEXT: bltu s3, a0, .LBB126_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB126_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB126_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB126_1 ; RV32I-NEXT: j .LBB126_1
; RV32I-NEXT: .LBB126_4: # %atomicrmw.end ; RV32I-NEXT: .LBB126_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB126_4 ; RV64I-NEXT: bnez a0, .LBB126_4
; RV64I-NEXT: .LBB126_2: # %atomicrmw.start ; RV64I-NEXT: .LBB126_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB126_1 ; RV64I-NEXT: bltu s3, a0, .LBB126_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB126_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB126_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB126_1 ; RV64I-NEXT: j .LBB126_1
; RV64I-NEXT: .LBB126_4: # %atomicrmw.end ; RV64I-NEXT: .LBB126_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB127_4 ; RV32I-NEXT: bnez a0, .LBB127_4
; RV32I-NEXT: .LBB127_2: # %atomicrmw.start ; RV32I-NEXT: .LBB127_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB127_1 ; RV32I-NEXT: bltu s3, a0, .LBB127_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB127_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB127_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB127_1 ; RV32I-NEXT: j .LBB127_1
; RV32I-NEXT: .LBB127_4: # %atomicrmw.end ; RV32I-NEXT: .LBB127_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB127_4 ; RV64I-NEXT: bnez a0, .LBB127_4
; RV64I-NEXT: .LBB127_2: # %atomicrmw.start ; RV64I-NEXT: .LBB127_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB127_1 ; RV64I-NEXT: bltu s3, a0, .LBB127_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB127_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB127_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB127_1 ; RV64I-NEXT: j .LBB127_1
; RV64I-NEXT: .LBB127_4: # %atomicrmw.end ; RV64I-NEXT: .LBB127_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB128_4 ; RV32I-NEXT: bnez a0, .LBB128_4
; RV32I-NEXT: .LBB128_2: # %atomicrmw.start ; RV32I-NEXT: .LBB128_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB128_1 ; RV32I-NEXT: bltu s3, a0, .LBB128_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB128_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB128_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB128_1 ; RV32I-NEXT: j .LBB128_1
; RV32I-NEXT: .LBB128_4: # %atomicrmw.end ; RV32I-NEXT: .LBB128_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB128_4 ; RV64I-NEXT: bnez a0, .LBB128_4
; RV64I-NEXT: .LBB128_2: # %atomicrmw.start ; RV64I-NEXT: .LBB128_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB128_1 ; RV64I-NEXT: bltu s3, a0, .LBB128_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB128_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB128_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB128_1 ; RV64I-NEXT: j .LBB128_1
; RV64I-NEXT: .LBB128_4: # %atomicrmw.end ; RV64I-NEXT: .LBB128_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB129_4 ; RV32I-NEXT: bnez a0, .LBB129_4
; RV32I-NEXT: .LBB129_2: # %atomicrmw.start ; RV32I-NEXT: .LBB129_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB129_1 ; RV32I-NEXT: bltu s3, a0, .LBB129_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB129_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB129_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB129_1 ; RV32I-NEXT: j .LBB129_1
; RV32I-NEXT: .LBB129_4: # %atomicrmw.end ; RV32I-NEXT: .LBB129_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB129_4 ; RV64I-NEXT: bnez a0, .LBB129_4
; RV64I-NEXT: .LBB129_2: # %atomicrmw.start ; RV64I-NEXT: .LBB129_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB129_1 ; RV64I-NEXT: bltu s3, a0, .LBB129_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB129_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB129_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB129_1 ; RV64I-NEXT: j .LBB129_1
; RV64I-NEXT: .LBB129_4: # %atomicrmw.end ; RV64I-NEXT: .LBB129_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 1,833 Lines • ▼ Show 20 Lines
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB170_4 ; RV32I-NEXT: bnez a0, .LBB170_4
; RV32I-NEXT: .LBB170_2: # %atomicrmw.start ; RV32I-NEXT: .LBB170_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB170_1 ; RV32I-NEXT: blt s1, a3, .LBB170_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB170_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB170_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB170_1 ; RV32I-NEXT: j .LBB170_1
; RV32I-NEXT: .LBB170_4: # %atomicrmw.end ; RV32I-NEXT: .LBB170_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB170_4 ; RV64I-NEXT: bnez a0, .LBB170_4
; RV64I-NEXT: .LBB170_2: # %atomicrmw.start ; RV64I-NEXT: .LBB170_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB170_1 ; RV64I-NEXT: blt s2, a3, .LBB170_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB170_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB170_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB170_1 ; RV64I-NEXT: j .LBB170_1
; RV64I-NEXT: .LBB170_4: # %atomicrmw.end ; RV64I-NEXT: .LBB170_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB171_4 ; RV32I-NEXT: bnez a0, .LBB171_4
; RV32I-NEXT: .LBB171_2: # %atomicrmw.start ; RV32I-NEXT: .LBB171_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB171_1 ; RV32I-NEXT: blt s1, a3, .LBB171_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB171_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB171_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB171_1 ; RV32I-NEXT: j .LBB171_1
; RV32I-NEXT: .LBB171_4: # %atomicrmw.end ; RV32I-NEXT: .LBB171_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 22 Lines
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB171_4 ; RV64I-NEXT: bnez a0, .LBB171_4
; RV64I-NEXT: .LBB171_2: # %atomicrmw.start ; RV64I-NEXT: .LBB171_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB171_1 ; RV64I-NEXT: blt s2, a3, .LBB171_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB171_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB171_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB171_1 ; RV64I-NEXT: j .LBB171_1
; RV64I-NEXT: .LBB171_4: # %atomicrmw.end ; RV64I-NEXT: .LBB171_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB172_4 ; RV32I-NEXT: bnez a0, .LBB172_4
; RV32I-NEXT: .LBB172_2: # %atomicrmw.start ; RV32I-NEXT: .LBB172_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB172_1 ; RV32I-NEXT: blt s1, a3, .LBB172_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB172_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB172_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB172_1 ; RV32I-NEXT: j .LBB172_1
; RV32I-NEXT: .LBB172_4: # %atomicrmw.end ; RV32I-NEXT: .LBB172_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 22 Lines
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB172_4 ; RV64I-NEXT: bnez a0, .LBB172_4
; RV64I-NEXT: .LBB172_2: # %atomicrmw.start ; RV64I-NEXT: .LBB172_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB172_1 ; RV64I-NEXT: blt s2, a3, .LBB172_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB172_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB172_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB172_1 ; RV64I-NEXT: j .LBB172_1
; RV64I-NEXT: .LBB172_4: # %atomicrmw.end ; RV64I-NEXT: .LBB172_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB173_4 ; RV32I-NEXT: bnez a0, .LBB173_4
; RV32I-NEXT: .LBB173_2: # %atomicrmw.start ; RV32I-NEXT: .LBB173_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB173_1 ; RV32I-NEXT: blt s1, a3, .LBB173_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB173_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB173_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB173_1 ; RV32I-NEXT: j .LBB173_1
; RV32I-NEXT: .LBB173_4: # %atomicrmw.end ; RV32I-NEXT: .LBB173_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB173_4 ; RV64I-NEXT: bnez a0, .LBB173_4
; RV64I-NEXT: .LBB173_2: # %atomicrmw.start ; RV64I-NEXT: .LBB173_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB173_1 ; RV64I-NEXT: blt s2, a3, .LBB173_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB173_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB173_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB173_1 ; RV64I-NEXT: j .LBB173_1
; RV64I-NEXT: .LBB173_4: # %atomicrmw.end ; RV64I-NEXT: .LBB173_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 25 Lines
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB174_4 ; RV32I-NEXT: bnez a0, .LBB174_4
; RV32I-NEXT: .LBB174_2: # %atomicrmw.start ; RV32I-NEXT: .LBB174_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB174_1 ; RV32I-NEXT: blt s1, a3, .LBB174_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB174_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB174_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB174_1 ; RV32I-NEXT: j .LBB174_1
; RV32I-NEXT: .LBB174_4: # %atomicrmw.end ; RV32I-NEXT: .LBB174_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB174_4 ; RV64I-NEXT: bnez a0, .LBB174_4
; RV64I-NEXT: .LBB174_2: # %atomicrmw.start ; RV64I-NEXT: .LBB174_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB174_1 ; RV64I-NEXT: blt s2, a3, .LBB174_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB174_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB174_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB174_1 ; RV64I-NEXT: j .LBB174_1
; RV64I-NEXT: .LBB174_4: # %atomicrmw.end ; RV64I-NEXT: .LBB174_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
▲ Show 20 Lines • Show All 470 Lines • ▼ Show 20 Lines
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB180_4 ; RV32I-NEXT: bnez a0, .LBB180_4
; RV32I-NEXT: .LBB180_2: # %atomicrmw.start ; RV32I-NEXT: .LBB180_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB180_1 ; RV32I-NEXT: bltu s1, a3, .LBB180_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB180_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB180_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB180_1 ; RV32I-NEXT: j .LBB180_1
; RV32I-NEXT: .LBB180_4: # %atomicrmw.end ; RV32I-NEXT: .LBB180_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 22 Lines
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB180_4 ; RV64I-NEXT: bnez a0, .LBB180_4
; RV64I-NEXT: .LBB180_2: # %atomicrmw.start ; RV64I-NEXT: .LBB180_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB180_1 ; RV64I-NEXT: bltu s2, a3, .LBB180_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB180_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB180_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB180_1 ; RV64I-NEXT: j .LBB180_1
; RV64I-NEXT: .LBB180_4: # %atomicrmw.end ; RV64I-NEXT: .LBB180_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 25 Lines
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB181_4 ; RV32I-NEXT: bnez a0, .LBB181_4
; RV32I-NEXT: .LBB181_2: # %atomicrmw.start ; RV32I-NEXT: .LBB181_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB181_1 ; RV32I-NEXT: bltu s1, a3, .LBB181_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB181_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB181_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB181_1 ; RV32I-NEXT: j .LBB181_1
; RV32I-NEXT: .LBB181_4: # %atomicrmw.end ; RV32I-NEXT: .LBB181_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 22 Lines
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB181_4 ; RV64I-NEXT: bnez a0, .LBB181_4
; RV64I-NEXT: .LBB181_2: # %atomicrmw.start ; RV64I-NEXT: .LBB181_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB181_1 ; RV64I-NEXT: bltu s2, a3, .LBB181_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB181_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB181_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB181_1 ; RV64I-NEXT: j .LBB181_1
; RV64I-NEXT: .LBB181_4: # %atomicrmw.end ; RV64I-NEXT: .LBB181_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 25 Lines
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB182_4 ; RV32I-NEXT: bnez a0, .LBB182_4
; RV32I-NEXT: .LBB182_2: # %atomicrmw.start ; RV32I-NEXT: .LBB182_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB182_1 ; RV32I-NEXT: bltu s1, a3, .LBB182_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB182_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB182_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB182_1 ; RV32I-NEXT: j .LBB182_1
; RV32I-NEXT: .LBB182_4: # %atomicrmw.end ; RV32I-NEXT: .LBB182_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 22 Lines
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB182_4 ; RV64I-NEXT: bnez a0, .LBB182_4
; RV64I-NEXT: .LBB182_2: # %atomicrmw.start ; RV64I-NEXT: .LBB182_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB182_1 ; RV64I-NEXT: bltu s2, a3, .LBB182_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB182_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB182_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB182_1 ; RV64I-NEXT: j .LBB182_1
; RV64I-NEXT: .LBB182_4: # %atomicrmw.end ; RV64I-NEXT: .LBB182_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB183_4 ; RV32I-NEXT: bnez a0, .LBB183_4
; RV32I-NEXT: .LBB183_2: # %atomicrmw.start ; RV32I-NEXT: .LBB183_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB183_1 ; RV32I-NEXT: bltu s1, a3, .LBB183_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB183_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB183_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB183_1 ; RV32I-NEXT: j .LBB183_1
; RV32I-NEXT: .LBB183_4: # %atomicrmw.end ; RV32I-NEXT: .LBB183_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB183_4 ; RV64I-NEXT: bnez a0, .LBB183_4
; RV64I-NEXT: .LBB183_2: # %atomicrmw.start ; RV64I-NEXT: .LBB183_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB183_1 ; RV64I-NEXT: bltu s2, a3, .LBB183_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB183_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB183_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB183_1 ; RV64I-NEXT: j .LBB183_1
; RV64I-NEXT: .LBB183_4: # %atomicrmw.end ; RV64I-NEXT: .LBB183_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB184_4 ; RV32I-NEXT: bnez a0, .LBB184_4
; RV32I-NEXT: .LBB184_2: # %atomicrmw.start ; RV32I-NEXT: .LBB184_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB184_1 ; RV32I-NEXT: bltu s1, a3, .LBB184_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB184_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB184_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB184_1 ; RV32I-NEXT: j .LBB184_1
; RV32I-NEXT: .LBB184_4: # %atomicrmw.end ; RV32I-NEXT: .LBB184_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB184_4 ; RV64I-NEXT: bnez a0, .LBB184_4
; RV64I-NEXT: .LBB184_2: # %atomicrmw.start ; RV64I-NEXT: .LBB184_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB184_1 ; RV64I-NEXT: bltu s2, a3, .LBB184_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB184_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB184_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB184_1 ; RV64I-NEXT: j .LBB184_1
; RV64I-NEXT: .LBB184_4: # %atomicrmw.end ; RV64I-NEXT: .LBB184_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB225_5 ; RV32I-NEXT: j .LBB225_5
; RV32I-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1 ; RV32I-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB225_5: # %atomicrmw.start ; RV32I-NEXT: .LBB225_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB225_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB225_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB225_1 ; RV32I-NEXT: j .LBB225_1
; RV32I-NEXT: .LBB225_7: # %atomicrmw.end ; RV32I-NEXT: .LBB225_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB225_5 ; RV32IA-NEXT: j .LBB225_5
; RV32IA-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1 ; RV32IA-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB225_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB225_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB225_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB225_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB225_1 ; RV32IA-NEXT: j .LBB225_1
; RV32IA-NEXT: .LBB225_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB225_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB225_4 ; RV64I-NEXT: bnez a0, .LBB225_4
; RV64I-NEXT: .LBB225_2: # %atomicrmw.start ; RV64I-NEXT: .LBB225_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB225_1 ; RV64I-NEXT: blt s1, a3, .LBB225_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB225_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB225_1 ; RV64I-NEXT: j .LBB225_1
; RV64I-NEXT: .LBB225_4: # %atomicrmw.end ; RV64I-NEXT: .LBB225_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB226_5 ; RV32I-NEXT: j .LBB226_5
; RV32I-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1 ; RV32I-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB226_5: # %atomicrmw.start ; RV32I-NEXT: .LBB226_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB226_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB226_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB226_1 ; RV32I-NEXT: j .LBB226_1
; RV32I-NEXT: .LBB226_7: # %atomicrmw.end ; RV32I-NEXT: .LBB226_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB226_5 ; RV32IA-NEXT: j .LBB226_5
; RV32IA-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1 ; RV32IA-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB226_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB226_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB226_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB226_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB226_1 ; RV32IA-NEXT: j .LBB226_1
; RV32IA-NEXT: .LBB226_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB226_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB226_4 ; RV64I-NEXT: bnez a0, .LBB226_4
; RV64I-NEXT: .LBB226_2: # %atomicrmw.start ; RV64I-NEXT: .LBB226_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB226_1 ; RV64I-NEXT: blt s1, a3, .LBB226_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB226_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB226_1 ; RV64I-NEXT: j .LBB226_1
; RV64I-NEXT: .LBB226_4: # %atomicrmw.end ; RV64I-NEXT: .LBB226_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB227_5 ; RV32I-NEXT: j .LBB227_5
; RV32I-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1 ; RV32I-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB227_5: # %atomicrmw.start ; RV32I-NEXT: .LBB227_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB227_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB227_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB227_1 ; RV32I-NEXT: j .LBB227_1
; RV32I-NEXT: .LBB227_7: # %atomicrmw.end ; RV32I-NEXT: .LBB227_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB227_5 ; RV32IA-NEXT: j .LBB227_5
; RV32IA-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1 ; RV32IA-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB227_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB227_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB227_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB227_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB227_1 ; RV32IA-NEXT: j .LBB227_1
; RV32IA-NEXT: .LBB227_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB227_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB227_4 ; RV64I-NEXT: bnez a0, .LBB227_4
; RV64I-NEXT: .LBB227_2: # %atomicrmw.start ; RV64I-NEXT: .LBB227_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB227_1 ; RV64I-NEXT: blt s1, a3, .LBB227_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB227_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB227_1 ; RV64I-NEXT: j .LBB227_1
; RV64I-NEXT: .LBB227_4: # %atomicrmw.end ; RV64I-NEXT: .LBB227_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB228_5 ; RV32I-NEXT: j .LBB228_5
; RV32I-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1 ; RV32I-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB228_5: # %atomicrmw.start ; RV32I-NEXT: .LBB228_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB228_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB228_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB228_1 ; RV32I-NEXT: j .LBB228_1
; RV32I-NEXT: .LBB228_7: # %atomicrmw.end ; RV32I-NEXT: .LBB228_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB228_5 ; RV32IA-NEXT: j .LBB228_5
; RV32IA-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1 ; RV32IA-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB228_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB228_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB228_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB228_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB228_1 ; RV32IA-NEXT: j .LBB228_1
; RV32IA-NEXT: .LBB228_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB228_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB228_4 ; RV64I-NEXT: bnez a0, .LBB228_4
; RV64I-NEXT: .LBB228_2: # %atomicrmw.start ; RV64I-NEXT: .LBB228_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB228_1 ; RV64I-NEXT: blt s1, a3, .LBB228_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB228_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB228_1 ; RV64I-NEXT: j .LBB228_1
; RV64I-NEXT: .LBB228_4: # %atomicrmw.end ; RV64I-NEXT: .LBB228_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 38 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB229_5 ; RV32I-NEXT: j .LBB229_5
; RV32I-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1 ; RV32I-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB229_5: # %atomicrmw.start ; RV32I-NEXT: .LBB229_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB229_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB229_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB229_1 ; RV32I-NEXT: j .LBB229_1
; RV32I-NEXT: .LBB229_7: # %atomicrmw.end ; RV32I-NEXT: .LBB229_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 31 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB229_5 ; RV32IA-NEXT: j .LBB229_5
; RV32IA-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1 ; RV32IA-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB229_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB229_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB229_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB229_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB229_1 ; RV32IA-NEXT: j .LBB229_1
; RV32IA-NEXT: .LBB229_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB229_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB229_4 ; RV64I-NEXT: bnez a0, .LBB229_4
; RV64I-NEXT: .LBB229_2: # %atomicrmw.start ; RV64I-NEXT: .LBB229_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB229_1 ; RV64I-NEXT: blt s1, a3, .LBB229_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB229_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB229_1 ; RV64I-NEXT: j .LBB229_1
; RV64I-NEXT: .LBB229_4: # %atomicrmw.end ; RV64I-NEXT: .LBB229_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB235_5 ; RV32I-NEXT: j .LBB235_5
; RV32I-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1 ; RV32I-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB235_5: # %atomicrmw.start ; RV32I-NEXT: .LBB235_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB235_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB235_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB235_1 ; RV32I-NEXT: j .LBB235_1
; RV32I-NEXT: .LBB235_7: # %atomicrmw.end ; RV32I-NEXT: .LBB235_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB235_5 ; RV32IA-NEXT: j .LBB235_5
; RV32IA-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1 ; RV32IA-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB235_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB235_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB235_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB235_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB235_1 ; RV32IA-NEXT: j .LBB235_1
; RV32IA-NEXT: .LBB235_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB235_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB235_4 ; RV64I-NEXT: bnez a0, .LBB235_4
; RV64I-NEXT: .LBB235_2: # %atomicrmw.start ; RV64I-NEXT: .LBB235_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB235_1 ; RV64I-NEXT: bltu s1, a3, .LBB235_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB235_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB235_1 ; RV64I-NEXT: j .LBB235_1
; RV64I-NEXT: .LBB235_4: # %atomicrmw.end ; RV64I-NEXT: .LBB235_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB236_5 ; RV32I-NEXT: j .LBB236_5
; RV32I-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1 ; RV32I-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB236_5: # %atomicrmw.start ; RV32I-NEXT: .LBB236_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB236_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB236_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB236_1 ; RV32I-NEXT: j .LBB236_1
; RV32I-NEXT: .LBB236_7: # %atomicrmw.end ; RV32I-NEXT: .LBB236_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB236_5 ; RV32IA-NEXT: j .LBB236_5
; RV32IA-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1 ; RV32IA-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB236_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB236_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB236_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB236_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB236_1 ; RV32IA-NEXT: j .LBB236_1
; RV32IA-NEXT: .LBB236_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB236_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB236_4 ; RV64I-NEXT: bnez a0, .LBB236_4
; RV64I-NEXT: .LBB236_2: # %atomicrmw.start ; RV64I-NEXT: .LBB236_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB236_1 ; RV64I-NEXT: bltu s1, a3, .LBB236_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB236_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB236_1 ; RV64I-NEXT: j .LBB236_1
; RV64I-NEXT: .LBB236_4: # %atomicrmw.end ; RV64I-NEXT: .LBB236_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 38 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB237_5 ; RV32I-NEXT: j .LBB237_5
; RV32I-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1 ; RV32I-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB237_5: # %atomicrmw.start ; RV32I-NEXT: .LBB237_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB237_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB237_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB237_1 ; RV32I-NEXT: j .LBB237_1
; RV32I-NEXT: .LBB237_7: # %atomicrmw.end ; RV32I-NEXT: .LBB237_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 31 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB237_5 ; RV32IA-NEXT: j .LBB237_5
; RV32IA-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1 ; RV32IA-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB237_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB237_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB237_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB237_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB237_1 ; RV32IA-NEXT: j .LBB237_1
; RV32IA-NEXT: .LBB237_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB237_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB237_4 ; RV64I-NEXT: bnez a0, .LBB237_4
; RV64I-NEXT: .LBB237_2: # %atomicrmw.start ; RV64I-NEXT: .LBB237_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB237_1 ; RV64I-NEXT: bltu s1, a3, .LBB237_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB237_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB237_1 ; RV64I-NEXT: j .LBB237_1
; RV64I-NEXT: .LBB237_4: # %atomicrmw.end ; RV64I-NEXT: .LBB237_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 38 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB238_5 ; RV32I-NEXT: j .LBB238_5
; RV32I-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1 ; RV32I-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB238_5: # %atomicrmw.start ; RV32I-NEXT: .LBB238_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB238_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB238_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB238_1 ; RV32I-NEXT: j .LBB238_1
; RV32I-NEXT: .LBB238_7: # %atomicrmw.end ; RV32I-NEXT: .LBB238_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 31 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB238_5 ; RV32IA-NEXT: j .LBB238_5
; RV32IA-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1 ; RV32IA-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB238_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB238_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB238_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB238_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB238_1 ; RV32IA-NEXT: j .LBB238_1
; RV32IA-NEXT: .LBB238_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB238_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB238_4 ; RV64I-NEXT: bnez a0, .LBB238_4
; RV64I-NEXT: .LBB238_2: # %atomicrmw.start ; RV64I-NEXT: .LBB238_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB238_1 ; RV64I-NEXT: bltu s1, a3, .LBB238_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB238_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB238_1 ; RV64I-NEXT: j .LBB238_1
; RV64I-NEXT: .LBB238_4: # %atomicrmw.end ; RV64I-NEXT: .LBB238_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB239_5 ; RV32I-NEXT: j .LBB239_5
; RV32I-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1 ; RV32I-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB239_5: # %atomicrmw.start ; RV32I-NEXT: .LBB239_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB239_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB239_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB239_1 ; RV32I-NEXT: j .LBB239_1
; RV32I-NEXT: .LBB239_7: # %atomicrmw.end ; RV32I-NEXT: .LBB239_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB239_5 ; RV32IA-NEXT: j .LBB239_5
; RV32IA-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1 ; RV32IA-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB239_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB239_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB239_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB239_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB239_1 ; RV32IA-NEXT: j .LBB239_1
; RV32IA-NEXT: .LBB239_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB239_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB239_4 ; RV64I-NEXT: bnez a0, .LBB239_4
; RV64I-NEXT: .LBB239_2: # %atomicrmw.start ; RV64I-NEXT: .LBB239_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB239_1 ; RV64I-NEXT: bltu s1, a3, .LBB239_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB239_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB239_1 ; RV64I-NEXT: j .LBB239_1
; RV64I-NEXT: .LBB239_4: # %atomicrmw.end ; RV64I-NEXT: .LBB239_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b seq_cst %1 = atomicrmw umin ptr %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/atomic-signext.ll

Show First 20 Lines • Show All 748 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB11_4 ; RV32I-NEXT: bnez a0, .LBB11_4
; RV32I-NEXT: .LBB11_2: # %atomicrmw.start ; RV32I-NEXT: .LBB11_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB11_1 ; RV32I-NEXT: blt s2, a0, .LBB11_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB11_1 ; RV32I-NEXT: j .LBB11_1
; RV32I-NEXT: .LBB11_4: # %atomicrmw.end ; RV32I-NEXT: .LBB11_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB11_4 ; RV64I-NEXT: bnez a0, .LBB11_4
; RV64I-NEXT: .LBB11_2: # %atomicrmw.start ; RV64I-NEXT: .LBB11_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB11_1 ; RV64I-NEXT: blt s2, a0, .LBB11_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB11_1 ; RV64I-NEXT: j .LBB11_1
; RV64I-NEXT: .LBB11_4: # %atomicrmw.end ; RV64I-NEXT: .LBB11_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lbu a3, 15(sp) ; RV32I-NEXT: lbu a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB13_4 ; RV32I-NEXT: bnez a0, .LBB13_4
; RV32I-NEXT: .LBB13_2: # %atomicrmw.start ; RV32I-NEXT: .LBB13_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s2, a0, .LBB13_1 ; RV32I-NEXT: bltu s2, a0, .LBB13_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB13_1 ; RV32I-NEXT: j .LBB13_1
; RV32I-NEXT: .LBB13_4: # %atomicrmw.end ; RV32I-NEXT: .LBB13_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lbu a3, 15(sp) ; RV64I-NEXT: lbu a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB13_4 ; RV64I-NEXT: bnez a0, .LBB13_4
; RV64I-NEXT: .LBB13_2: # %atomicrmw.start ; RV64I-NEXT: .LBB13_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a0, .LBB13_1 ; RV64I-NEXT: bltu s2, a0, .LBB13_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB13_1 ; RV64I-NEXT: j .LBB13_1
; RV64I-NEXT: .LBB13_4: # %atomicrmw.end ; RV64I-NEXT: .LBB13_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB22_4 ; RV32I-NEXT: bnez a0, .LBB22_4
; RV32I-NEXT: .LBB22_2: # %atomicrmw.start ; RV32I-NEXT: .LBB22_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s2, a0, .LBB22_1 ; RV32I-NEXT: blt s2, a0, .LBB22_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB22_1 ; RV32I-NEXT: j .LBB22_1
; RV32I-NEXT: .LBB22_4: # %atomicrmw.end ; RV32I-NEXT: .LBB22_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB22_4 ; RV64I-NEXT: bnez a0, .LBB22_4
; RV64I-NEXT: .LBB22_2: # %atomicrmw.start ; RV64I-NEXT: .LBB22_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a0, .LBB22_1 ; RV64I-NEXT: blt s2, a0, .LBB22_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB22_1 ; RV64I-NEXT: j .LBB22_1
; RV64I-NEXT: .LBB22_4: # %atomicrmw.end ; RV64I-NEXT: .LBB22_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB24_4 ; RV32I-NEXT: bnez a0, .LBB24_4
; RV32I-NEXT: .LBB24_2: # %atomicrmw.start ; RV32I-NEXT: .LBB24_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s2 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: bgeu s3, a0, .LBB24_1 ; RV32I-NEXT: bltu s3, a0, .LBB24_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: j .LBB24_1 ; RV32I-NEXT: j .LBB24_1
; RV32I-NEXT: .LBB24_4: # %atomicrmw.end ; RV32I-NEXT: .LBB24_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB24_4 ; RV64I-NEXT: bnez a0, .LBB24_4
; RV64I-NEXT: .LBB24_2: # %atomicrmw.start ; RV64I-NEXT: .LBB24_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s2 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: bgeu s3, a0, .LBB24_1 ; RV64I-NEXT: bltu s3, a0, .LBB24_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: j .LBB24_1 ; RV64I-NEXT: j .LBB24_1
; RV64I-NEXT: .LBB24_4: # %atomicrmw.end ; RV64I-NEXT: .LBB24_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB33_4 ; RV32I-NEXT: bnez a0, .LBB33_4
; RV32I-NEXT: .LBB33_2: # %atomicrmw.start ; RV32I-NEXT: .LBB33_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bge s1, a3, .LBB33_1 ; RV32I-NEXT: blt s1, a3, .LBB33_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB33_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB33_1 ; RV32I-NEXT: j .LBB33_1
; RV32I-NEXT: .LBB33_4: # %atomicrmw.end ; RV32I-NEXT: .LBB33_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB33_4 ; RV64I-NEXT: bnez a0, .LBB33_4
; RV64I-NEXT: .LBB33_2: # %atomicrmw.start ; RV64I-NEXT: .LBB33_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s2, a3, .LBB33_1 ; RV64I-NEXT: blt s2, a3, .LBB33_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB33_1 ; RV64I-NEXT: j .LBB33_1
; RV64I-NEXT: .LBB33_4: # %atomicrmw.end ; RV64I-NEXT: .LBB33_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4@plt ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: bgeu s1, a3, .LBB35_1 ; RV32I-NEXT: bltu s1, a3, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
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; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s2, a3, .LBB35_1 ; RV64I-NEXT: bltu s2, a3, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5 ; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB44_5 ; RV32I-NEXT: j .LBB44_5
; RV32I-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB44_5: # %atomicrmw.start ; RV32I-NEXT: .LBB44_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB44_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB44_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_7: # %atomicrmw.end ; RV32I-NEXT: .LBB44_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 31 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5 ; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB44_5 ; RV32IA-NEXT: j .LBB44_5
; RV32IA-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB44_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB44_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB44_1 ; RV32IA-NEXT: j .LBB44_1
; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB44_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bge s1, a3, .LBB44_1 ; RV64I-NEXT: blt s1, a3, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5 ; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB46_5 ; RV32I-NEXT: j .LBB46_5
; RV32I-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4 ; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB46_5: # %atomicrmw.start ; RV32I-NEXT: .LBB46_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: beqz a0, .LBB46_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: bnez a0, .LBB46_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_7: # %atomicrmw.end ; RV32I-NEXT: .LBB46_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 31 Lines
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5 ; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB46_5 ; RV32IA-NEXT: j .LBB46_5
; RV32IA-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4 ; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: beqz a0, .LBB46_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: bnez a0, .LBB46_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: j .LBB46_1 ; RV32IA-NEXT: j .LBB46_1
; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB46_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
Show All 17 Lines
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_8@plt ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: bgeu s1, a3, .LBB46_1 ; RV64I-NEXT: bltu s1, a3, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 462 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%1 = icmp ugt i32 %a, %b %1 = icmp ugt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
; CHECK-LABEL: select_icmp_uge: ; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2 ; CHECK-NEXT: bltu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp uge i32 %a, %b %1 = icmp uge i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_ult(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_ult(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
Show All 11 Lines; CHECK-NEXT: ret
%1 = icmp ult i32 %a, %b %1 = icmp ult i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
; CHECK-LABEL: select_icmp_ule: ; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2 ; CHECK-NEXT: bltu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: ; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b %1 = icmp ule i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_sgt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_sgt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
Show All 11 Lines; CHECK-NEXT: ret
%1 = icmp sgt i32 %a, %b %1 = icmp sgt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
; CHECK-LABEL: select_icmp_sge: ; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2 ; CHECK-NEXT: blt a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp sge i32 %a, %b %1 = icmp sge i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_slt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_slt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
Show All 11 Lines; CHECK-NEXT: ret
%1 = icmp slt i32 %a, %b %1 = icmp slt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) { define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
; CHECK-LABEL: select_icmp_sle: ; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2 ; CHECK-NEXT: blt a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 ; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.bf16.s fa0, fa5 ; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b %1 = icmp sle i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d %2 = select i1 %1, bfloat %c, bfloat %d
ret bfloat %2 ret bfloat %2
} }
define bfloat @select_icmp_slt_one(i32 signext %a) { define bfloat @select_icmp_slt_one(i32 signext %a) {
Show All 22 Lines

llvm/test/CodeGen/RISCV/compress.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: c.bnez a2, 0x1e ; RV32IC-NEXT: c.bnez a2, 0x1e
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: bltu a2, a0, 0x26 ; RV32IC-NEXT: bltu a2, a0, 0x26
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: bgeu a0, a2, 0x2e ; RV32IC-NEXT: bltu a0, a2, 0x2e
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a2, a0
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a0, 0(a1)
; RV32IC-NEXT: bltu a0, a2, 0x36 ; RV32IC-NEXT: bltu a2, a0, 0x36
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a2, a0
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a0, 0(a1)
; RV32IC-NEXT: bgeu a2, a0, 0x3e ; RV32IC-NEXT: bltu a0, a2, 0x3e
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: blt a2, a0, 0x46 ; RV32IC-NEXT: blt a2, a0, 0x46
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: bge a0, a2, 0x4e ; RV32IC-NEXT: blt a0, a2, 0x4e
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a2, a0
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a0, 0(a1)
; RV32IC-NEXT: blt a0, a2, 0x56 ; RV32IC-NEXT: blt a2, a0, 0x56
; RV32IC-NEXT: c.mv a2, a0
; RV32IC-NEXT: c.lw a0, 0(a1)
; RV32IC-NEXT: blt a0, a2, 0x5e
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a1, 0(a1)
; RV32IC-NEXT: bge a1, a0, 0x5e
; RV32IC-NEXT: c.mv a0, a1
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
%val1 = load volatile i32, ptr %b %val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 0, %val1 %tst1 = icmp eq i32 0, %val1
%val2 = select i1 %tst1, i32 %a, i32 %val1 %val2 = select i1 %tst1, i32 %a, i32 %val1
%val3 = load volatile i32, ptr %b %val3 = load volatile i32, ptr %b
%tst2 = icmp ne i32 0, %val3 %tst2 = icmp ne i32 0, %val3
%val4 = select i1 %tst2, i32 %val2, i32 %val3 %val4 = select i1 %tst2, i32 %val2, i32 %val3
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/condops.ll

Show First 20 Lines • Show All 1,258 Lines • ▼ Show 20 Lines
} }
define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setge: ; RV32I-LABEL: setge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB24_2 ; RV32I-NEXT: beq a1, a3, .LBB24_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a1, a3 ; RV32I-NEXT: slt a0, a1, a3
; RV32I-NEXT: bnez a0, .LBB24_3 ; RV32I-NEXT: beqz a0, .LBB24_3
; RV32I-NEXT: j .LBB24_4 ; RV32I-NEXT: j .LBB24_4
; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: sltu a0, a0, a2 ; RV32I-NEXT: sltu a0, a0, a2
; RV32I-NEXT: beqz a0, .LBB24_4 ; RV32I-NEXT: bnez a0, .LBB24_4
; RV32I-NEXT: .LBB24_3: ; RV32I-NEXT: .LBB24_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: .LBB24_4: ; RV32I-NEXT: .LBB24_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: setge: ; RV64I-LABEL: setge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a0, a1, .LBB24_2 ; RV64I-NEXT: blt a0, a1, .LBB24_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a3, a2
; RV64I-NEXT: .LBB24_2: ; RV64I-NEXT: .LBB24_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64XVENTANACONDOPS-LABEL: setge: ; RV64XVENTANACONDOPS-LABEL: setge:
; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0
; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret ; RV64XVENTANACONDOPS-NEXT: ret
; ;
; RV64XTHEADCONDMOV-LABEL: setge: ; RV64XTHEADCONDMOV-LABEL: setge:
; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: slt a0, a0, a1
; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 ; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0
; RV64XTHEADCONDMOV-NEXT: mv a0, a2 ; RV64XTHEADCONDMOV-NEXT: mv a0, a2
; RV64XTHEADCONDMOV-NEXT: ret ; RV64XTHEADCONDMOV-NEXT: ret
; ;
; RV32ZICOND-LABEL: setge: ; RV32ZICOND-LABEL: setge:
; RV32ZICOND: # %bb.0: ; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: xor t0, a1, a3
; RV32ZICOND-NEXT: slt a1, a1, a3 ; RV32ZICOND-NEXT: slt a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: sltu a0, a0, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a1, a0, a1 ; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 ; RV32ZICOND-NEXT: czero.nez a0, a4, a1
; RV32ZICOND-NEXT: czero.nez a2, a4, a1 ; RV32ZICOND-NEXT: czero.eqz a2, a6, a1
; RV32ZICOND-NEXT: or a0, a2, a0 ; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 ; RV32ZICOND-NEXT: czero.nez a2, a5, a1
; RV32ZICOND-NEXT: czero.nez a1, a5, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a7, a1
; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: setge: ; RV64ZICOND-LABEL: setge:
; RV64ZICOND: # %bb.0: ; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: slt a0, a0, a1 ; RV64ZICOND-NEXT: slt a0, a0, a1
; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a1, a2, a0
; RV64ZICOND-NEXT: czero.nez a0, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a3, a0
; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: ret ; RV64ZICOND-NEXT: ret
%rc = icmp sge i64 %a, %b %rc = icmp sge i64 %a, %b
%sel = select i1 %rc, i64 %rs1, i64 %rs2 %sel = select i1 %rc, i64 %rs1, i64 %rs2
ret i64 %sel ret i64 %sel
} }
define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
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} }
define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setle: ; RV32I-LABEL: setle:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB26_2 ; RV32I-NEXT: beq a1, a3, .LBB26_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a3, a1 ; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: bnez a0, .LBB26_3 ; RV32I-NEXT: beqz a0, .LBB26_3
; RV32I-NEXT: j .LBB26_4 ; RV32I-NEXT: j .LBB26_4
; RV32I-NEXT: .LBB26_2: ; RV32I-NEXT: .LBB26_2:
; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: beqz a0, .LBB26_4 ; RV32I-NEXT: bnez a0, .LBB26_4
; RV32I-NEXT: .LBB26_3: ; RV32I-NEXT: .LBB26_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: .LBB26_4: ; RV32I-NEXT: .LBB26_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: setle: ; RV64I-LABEL: setle:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a0, .LBB26_2 ; RV64I-NEXT: blt a1, a0, .LBB26_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a3, a2
; RV64I-NEXT: .LBB26_2: ; RV64I-NEXT: .LBB26_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64XVENTANACONDOPS-LABEL: setle: ; RV64XVENTANACONDOPS-LABEL: setle:
; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0
; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret ; RV64XVENTANACONDOPS-NEXT: ret
; ;
; RV64XTHEADCONDMOV-LABEL: setle: ; RV64XTHEADCONDMOV-LABEL: setle:
; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a0 ; RV64XTHEADCONDMOV-NEXT: slt a0, a1, a0
; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 ; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0
; RV64XTHEADCONDMOV-NEXT: mv a0, a2 ; RV64XTHEADCONDMOV-NEXT: mv a0, a2
; RV64XTHEADCONDMOV-NEXT: ret ; RV64XTHEADCONDMOV-NEXT: ret
; ;
; RV32ZICOND-LABEL: setle: ; RV32ZICOND-LABEL: setle:
; RV32ZICOND: # %bb.0: ; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: xor t0, a1, a3
; RV32ZICOND-NEXT: slt a1, a3, a1 ; RV32ZICOND-NEXT: slt a1, a3, a1
; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a1, a0, a1 ; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 ; RV32ZICOND-NEXT: czero.nez a0, a4, a1
; RV32ZICOND-NEXT: czero.nez a2, a4, a1 ; RV32ZICOND-NEXT: czero.eqz a2, a6, a1
; RV32ZICOND-NEXT: or a0, a2, a0 ; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 ; RV32ZICOND-NEXT: czero.nez a2, a5, a1
; RV32ZICOND-NEXT: czero.nez a1, a5, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a7, a1
; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: setle: ; RV64ZICOND-LABEL: setle:
; RV64ZICOND: # %bb.0: ; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: slt a0, a1, a0 ; RV64ZICOND-NEXT: slt a0, a1, a0
; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a1, a2, a0
; RV64ZICOND-NEXT: czero.nez a0, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a3, a0
; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: ret ; RV64ZICOND-NEXT: ret
%rc = icmp sle i64 %a, %b %rc = icmp sle i64 %a, %b
%sel = select i1 %rc, i64 %rs1, i64 %rs2 %sel = select i1 %rc, i64 %rs1, i64 %rs2
ret i64 %sel ret i64 %sel
} }
define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
} }
define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setuge: ; RV32I-LABEL: setuge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB28_2 ; RV32I-NEXT: beq a1, a3, .LBB28_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a1, a3 ; RV32I-NEXT: sltu a0, a1, a3
; RV32I-NEXT: bnez a0, .LBB28_3 ; RV32I-NEXT: beqz a0, .LBB28_3
; RV32I-NEXT: j .LBB28_4 ; RV32I-NEXT: j .LBB28_4
; RV32I-NEXT: .LBB28_2: ; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: sltu a0, a0, a2 ; RV32I-NEXT: sltu a0, a0, a2
; RV32I-NEXT: beqz a0, .LBB28_4 ; RV32I-NEXT: bnez a0, .LBB28_4
; RV32I-NEXT: .LBB28_3: ; RV32I-NEXT: .LBB28_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: .LBB28_4: ; RV32I-NEXT: .LBB28_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: setuge: ; RV64I-LABEL: setuge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a0, a1, .LBB28_2 ; RV64I-NEXT: bltu a0, a1, .LBB28_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a3, a2
; RV64I-NEXT: .LBB28_2: ; RV64I-NEXT: .LBB28_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64XVENTANACONDOPS-LABEL: setuge: ; RV64XVENTANACONDOPS-LABEL: setuge:
; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0
; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret ; RV64XVENTANACONDOPS-NEXT: ret
; ;
; RV64XTHEADCONDMOV-LABEL: setuge: ; RV64XTHEADCONDMOV-LABEL: setuge:
; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a1 ; RV64XTHEADCONDMOV-NEXT: sltu a0, a0, a1
; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 ; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0
; RV64XTHEADCONDMOV-NEXT: mv a0, a2 ; RV64XTHEADCONDMOV-NEXT: mv a0, a2
; RV64XTHEADCONDMOV-NEXT: ret ; RV64XTHEADCONDMOV-NEXT: ret
; ;
; RV32ZICOND-LABEL: setuge: ; RV32ZICOND-LABEL: setuge:
; RV32ZICOND: # %bb.0: ; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: xor t0, a1, a3
; RV32ZICOND-NEXT: sltu a1, a1, a3 ; RV32ZICOND-NEXT: sltu a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: sltu a0, a0, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a1, a0, a1 ; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 ; RV32ZICOND-NEXT: czero.nez a0, a4, a1
; RV32ZICOND-NEXT: czero.nez a2, a4, a1 ; RV32ZICOND-NEXT: czero.eqz a2, a6, a1
; RV32ZICOND-NEXT: or a0, a2, a0 ; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 ; RV32ZICOND-NEXT: czero.nez a2, a5, a1
; RV32ZICOND-NEXT: czero.nez a1, a5, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a7, a1
; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: setuge: ; RV64ZICOND-LABEL: setuge:
; RV64ZICOND: # %bb.0: ; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: sltu a0, a0, a1 ; RV64ZICOND-NEXT: sltu a0, a0, a1
; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a1, a2, a0
; RV64ZICOND-NEXT: czero.nez a0, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a3, a0
; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: ret ; RV64ZICOND-NEXT: ret
%rc = icmp uge i64 %a, %b %rc = icmp uge i64 %a, %b
%sel = select i1 %rc, i64 %rs1, i64 %rs2 %sel = select i1 %rc, i64 %rs1, i64 %rs2
ret i64 %sel ret i64 %sel
} }
define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
} }
define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-LABEL: setule: ; RV32I-LABEL: setule:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB30_2 ; RV32I-NEXT: beq a1, a3, .LBB30_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a3, a1 ; RV32I-NEXT: sltu a0, a3, a1
; RV32I-NEXT: bnez a0, .LBB30_3 ; RV32I-NEXT: beqz a0, .LBB30_3
; RV32I-NEXT: j .LBB30_4 ; RV32I-NEXT: j .LBB30_4
; RV32I-NEXT: .LBB30_2: ; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: beqz a0, .LBB30_4 ; RV32I-NEXT: bnez a0, .LBB30_4
; RV32I-NEXT: .LBB30_3: ; RV32I-NEXT: .LBB30_3:
; RV32I-NEXT: mv a4, a6 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: .LBB30_4: ; RV32I-NEXT: .LBB30_4:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: setule: ; RV64I-LABEL: setule:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a0, .LBB30_2 ; RV64I-NEXT: bltu a1, a0, .LBB30_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a3, a2
; RV64I-NEXT: .LBB30_2: ; RV64I-NEXT: .LBB30_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64XVENTANACONDOPS-LABEL: setule: ; RV64XVENTANACONDOPS-LABEL: setule:
; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0
; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret ; RV64XVENTANACONDOPS-NEXT: ret
; ;
; RV64XTHEADCONDMOV-LABEL: setule: ; RV64XTHEADCONDMOV-LABEL: setule:
; RV64XTHEADCONDMOV: # %bb.0: ; RV64XTHEADCONDMOV: # %bb.0:
; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a0 ; RV64XTHEADCONDMOV-NEXT: sltu a0, a1, a0
; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0 ; RV64XTHEADCONDMOV-NEXT: th.mvnez a2, a3, a0
; RV64XTHEADCONDMOV-NEXT: mv a0, a2 ; RV64XTHEADCONDMOV-NEXT: mv a0, a2
; RV64XTHEADCONDMOV-NEXT: ret ; RV64XTHEADCONDMOV-NEXT: ret
; ;
; RV32ZICOND-LABEL: setule: ; RV32ZICOND-LABEL: setule:
; RV32ZICOND: # %bb.0: ; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xor t0, a1, a3 ; RV32ZICOND-NEXT: xor t0, a1, a3
; RV32ZICOND-NEXT: sltu a1, a3, a1 ; RV32ZICOND-NEXT: sltu a1, a3, a1
; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0
; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: czero.nez a0, a0, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0
; RV32ZICOND-NEXT: or a1, a0, a1 ; RV32ZICOND-NEXT: or a1, a0, a1
; RV32ZICOND-NEXT: czero.eqz a0, a6, a1 ; RV32ZICOND-NEXT: czero.nez a0, a4, a1
; RV32ZICOND-NEXT: czero.nez a2, a4, a1 ; RV32ZICOND-NEXT: czero.eqz a2, a6, a1
; RV32ZICOND-NEXT: or a0, a2, a0 ; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: czero.eqz a2, a7, a1 ; RV32ZICOND-NEXT: czero.nez a2, a5, a1
; RV32ZICOND-NEXT: czero.nez a1, a5, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a7, a1
; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: setule: ; RV64ZICOND-LABEL: setule:
; RV64ZICOND: # %bb.0: ; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: sltu a0, a1, a0 ; RV64ZICOND-NEXT: sltu a0, a1, a0
; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a1, a2, a0
; RV64ZICOND-NEXT: czero.nez a0, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a3, a0
; RV64ZICOND-NEXT: or a0, a0, a1 ; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: ret ; RV64ZICOND-NEXT: ret
%rc = icmp ule i64 %a, %b %rc = icmp ule i64 %a, %b
%sel = select i1 %rc, i64 %rs1, i64 %rs2 %sel = select i1 %rc, i64 %rs1, i64 %rs2
ret i64 %sel ret i64 %sel
} }
define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) { define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
▲ Show 20 Lines • Show All 1,777 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-select-icmp.ll

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; RV64ZDINX-NEXT: ret
%1 = icmp ugt i32 %a, %b %1 = icmp ugt i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_uge: ; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2 ; CHECK-NEXT: bltu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: fmv.d fa1, fa0
; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; RV32ZDINX-LABEL: select_icmp_uge: ; RV32ZDINX-LABEL: select_icmp_uge:
; RV32ZDINX: # %bb.0: ; RV32ZDINX: # %bb.0:
; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: bltu a0, a1, .LBB3_2 ; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: # %bb.1: ; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: .LBB3_2:
; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2
; RV32ZDINX-NEXT: # %bb.1:
; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: .LBB3_2:
; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp)
; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp)
; RV32ZDINX-NEXT: addi sp, sp, 16 ; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret ; RV32ZDINX-NEXT: ret
; ;
; RV64ZDINX-LABEL: select_icmp_uge: ; RV64ZDINX-LABEL: select_icmp_uge:
; RV64ZDINX: # %bb.0: ; RV64ZDINX: # %bb.0:
; RV64ZDINX-NEXT: bgeu a0, a1, .LBB3_2 ; RV64ZDINX-NEXT: bltu a0, a1, .LBB3_2
; RV64ZDINX-NEXT: # %bb.1: ; RV64ZDINX-NEXT: # %bb.1:
; RV64ZDINX-NEXT: mv a2, a3 ; RV64ZDINX-NEXT: mv a3, a2
; RV64ZDINX-NEXT: .LBB3_2: ; RV64ZDINX-NEXT: .LBB3_2:
; RV64ZDINX-NEXT: mv a0, a2 ; RV64ZDINX-NEXT: mv a0, a3
; RV64ZDINX-NEXT: ret ; RV64ZDINX-NEXT: ret
%1 = icmp uge i32 %a, %b %1 = icmp uge i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ult: ; CHECK-LABEL: select_icmp_ult:
Show All 37 Lines; RV64ZDINX-NEXT: ret
%1 = icmp ult i32 %a, %b %1 = icmp ult i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_ule: ; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2 ; CHECK-NEXT: bltu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: fmv.d fa1, fa0
; CHECK-NEXT: .LBB5_2: ; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; RV32ZDINX-LABEL: select_icmp_ule: ; RV32ZDINX-LABEL: select_icmp_ule:
; RV32ZDINX: # %bb.0: ; RV32ZDINX: # %bb.0:
; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: bltu a1, a0, .LBB5_2 ; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: # %bb.1: ; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: .LBB5_2:
; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2
; RV32ZDINX-NEXT: # %bb.1:
; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: .LBB5_2:
; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp)
; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp)
; RV32ZDINX-NEXT: addi sp, sp, 16 ; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret ; RV32ZDINX-NEXT: ret
; ;
; RV64ZDINX-LABEL: select_icmp_ule: ; RV64ZDINX-LABEL: select_icmp_ule:
; RV64ZDINX: # %bb.0: ; RV64ZDINX: # %bb.0:
; RV64ZDINX-NEXT: bgeu a1, a0, .LBB5_2 ; RV64ZDINX-NEXT: bltu a1, a0, .LBB5_2
; RV64ZDINX-NEXT: # %bb.1: ; RV64ZDINX-NEXT: # %bb.1:
; RV64ZDINX-NEXT: mv a2, a3 ; RV64ZDINX-NEXT: mv a3, a2
; RV64ZDINX-NEXT: .LBB5_2: ; RV64ZDINX-NEXT: .LBB5_2:
; RV64ZDINX-NEXT: mv a0, a2 ; RV64ZDINX-NEXT: mv a0, a3
; RV64ZDINX-NEXT: ret ; RV64ZDINX-NEXT: ret
%1 = icmp ule i32 %a, %b %1 = icmp ule i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sgt: ; CHECK-LABEL: select_icmp_sgt:
Show All 37 Lines; RV64ZDINX-NEXT: ret
%1 = icmp sgt i32 %a, %b %1 = icmp sgt i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sge: ; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2 ; CHECK-NEXT: blt a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: fmv.d fa1, fa0
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; RV32ZDINX-LABEL: select_icmp_sge: ; RV32ZDINX-LABEL: select_icmp_sge:
; RV32ZDINX: # %bb.0: ; RV32ZDINX: # %bb.0:
; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: blt a0, a1, .LBB7_2 ; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: # %bb.1: ; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: .LBB7_2:
; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2
; RV32ZDINX-NEXT: # %bb.1:
; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: .LBB7_2:
; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp)
; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp)
; RV32ZDINX-NEXT: addi sp, sp, 16 ; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret ; RV32ZDINX-NEXT: ret
; ;
; RV64ZDINX-LABEL: select_icmp_sge: ; RV64ZDINX-LABEL: select_icmp_sge:
; RV64ZDINX: # %bb.0: ; RV64ZDINX: # %bb.0:
; RV64ZDINX-NEXT: bge a0, a1, .LBB7_2 ; RV64ZDINX-NEXT: blt a0, a1, .LBB7_2
; RV64ZDINX-NEXT: # %bb.1: ; RV64ZDINX-NEXT: # %bb.1:
; RV64ZDINX-NEXT: mv a2, a3 ; RV64ZDINX-NEXT: mv a3, a2
; RV64ZDINX-NEXT: .LBB7_2: ; RV64ZDINX-NEXT: .LBB7_2:
; RV64ZDINX-NEXT: mv a0, a2 ; RV64ZDINX-NEXT: mv a0, a3
; RV64ZDINX-NEXT: ret ; RV64ZDINX-NEXT: ret
%1 = icmp sge i32 %a, %b %1 = icmp sge i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_slt: ; CHECK-LABEL: select_icmp_slt:
Show All 37 Lines; RV64ZDINX-NEXT: ret
%1 = icmp slt i32 %a, %b %1 = icmp slt i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) { define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) {
; CHECK-LABEL: select_icmp_sle: ; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2 ; CHECK-NEXT: blt a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.d fa0, fa1 ; CHECK-NEXT: fmv.d fa1, fa0
; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: fmv.d fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; RV32ZDINX-LABEL: select_icmp_sle: ; RV32ZDINX-LABEL: select_icmp_sle:
; RV32ZDINX: # %bb.0: ; RV32ZDINX: # %bb.0:
; RV32ZDINX-NEXT: addi sp, sp, -16 ; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: sw a2, 8(sp) ; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp) ; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: blt a1, a0, .LBB9_2 ; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: # %bb.1: ; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: lw a4, 8(sp)
; RV32ZDINX-NEXT: lw a5, 12(sp)
; RV32ZDINX-NEXT: .LBB9_2:
; RV32ZDINX-NEXT: sw a4, 8(sp) ; RV32ZDINX-NEXT: sw a4, 8(sp)
; RV32ZDINX-NEXT: sw a5, 12(sp) ; RV32ZDINX-NEXT: sw a5, 12(sp)
; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2
; RV32ZDINX-NEXT: # %bb.1:
; RV32ZDINX-NEXT: lw a2, 8(sp)
; RV32ZDINX-NEXT: lw a3, 12(sp)
; RV32ZDINX-NEXT: .LBB9_2:
; RV32ZDINX-NEXT: sw a2, 8(sp)
; RV32ZDINX-NEXT: sw a3, 12(sp)
; RV32ZDINX-NEXT: lw a0, 8(sp) ; RV32ZDINX-NEXT: lw a0, 8(sp)
; RV32ZDINX-NEXT: lw a1, 12(sp) ; RV32ZDINX-NEXT: lw a1, 12(sp)
; RV32ZDINX-NEXT: addi sp, sp, 16 ; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret ; RV32ZDINX-NEXT: ret
; ;
; RV64ZDINX-LABEL: select_icmp_sle: ; RV64ZDINX-LABEL: select_icmp_sle:
; RV64ZDINX: # %bb.0: ; RV64ZDINX: # %bb.0:
; RV64ZDINX-NEXT: bge a1, a0, .LBB9_2 ; RV64ZDINX-NEXT: blt a1, a0, .LBB9_2
; RV64ZDINX-NEXT: # %bb.1: ; RV64ZDINX-NEXT: # %bb.1:
; RV64ZDINX-NEXT: mv a2, a3 ; RV64ZDINX-NEXT: mv a3, a2
; RV64ZDINX-NEXT: .LBB9_2: ; RV64ZDINX-NEXT: .LBB9_2:
; RV64ZDINX-NEXT: mv a0, a2 ; RV64ZDINX-NEXT: mv a0, a3
; RV64ZDINX-NEXT: ret ; RV64ZDINX-NEXT: ret
%1 = icmp sle i32 %a, %b %1 = icmp sle i32 %a, %b
%2 = select i1 %1, double %c, double %d %2 = select i1 %1, double %c, double %d
ret double %2 ret double %2
} }
define double @select_icmp_slt_one(i32 signext %a) { define double @select_icmp_slt_one(i32 signext %a) {
; CHECK-LABEL: select_icmp_slt_one: ; CHECK-LABEL: select_icmp_slt_one:
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-select-icmp.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; CHECKZFINX-NEXT: ret
%1 = icmp ugt i32 %a, %b %1 = icmp ugt i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_uge(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_uge(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_uge: ; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2 ; CHECK-NEXT: bltu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: fmv.s fa1, fa0
; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKZFINX-LABEL: select_icmp_uge: ; CHECKZFINX-LABEL: select_icmp_uge:
; CHECKZFINX: # %bb.0: ; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: bgeu a0, a1, .LBB3_2 ; CHECKZFINX-NEXT: bltu a0, a1, .LBB3_2
; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: # %bb.1:
; CHECKZFINX-NEXT: mv a2, a3 ; CHECKZFINX-NEXT: mv a3, a2
; CHECKZFINX-NEXT: .LBB3_2: ; CHECKZFINX-NEXT: .LBB3_2:
; CHECKZFINX-NEXT: mv a0, a2 ; CHECKZFINX-NEXT: mv a0, a3
; CHECKZFINX-NEXT: ret ; CHECKZFINX-NEXT: ret
%1 = icmp uge i32 %a, %b %1 = icmp uge i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_ult(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_ult(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ult: ; CHECK-LABEL: select_icmp_ult:
Show All 15 Lines; CHECKZFINX-NEXT: ret
%1 = icmp ult i32 %a, %b %1 = icmp ult i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_ule(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_ule(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_ule: ; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2 ; CHECK-NEXT: bltu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: fmv.s fa1, fa0
; CHECK-NEXT: .LBB5_2: ; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKZFINX-LABEL: select_icmp_ule: ; CHECKZFINX-LABEL: select_icmp_ule:
; CHECKZFINX: # %bb.0: ; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: bgeu a1, a0, .LBB5_2 ; CHECKZFINX-NEXT: bltu a1, a0, .LBB5_2
; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: # %bb.1:
; CHECKZFINX-NEXT: mv a2, a3 ; CHECKZFINX-NEXT: mv a3, a2
; CHECKZFINX-NEXT: .LBB5_2: ; CHECKZFINX-NEXT: .LBB5_2:
; CHECKZFINX-NEXT: mv a0, a2 ; CHECKZFINX-NEXT: mv a0, a3
; CHECKZFINX-NEXT: ret ; CHECKZFINX-NEXT: ret
%1 = icmp ule i32 %a, %b %1 = icmp ule i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_sgt(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_sgt(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sgt: ; CHECK-LABEL: select_icmp_sgt:
Show All 15 Lines; CHECKZFINX-NEXT: ret
%1 = icmp sgt i32 %a, %b %1 = icmp sgt i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_sge(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_sge(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sge: ; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2 ; CHECK-NEXT: blt a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: fmv.s fa1, fa0
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKZFINX-LABEL: select_icmp_sge: ; CHECKZFINX-LABEL: select_icmp_sge:
; CHECKZFINX: # %bb.0: ; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: bge a0, a1, .LBB7_2 ; CHECKZFINX-NEXT: blt a0, a1, .LBB7_2
; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: # %bb.1:
; CHECKZFINX-NEXT: mv a2, a3 ; CHECKZFINX-NEXT: mv a3, a2
; CHECKZFINX-NEXT: .LBB7_2: ; CHECKZFINX-NEXT: .LBB7_2:
; CHECKZFINX-NEXT: mv a0, a2 ; CHECKZFINX-NEXT: mv a0, a3
; CHECKZFINX-NEXT: ret ; CHECKZFINX-NEXT: ret
%1 = icmp sge i32 %a, %b %1 = icmp sge i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_slt(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_slt(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_slt: ; CHECK-LABEL: select_icmp_slt:
Show All 15 Lines; CHECKZFINX-NEXT: ret
%1 = icmp slt i32 %a, %b %1 = icmp slt i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_sle(i32 signext %a, i32 signext %b, float %c, float %d) { define float @select_icmp_sle(i32 signext %a, i32 signext %b, float %c, float %d) {
; CHECK-LABEL: select_icmp_sle: ; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2 ; CHECK-NEXT: blt a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s fa0, fa1 ; CHECK-NEXT: fmv.s fa1, fa0
; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKZFINX-LABEL: select_icmp_sle: ; CHECKZFINX-LABEL: select_icmp_sle:
; CHECKZFINX: # %bb.0: ; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: bge a1, a0, .LBB9_2 ; CHECKZFINX-NEXT: blt a1, a0, .LBB9_2
; CHECKZFINX-NEXT: # %bb.1: ; CHECKZFINX-NEXT: # %bb.1:
; CHECKZFINX-NEXT: mv a2, a3 ; CHECKZFINX-NEXT: mv a3, a2
; CHECKZFINX-NEXT: .LBB9_2: ; CHECKZFINX-NEXT: .LBB9_2:
; CHECKZFINX-NEXT: mv a0, a2 ; CHECKZFINX-NEXT: mv a0, a3
; CHECKZFINX-NEXT: ret ; CHECKZFINX-NEXT: ret
%1 = icmp sle i32 %a, %b %1 = icmp sle i32 %a, %b
%2 = select i1 %1, float %c, float %d %2 = select i1 %1, float %c, float %d
ret float %2 ret float %2
} }
define float @select_icmp_slt_one(i32 signext %a) { define float @select_icmp_slt_one(i32 signext %a) {
; CHECK-LABEL: select_icmp_slt_one: ; CHECK-LABEL: select_icmp_slt_one:
Show All 31 Lines

llvm/test/CodeGen/RISCV/forced-atomics.ll

Show First 20 Lines • Show All 1,461 Lines • ▼ Show 20 Lines
} }
define i32 @rmw32_min_seq_cst(ptr %p) nounwind { define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-LABEL: rmw32_min_seq_cst: ; RV32-NO-ATOMIC-LABEL: rmw32_min_seq_cst:
; RV32-NO-ATOMIC: # %bb.0: ; RV32-NO-ATOMIC: # %bb.0:
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0)
; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB24_2 ; RV32-NO-ATOMIC-NEXT: j .LBB24_2
; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: li a0, 1
; RV32-NO-ATOMIC-NEXT: mv a2, a1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1
; RV32-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 ; RV32-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 1
; RV32-NO-ATOMIC-NEXT: j .LBB24_1 ; RV32-NO-ATOMIC-NEXT: j .LBB24_1
; RV32-NO-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.end ; RV32-NO-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.end
; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret ; RV32-NO-ATOMIC-NEXT: ret
; ;
; RV32-ATOMIC-LABEL: rmw32_min_seq_cst: ; RV32-ATOMIC-LABEL: rmw32_min_seq_cst:
; RV32-ATOMIC: # %bb.0: ; RV32-ATOMIC: # %bb.0:
; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: addi sp, sp, -16
; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ATOMIC-NEXT: li a1, 1 ; RV32-ATOMIC-NEXT: li a1, 1
Show All 12 Lines
; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16
; RV32-ATOMIC-TRAILING-NEXT: ret ; RV32-ATOMIC-TRAILING-NEXT: ret
; ;
; RV64-NO-ATOMIC-LABEL: rmw32_min_seq_cst: ; RV64-NO-ATOMIC-LABEL: rmw32_min_seq_cst:
; RV64-NO-ATOMIC: # %bb.0: ; RV64-NO-ATOMIC: # %bb.0:
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0)
; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB24_2 ; RV64-NO-ATOMIC-NEXT: j .LBB24_2
; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1 ; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB24_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB24_1 ; RV64-NO-ATOMIC-NEXT: j .LBB24_1
; RV64-NO-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB24_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret ; RV64-NO-ATOMIC-NEXT: ret
; ;
; RV64-ATOMIC-LABEL: rmw32_min_seq_cst: ; RV64-ATOMIC-LABEL: rmw32_min_seq_cst:
; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC: # %bb.0:
; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: addi sp, sp, -16
; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ATOMIC-NEXT: li a1, 1 ; RV64-ATOMIC-NEXT: li a1, 1
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
} }
define i32 @rmw32_umin_seq_cst(ptr %p) nounwind { define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-LABEL: rmw32_umin_seq_cst: ; RV32-NO-ATOMIC-LABEL: rmw32_umin_seq_cst:
; RV32-NO-ATOMIC: # %bb.0: ; RV32-NO-ATOMIC: # %bb.0:
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0 ; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0) ; RV32-NO-ATOMIC-NEXT: lw a1, 0(a0)
; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB26_2 ; RV32-NO-ATOMIC-NEXT: j .LBB26_2
; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: mv a1, sp ; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp) ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: li a0, 1
; RV32-NO-ATOMIC-NEXT: mv a2, a1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1
; RV32-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 ; RV32-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 1
; RV32-NO-ATOMIC-NEXT: j .LBB26_1 ; RV32-NO-ATOMIC-NEXT: j .LBB26_1
; RV32-NO-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.end ; RV32-NO-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.end
; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16 ; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret ; RV32-NO-ATOMIC-NEXT: ret
; ;
; RV32-ATOMIC-LABEL: rmw32_umin_seq_cst: ; RV32-ATOMIC-LABEL: rmw32_umin_seq_cst:
; RV32-ATOMIC: # %bb.0: ; RV32-ATOMIC: # %bb.0:
; RV32-ATOMIC-NEXT: addi sp, sp, -16 ; RV32-ATOMIC-NEXT: addi sp, sp, -16
; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ATOMIC-NEXT: li a1, 1 ; RV32-ATOMIC-NEXT: li a1, 1
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; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16 ; RV32-ATOMIC-TRAILING-NEXT: addi sp, sp, 16
; RV32-ATOMIC-TRAILING-NEXT: ret ; RV32-ATOMIC-TRAILING-NEXT: ret
; ;
; RV64-NO-ATOMIC-LABEL: rmw32_umin_seq_cst: ; RV64-NO-ATOMIC-LABEL: rmw32_umin_seq_cst:
; RV64-NO-ATOMIC: # %bb.0: ; RV64-NO-ATOMIC: # %bb.0:
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0) ; RV64-NO-ATOMIC-NEXT: lw a1, 0(a0)
; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB26_2 ; RV64-NO-ATOMIC-NEXT: j .LBB26_2
; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4 ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1 ; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB26_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB26_1 ; RV64-NO-ATOMIC-NEXT: j .LBB26_1
; RV64-NO-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB26_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret ; RV64-NO-ATOMIC-NEXT: ret
; ;
; RV64-ATOMIC-LABEL: rmw32_umin_seq_cst: ; RV64-ATOMIC-LABEL: rmw32_umin_seq_cst:
; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC: # %bb.0:
; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: addi sp, sp, -16
; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ATOMIC-NEXT: li a1, 1 ; RV64-ATOMIC-NEXT: li a1, 1
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0 ; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a1, 4(a0) ; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a4, 0(a0) ; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: j .LBB50_2 ; RV32-NEXT: j .LBB50_2
; RV32-NEXT: .LBB50_1: # %atomicrmw.start ; RV32-NEXT: .LBB50_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32-NEXT: neg a3, a0 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a3, a3, a1 ; RV32-NEXT: and a3, a0, a1
; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a4, 0(sp)
; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a1, 4(sp)
; RV32-NEXT: mv a1, sp ; RV32-NEXT: mv a1, sp
; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0 ; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt ; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a1, 4(sp)
; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: lw a4, 0(sp)
; RV32-NEXT: bnez a0, .LBB50_6 ; RV32-NEXT: bnez a0, .LBB50_6
; RV32-NEXT: .LBB50_2: # %atomicrmw.start ; RV32-NEXT: .LBB50_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: beqz a1, .LBB50_4 ; RV32-NEXT: beqz a1, .LBB50_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32-NEXT: slti a0, a1, 0 ; RV32-NEXT: sgtz a0, a1
; RV32-NEXT: mv a2, a4 ; RV32-NEXT: li a2, 1
; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: bnez a0, .LBB50_1
; RV32-NEXT: j .LBB50_5 ; RV32-NEXT: j .LBB50_5
; RV32-NEXT: .LBB50_4: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: .LBB50_4: # in Loop: Header=BB50_2 Depth=1
; RV32-NEXT: sltiu a0, a4, 2 ; RV32-NEXT: sltiu a0, a4, 2
; RV32-NEXT: mv a2, a4 ; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: li a2, 1
; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: bnez a0, .LBB50_1
; RV32-NEXT: .LBB50_5: # %atomicrmw.start ; RV32-NEXT: .LBB50_5: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32-NEXT: li a2, 1 ; RV32-NEXT: mv a2, a4
; RV32-NEXT: j .LBB50_1 ; RV32-NEXT: j .LBB50_1
; RV32-NEXT: .LBB50_6: # %atomicrmw.end ; RV32-NEXT: .LBB50_6: # %atomicrmw.end
; RV32-NEXT: mv a0, a4 ; RV32-NEXT: mv a0, a4
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-NO-ATOMIC-LABEL: rmw64_min_seq_cst: ; RV64-NO-ATOMIC-LABEL: rmw64_min_seq_cst:
; RV64-NO-ATOMIC: # %bb.0: ; RV64-NO-ATOMIC: # %bb.0:
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0)
; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB50_2 ; RV64-NO-ATOMIC-NEXT: j .LBB50_2
; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: mv a1, sp ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt
; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4
; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB50_1 ; RV64-NO-ATOMIC-NEXT: bge a0, a1, .LBB50_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB50_1 ; RV64-NO-ATOMIC-NEXT: j .LBB50_1
; RV64-NO-ATOMIC-NEXT: .LBB50_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB50_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret ; RV64-NO-ATOMIC-NEXT: ret
; ;
; RV64-ATOMIC-LABEL: rmw64_min_seq_cst: ; RV64-ATOMIC-LABEL: rmw64_min_seq_cst:
; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC: # %bb.0:
; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: addi sp, sp, -16
; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ATOMIC-NEXT: li a1, 1 ; RV64-ATOMIC-NEXT: li a1, 1
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0 ; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a1, 4(a0) ; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a4, 0(a0) ; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: j .LBB52_2 ; RV32-NEXT: j .LBB52_2
; RV32-NEXT: .LBB52_1: # %atomicrmw.start ; RV32-NEXT: .LBB52_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32-NEXT: neg a3, a0 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a3, a3, a1 ; RV32-NEXT: and a3, a0, a1
; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a4, 0(sp)
; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a1, 4(sp)
; RV32-NEXT: mv a1, sp ; RV32-NEXT: mv a1, sp
; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0 ; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt ; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a1, 4(sp) ; RV32-NEXT: lw a1, 4(sp)
; RV32-NEXT: lw a4, 0(sp) ; RV32-NEXT: lw a4, 0(sp)
; RV32-NEXT: bnez a0, .LBB52_4 ; RV32-NEXT: bnez a0, .LBB52_4
; RV32-NEXT: .LBB52_2: # %atomicrmw.start ; RV32-NEXT: .LBB52_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: sltiu a0, a4, 2 ; RV32-NEXT: snez a0, a1
; RV32-NEXT: seqz a2, a1 ; RV32-NEXT: sltiu a2, a4, 2
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: mv a2, a4 ; RV32-NEXT: or a0, a2, a0
; RV32-NEXT: li a2, 1
; RV32-NEXT: bnez a0, .LBB52_1 ; RV32-NEXT: bnez a0, .LBB52_1
; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32-NEXT: li a2, 1 ; RV32-NEXT: mv a2, a4
; RV32-NEXT: j .LBB52_1 ; RV32-NEXT: j .LBB52_1
; RV32-NEXT: .LBB52_4: # %atomicrmw.end ; RV32-NEXT: .LBB52_4: # %atomicrmw.end
; RV32-NEXT: mv a0, a4 ; RV32-NEXT: mv a0, a4
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-NO-ATOMIC-LABEL: rmw64_umin_seq_cst: ; RV64-NO-ATOMIC-LABEL: rmw64_umin_seq_cst:
; RV64-NO-ATOMIC: # %bb.0: ; RV64-NO-ATOMIC: # %bb.0:
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0) ; RV64-NO-ATOMIC-NEXT: ld a1, 0(a0)
; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB52_2 ; RV64-NO-ATOMIC-NEXT: j .LBB52_2
; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: mv a1, sp ; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt
; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp) ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4
; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB52_1 ; RV64-NO-ATOMIC-NEXT: bgeu a0, a1, .LBB52_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB52_1 ; RV64-NO-ATOMIC-NEXT: j .LBB52_1
; RV64-NO-ATOMIC-NEXT: .LBB52_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB52_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32 ; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret ; RV64-NO-ATOMIC-NEXT: ret
; ;
; RV64-ATOMIC-LABEL: rmw64_umin_seq_cst: ; RV64-ATOMIC-LABEL: rmw64_umin_seq_cst:
; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC: # %bb.0:
; RV64-ATOMIC-NEXT: addi sp, sp, -16 ; RV64-ATOMIC-NEXT: addi sp, sp, -16
; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-ATOMIC-NEXT: li a1, 1 ; RV64-ATOMIC-NEXT: li a1, 1
▲ Show 20 Lines • Show All 920 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-select-icmp.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ugt i32 %a, %b %1 = icmp ugt i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_uge: ; CHECK-LABEL: select_icmp_uge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2 ; CHECK-NEXT: bltu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: fmv.h fa1, fa0
; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKIZHINX-LABEL: select_icmp_uge: ; CHECKIZHINX-LABEL: select_icmp_uge:
; CHECKIZHINX: # %bb.0: ; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2 ; CHECKIZHINX-NEXT: bltu a0, a1, .LBB3_2
; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: mv a2, a3 ; CHECKIZHINX-NEXT: mv a3, a2
; CHECKIZHINX-NEXT: .LBB3_2: ; CHECKIZHINX-NEXT: .LBB3_2:
; CHECKIZHINX-NEXT: mv a0, a2 ; CHECKIZHINX-NEXT: mv a0, a3
; CHECKIZHINX-NEXT: ret ; CHECKIZHINX-NEXT: ret
; ;
; CHECKIZFHMIN-LABEL: select_icmp_uge: ; CHECKIZFHMIN-LABEL: select_icmp_uge:
; CHECKIZFHMIN: # %bb.0: ; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2 ; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB3_2
; CHECKIZFHMIN-NEXT: # %bb.1: ; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; CHECKIZFHMIN-NEXT: .LBB3_2: ; CHECKIZFHMIN-NEXT: .LBB3_2:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; ;
; CHECKIZHINXMIN-LABEL: select_icmp_uge: ; CHECKIZHINXMIN-LABEL: select_icmp_uge:
; CHECKIZHINXMIN: # %bb.0: ; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2 ; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB3_2
; CHECKIZHINXMIN-NEXT: # %bb.1: ; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
; CHECKIZHINXMIN-NEXT: .LBB3_2: ; CHECKIZHINXMIN-NEXT: .LBB3_2:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
%1 = icmp uge i32 %a, %b %1 = icmp uge i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
Show All 40 Lines; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ult i32 %a, %b %1 = icmp ult i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_ule: ; CHECK-LABEL: select_icmp_ule:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2 ; CHECK-NEXT: bltu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: fmv.h fa1, fa0
; CHECK-NEXT: .LBB5_2: ; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKIZHINX-LABEL: select_icmp_ule: ; CHECKIZHINX-LABEL: select_icmp_ule:
; CHECKIZHINX: # %bb.0: ; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2 ; CHECKIZHINX-NEXT: bltu a1, a0, .LBB5_2
; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: mv a2, a3 ; CHECKIZHINX-NEXT: mv a3, a2
; CHECKIZHINX-NEXT: .LBB5_2: ; CHECKIZHINX-NEXT: .LBB5_2:
; CHECKIZHINX-NEXT: mv a0, a2 ; CHECKIZHINX-NEXT: mv a0, a3
; CHECKIZHINX-NEXT: ret ; CHECKIZHINX-NEXT: ret
; ;
; CHECKIZFHMIN-LABEL: select_icmp_ule: ; CHECKIZFHMIN-LABEL: select_icmp_ule:
; CHECKIZFHMIN: # %bb.0: ; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2 ; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB5_2
; CHECKIZFHMIN-NEXT: # %bb.1: ; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; CHECKIZFHMIN-NEXT: .LBB5_2: ; CHECKIZFHMIN-NEXT: .LBB5_2:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; ;
; CHECKIZHINXMIN-LABEL: select_icmp_ule: ; CHECKIZHINXMIN-LABEL: select_icmp_ule:
; CHECKIZHINXMIN: # %bb.0: ; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2 ; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB5_2
; CHECKIZHINXMIN-NEXT: # %bb.1: ; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
; CHECKIZHINXMIN-NEXT: .LBB5_2: ; CHECKIZHINXMIN-NEXT: .LBB5_2:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ule i32 %a, %b %1 = icmp ule i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
Show All 40 Lines; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sgt i32 %a, %b %1 = icmp sgt i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_sge: ; CHECK-LABEL: select_icmp_sge:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2 ; CHECK-NEXT: blt a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: fmv.h fa1, fa0
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKIZHINX-LABEL: select_icmp_sge: ; CHECKIZHINX-LABEL: select_icmp_sge:
; CHECKIZHINX: # %bb.0: ; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2 ; CHECKIZHINX-NEXT: blt a0, a1, .LBB7_2
; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: mv a2, a3 ; CHECKIZHINX-NEXT: mv a3, a2
; CHECKIZHINX-NEXT: .LBB7_2: ; CHECKIZHINX-NEXT: .LBB7_2:
; CHECKIZHINX-NEXT: mv a0, a2 ; CHECKIZHINX-NEXT: mv a0, a3
; CHECKIZHINX-NEXT: ret ; CHECKIZHINX-NEXT: ret
; ;
; CHECKIZFHMIN-LABEL: select_icmp_sge: ; CHECKIZFHMIN-LABEL: select_icmp_sge:
; CHECKIZFHMIN: # %bb.0: ; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2 ; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB7_2
; CHECKIZFHMIN-NEXT: # %bb.1: ; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; CHECKIZFHMIN-NEXT: .LBB7_2: ; CHECKIZFHMIN-NEXT: .LBB7_2:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; ;
; CHECKIZHINXMIN-LABEL: select_icmp_sge: ; CHECKIZHINXMIN-LABEL: select_icmp_sge:
; CHECKIZHINXMIN: # %bb.0: ; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2 ; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB7_2
; CHECKIZHINXMIN-NEXT: # %bb.1: ; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
; CHECKIZHINXMIN-NEXT: .LBB7_2: ; CHECKIZHINXMIN-NEXT: .LBB7_2:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sge i32 %a, %b %1 = icmp sge i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
Show All 40 Lines; CHECKIZHINXMIN-NEXT: ret
%1 = icmp slt i32 %a, %b %1 = icmp slt i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) { define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_sle: ; CHECK-LABEL: select_icmp_sle:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2 ; CHECK-NEXT: blt a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h fa0, fa1 ; CHECK-NEXT: fmv.h fa1, fa0
; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: fmv.h fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECKIZHINX-LABEL: select_icmp_sle: ; CHECKIZHINX-LABEL: select_icmp_sle:
; CHECKIZHINX: # %bb.0: ; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2 ; CHECKIZHINX-NEXT: blt a1, a0, .LBB9_2
; CHECKIZHINX-NEXT: # %bb.1: ; CHECKIZHINX-NEXT: # %bb.1:
; CHECKIZHINX-NEXT: mv a2, a3 ; CHECKIZHINX-NEXT: mv a3, a2
; CHECKIZHINX-NEXT: .LBB9_2: ; CHECKIZHINX-NEXT: .LBB9_2:
; CHECKIZHINX-NEXT: mv a0, a2 ; CHECKIZHINX-NEXT: mv a0, a3
; CHECKIZHINX-NEXT: ret ; CHECKIZHINX-NEXT: ret
; ;
; CHECKIZFHMIN-LABEL: select_icmp_sle: ; CHECKIZFHMIN-LABEL: select_icmp_sle:
; CHECKIZFHMIN: # %bb.0: ; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2 ; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB9_2
; CHECKIZFHMIN-NEXT: # %bb.1: ; CHECKIZFHMIN-NEXT: # %bb.1:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; CHECKIZFHMIN-NEXT: .LBB9_2: ; CHECKIZFHMIN-NEXT: .LBB9_2:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret ; CHECKIZFHMIN-NEXT: ret
; ;
; CHECKIZHINXMIN-LABEL: select_icmp_sle: ; CHECKIZHINXMIN-LABEL: select_icmp_sle:
; CHECKIZHINXMIN: # %bb.0: ; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2 ; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB9_2
; CHECKIZHINXMIN-NEXT: # %bb.1: ; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
; CHECKIZHINXMIN-NEXT: .LBB9_2: ; CHECKIZHINXMIN-NEXT: .LBB9_2:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret ; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sle i32 %a, %b %1 = icmp sle i32 %a, %b
%2 = select i1 %1, half %c, half %d %2 = select i1 %1, half %c, half %d
ret half %2 ret half %2
} }
define half @select_icmp_slt_one(i32 signext %a) { define half @select_icmp_slt_one(i32 signext %a) {
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-cc.ll

Show All 17 Lines
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_4: ; RV32I-NEXT: .LBB0_4:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bltu a2, a0, .LBB0_6 ; RV32I-NEXT: bltu a2, a0, .LBB0_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_6: ; RV32I-NEXT: .LBB0_6:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bgeu a0, a2, .LBB0_8 ; RV32I-NEXT: bltu a0, a2, .LBB0_8
; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB0_8: ; RV32I-NEXT: .LBB0_8:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: bltu a0, a2, .LBB0_10 ; RV32I-NEXT: bltu a2, a0, .LBB0_10
; RV32I-NEXT: # %bb.9: ; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB0_10: ; RV32I-NEXT: .LBB0_10:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: bgeu a2, a0, .LBB0_12 ; RV32I-NEXT: bltu a0, a2, .LBB0_12
; RV32I-NEXT: # %bb.11: ; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_12: ; RV32I-NEXT: .LBB0_12:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: blt a2, a0, .LBB0_14 ; RV32I-NEXT: blt a2, a0, .LBB0_14
; RV32I-NEXT: # %bb.13: ; RV32I-NEXT: # %bb.13:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_14: ; RV32I-NEXT: .LBB0_14:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bge a0, a2, .LBB0_16 ; RV32I-NEXT: blt a0, a2, .LBB0_16
; RV32I-NEXT: # %bb.15: ; RV32I-NEXT: # %bb.15:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB0_16: ; RV32I-NEXT: .LBB0_16:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: blt a0, a2, .LBB0_18 ; RV32I-NEXT: blt a2, a0, .LBB0_18
; RV32I-NEXT: # %bb.17: ; RV32I-NEXT: # %bb.17:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB0_18: ; RV32I-NEXT: .LBB0_18:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: bge a2, a0, .LBB0_20 ; RV32I-NEXT: blt a0, a2, .LBB0_20
; RV32I-NEXT: # %bb.19: ; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_20: ; RV32I-NEXT: .LBB0_20:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: blez a2, .LBB0_22 ; RV32I-NEXT: blez a2, .LBB0_22
; RV32I-NEXT: # %bb.21: ; RV32I-NEXT: # %bb.21:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_22: ; RV32I-NEXT: .LBB0_22:
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; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_4: ; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: bltu a2, a0, .LBB0_6 ; RV64I-NEXT: bltu a2, a0, .LBB0_6
; RV64I-NEXT: # %bb.5: ; RV64I-NEXT: # %bb.5:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_6: ; RV64I-NEXT: .LBB0_6:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: bgeu a0, a2, .LBB0_8 ; RV64I-NEXT: bltu a0, a2, .LBB0_8
; RV64I-NEXT: # %bb.7: ; RV64I-NEXT: # %bb.7:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB0_8: ; RV64I-NEXT: .LBB0_8:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a0, 0(a1)
; RV64I-NEXT: bltu a0, a2, .LBB0_10 ; RV64I-NEXT: bltu a2, a0, .LBB0_10
; RV64I-NEXT: # %bb.9: ; RV64I-NEXT: # %bb.9:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB0_10: ; RV64I-NEXT: .LBB0_10:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a0, 0(a1)
; RV64I-NEXT: bgeu a2, a0, .LBB0_12 ; RV64I-NEXT: bltu a0, a2, .LBB0_12
; RV64I-NEXT: # %bb.11: ; RV64I-NEXT: # %bb.11:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_12: ; RV64I-NEXT: .LBB0_12:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: blt a2, a0, .LBB0_14 ; RV64I-NEXT: blt a2, a0, .LBB0_14
; RV64I-NEXT: # %bb.13: ; RV64I-NEXT: # %bb.13:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_14: ; RV64I-NEXT: .LBB0_14:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: bge a0, a2, .LBB0_16 ; RV64I-NEXT: blt a0, a2, .LBB0_16
; RV64I-NEXT: # %bb.15: ; RV64I-NEXT: # %bb.15:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB0_16: ; RV64I-NEXT: .LBB0_16:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a0, 0(a1)
; RV64I-NEXT: blt a0, a2, .LBB0_18 ; RV64I-NEXT: blt a2, a0, .LBB0_18
; RV64I-NEXT: # %bb.17: ; RV64I-NEXT: # %bb.17:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB0_18: ; RV64I-NEXT: .LBB0_18:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a0, 0(a1)
; RV64I-NEXT: bge a2, a0, .LBB0_20 ; RV64I-NEXT: blt a0, a2, .LBB0_20
; RV64I-NEXT: # %bb.19: ; RV64I-NEXT: # %bb.19:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_20: ; RV64I-NEXT: .LBB0_20:
; RV64I-NEXT: lw a2, 0(a1) ; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: blez a2, .LBB0_22 ; RV64I-NEXT: blez a2, .LBB0_22
; RV64I-NEXT: # %bb.21: ; RV64I-NEXT: # %bb.21:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_22: ; RV64I-NEXT: .LBB0_22:
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
} }
declare void @bar(i16 signext) declare void @bar(i16 signext)
define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) { define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) {
; RV32I-LABEL: select_sge_int16min: ; RV32I-LABEL: select_sge_int16min:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1048560 ; RV32I-NEXT: lui a3, 1048560
; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: blt a0, a3, .LBB2_2
; RV32I-NEXT: blt a3, a0, .LBB2_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: select_sge_int16min: ; RV64I-LABEL: select_sge_int16min:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048560 ; RV64I-NEXT: lui a3, 1048560
; RV64I-NEXT: addiw a3, a3, -1 ; RV64I-NEXT: blt a0, a3, .LBB2_2
; RV64I-NEXT: blt a3, a0, .LBB2_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: .LBB2_2:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a = icmp sge i32 %x, -65536 %a = icmp sge i32 %x, -65536
%b = select i1 %a, i32 %y, i32 %z %b = select i1 %a, i32 %y, i32 %z
ret i32 %b ret i32 %b
} }
define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) { define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
; RV32I-LABEL: select_sge_int32min: ; RV32I-LABEL: select_sge_int32min:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: li a6, -1 ; RV32I-NEXT: li a6, -1
; RV32I-NEXT: bne a1, a6, .LBB3_2 ; RV32I-NEXT: bne a1, a6, .LBB3_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: slti a0, a1, 0 ; RV32I-NEXT: slti a0, a1, -1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: .LBB3_3: ; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: bnez a0, .LBB3_5 ; RV32I-NEXT: bnez a0, .LBB3_5
; RV32I-NEXT: # %bb.4: ; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a4, a2
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: .LBB3_5: ; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: select_sge_int32min: ; RV64I-LABEL: select_sge_int32min:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 524288 ; RV64I-NEXT: lui a3, 524288
; RV64I-NEXT: addi a3, a3, -1 ; RV64I-NEXT: blt a0, a3, .LBB3_2
; RV64I-NEXT: blt a3, a0, .LBB3_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a = icmp sge i64 %x, -2147483648 %a = icmp sge i64 %x, -2147483648
%b = select i1 %a, i64 %y, i64 %z %b = select i1 %a, i64 %y, i64 %z
ret i64 %b ret i64 %b
} }

llvm/test/CodeGen/RISCV/select-constant-xor.ll

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret i32 %s ret i32 %s
} }
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) { define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; RV32-LABEL: oneusecmp: ; RV32-LABEL: oneusecmp:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: srai a3, a0, 31 ; RV32-NEXT: srai a3, a0, 31
; RV32-NEXT: xori a3, a3, 127 ; RV32-NEXT: xori a3, a3, 127
; RV32-NEXT: bltz a0, .LBB10_2 ; RV32-NEXT: bgez a0, .LBB10_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: .LBB10_2: ; RV32-NEXT: .LBB10_2:
; RV32-NEXT: add a0, a3, a2 ; RV32-NEXT: add a0, a3, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: oneusecmp: ; RV64-LABEL: oneusecmp:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sext.w a3, a0 ; RV64-NEXT: sext.w a3, a0
; RV64-NEXT: sraiw a0, a0, 31 ; RV64-NEXT: sraiw a0, a0, 31
; RV64-NEXT: xori a0, a0, 127 ; RV64-NEXT: xori a0, a0, 127
; RV64-NEXT: bltz a3, .LBB10_2 ; RV64-NEXT: bgez a3, .LBB10_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a2, a1 ; RV64-NEXT: mv a1, a2
; RV64-NEXT: .LBB10_2: ; RV64-NEXT: .LBB10_2:
; RV64-NEXT: addw a0, a0, a2 ; RV64-NEXT: addw a0, a0, a1
; RV64-NEXT: ret ; RV64-NEXT: ret
%c = icmp sle i32 %a, -1 %c = icmp sle i32 %a, -1
%s = select i1 %c, i32 -128, i32 127 %s = select i1 %c, i32 -128, i32 127
%s2 = select i1 %c, i32 %d, i32 %b %s2 = select i1 %c, i32 %d, i32 %b
%x = add i32 %s, %s2 %x = add i32 %s, %s2
ret i32 %x ret i32 %x
} }

llvm/test/CodeGen/RISCV/xaluo.ll

Show First 20 Lines • Show All 5,628 Lines • ▼ Show 20 Lines
define zeroext i1 @uaddo.i64.constant(i64 %v1, ptr %res) { define zeroext i1 @uaddo.i64.constant(i64 %v1, ptr %res) {
; RV32-LABEL: uaddo.i64.constant: ; RV32-LABEL: uaddo.i64.constant:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 2 ; RV32-NEXT: addi a3, a0, 2
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: add a4, a1, a0
; RV32-NEXT: sltu a1, a4, a1 ; RV32-NEXT: sltu a1, a4, a1
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uaddo.i64.constant: ; RV64-LABEL: uaddo.i64.constant:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, 2 ; RV64-NEXT: addi a2, a0, 2
; RV64-NEXT: sltu a0, a2, a0 ; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: uaddo.i64.constant: ; RV32ZBA-LABEL: uaddo.i64.constant:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi a3, a0, 2 ; RV32ZBA-NEXT: addi a3, a0, 2
; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: sltu a0, a3, a0
; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: add a4, a1, a0
; RV32ZBA-NEXT: sltu a1, a4, a1 ; RV32ZBA-NEXT: sltu a1, a4, a1
; RV32ZBA-NEXT: and a0, a0, a1 ; RV32ZBA-NEXT: and a0, a1, a0
; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a3, 0(a2)
; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: sw a4, 4(a2)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: uaddo.i64.constant: ; RV64ZBA-LABEL: uaddo.i64.constant:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addi a2, a0, 2 ; RV64ZBA-NEXT: addi a2, a0, 2
; RV64ZBA-NEXT: sltu a0, a2, a0 ; RV64ZBA-NEXT: sltu a0, a2, a0
; RV64ZBA-NEXT: sd a2, 0(a1) ; RV64ZBA-NEXT: sd a2, 0(a1)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
; ;
; RV32ZICOND-LABEL: uaddo.i64.constant: ; RV32ZICOND-LABEL: uaddo.i64.constant:
; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND: # %bb.0: # %entry
; RV32ZICOND-NEXT: addi a3, a0, 2 ; RV32ZICOND-NEXT: addi a3, a0, 2
; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1 ; RV32ZICOND-NEXT: sltu a1, a4, a1
; RV32ZICOND-NEXT: and a0, a0, a1 ; RV32ZICOND-NEXT: and a0, a1, a0
; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: uaddo.i64.constant: ; RV64ZICOND-LABEL: uaddo.i64.constant:
; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: addi a2, a0, 2 ; RV64ZICOND-NEXT: addi a2, a0, 2
; RV64ZICOND-NEXT: sltu a0, a2, a0 ; RV64ZICOND-NEXT: sltu a0, a2, a0
Show All 10 Lines
define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, ptr %res) { define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, ptr %res) {
; RV32-LABEL: uaddo.i64.constant_2048: ; RV32-LABEL: uaddo.i64.constant_2048:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 2047 ; RV32-NEXT: addi a3, a0, 2047
; RV32-NEXT: addi a3, a3, 1 ; RV32-NEXT: addi a3, a3, 1
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: add a4, a1, a0
; RV32-NEXT: sltu a1, a4, a1 ; RV32-NEXT: sltu a1, a4, a1
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uaddo.i64.constant_2048: ; RV64-LABEL: uaddo.i64.constant_2048:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, 2047 ; RV64-NEXT: addi a2, a0, 2047
; RV64-NEXT: addi a2, a2, 1 ; RV64-NEXT: addi a2, a2, 1
; RV64-NEXT: sltu a0, a2, a0 ; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: uaddo.i64.constant_2048: ; RV32ZBA-LABEL: uaddo.i64.constant_2048:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi a3, a0, 2047 ; RV32ZBA-NEXT: addi a3, a0, 2047
; RV32ZBA-NEXT: addi a3, a3, 1 ; RV32ZBA-NEXT: addi a3, a3, 1
; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: sltu a0, a3, a0
; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: add a4, a1, a0
; RV32ZBA-NEXT: sltu a1, a4, a1 ; RV32ZBA-NEXT: sltu a1, a4, a1
; RV32ZBA-NEXT: and a0, a0, a1 ; RV32ZBA-NEXT: and a0, a1, a0
; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a3, 0(a2)
; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: sw a4, 4(a2)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: uaddo.i64.constant_2048: ; RV64ZBA-LABEL: uaddo.i64.constant_2048:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addi a2, a0, 2047 ; RV64ZBA-NEXT: addi a2, a0, 2047
; RV64ZBA-NEXT: addi a2, a2, 1 ; RV64ZBA-NEXT: addi a2, a2, 1
; RV64ZBA-NEXT: sltu a0, a2, a0 ; RV64ZBA-NEXT: sltu a0, a2, a0
; RV64ZBA-NEXT: sd a2, 0(a1) ; RV64ZBA-NEXT: sd a2, 0(a1)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
; ;
; RV32ZICOND-LABEL: uaddo.i64.constant_2048: ; RV32ZICOND-LABEL: uaddo.i64.constant_2048:
; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND: # %bb.0: # %entry
; RV32ZICOND-NEXT: addi a3, a0, 2047 ; RV32ZICOND-NEXT: addi a3, a0, 2047
; RV32ZICOND-NEXT: addi a3, a3, 1 ; RV32ZICOND-NEXT: addi a3, a3, 1
; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1 ; RV32ZICOND-NEXT: sltu a1, a4, a1
; RV32ZICOND-NEXT: and a0, a0, a1 ; RV32ZICOND-NEXT: and a0, a1, a0
; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: uaddo.i64.constant_2048: ; RV64ZICOND-LABEL: uaddo.i64.constant_2048:
; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: addi a2, a0, 2047 ; RV64ZICOND-NEXT: addi a2, a0, 2047
; RV64ZICOND-NEXT: addi a2, a2, 1 ; RV64ZICOND-NEXT: addi a2, a2, 1
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define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, ptr %res) { define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, ptr %res) {
; RV32-LABEL: uaddo.i64.constant_2049: ; RV32-LABEL: uaddo.i64.constant_2049:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 2047 ; RV32-NEXT: addi a3, a0, 2047
; RV32-NEXT: addi a3, a3, 2 ; RV32-NEXT: addi a3, a3, 2
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: add a4, a1, a0
; RV32-NEXT: sltu a1, a4, a1 ; RV32-NEXT: sltu a1, a4, a1
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uaddo.i64.constant_2049: ; RV64-LABEL: uaddo.i64.constant_2049:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, 2047 ; RV64-NEXT: addi a2, a0, 2047
; RV64-NEXT: addi a2, a2, 2 ; RV64-NEXT: addi a2, a2, 2
; RV64-NEXT: sltu a0, a2, a0 ; RV64-NEXT: sltu a0, a2, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: uaddo.i64.constant_2049: ; RV32ZBA-LABEL: uaddo.i64.constant_2049:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi a3, a0, 2047 ; RV32ZBA-NEXT: addi a3, a0, 2047
; RV32ZBA-NEXT: addi a3, a3, 2 ; RV32ZBA-NEXT: addi a3, a3, 2
; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: sltu a0, a3, a0
; RV32ZBA-NEXT: add a4, a1, a0 ; RV32ZBA-NEXT: add a4, a1, a0
; RV32ZBA-NEXT: sltu a1, a4, a1 ; RV32ZBA-NEXT: sltu a1, a4, a1
; RV32ZBA-NEXT: and a0, a0, a1 ; RV32ZBA-NEXT: and a0, a1, a0
; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a3, 0(a2)
; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: sw a4, 4(a2)
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: uaddo.i64.constant_2049: ; RV64ZBA-LABEL: uaddo.i64.constant_2049:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addi a2, a0, 2047 ; RV64ZBA-NEXT: addi a2, a0, 2047
; RV64ZBA-NEXT: addi a2, a2, 2 ; RV64ZBA-NEXT: addi a2, a2, 2
; RV64ZBA-NEXT: sltu a0, a2, a0 ; RV64ZBA-NEXT: sltu a0, a2, a0
; RV64ZBA-NEXT: sd a2, 0(a1) ; RV64ZBA-NEXT: sd a2, 0(a1)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
; ;
; RV32ZICOND-LABEL: uaddo.i64.constant_2049: ; RV32ZICOND-LABEL: uaddo.i64.constant_2049:
; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND: # %bb.0: # %entry
; RV32ZICOND-NEXT: addi a3, a0, 2047 ; RV32ZICOND-NEXT: addi a3, a0, 2047
; RV32ZICOND-NEXT: addi a3, a3, 2 ; RV32ZICOND-NEXT: addi a3, a3, 2
; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: sltu a0, a3, a0
; RV32ZICOND-NEXT: add a4, a1, a0 ; RV32ZICOND-NEXT: add a4, a1, a0
; RV32ZICOND-NEXT: sltu a1, a4, a1 ; RV32ZICOND-NEXT: sltu a1, a4, a1
; RV32ZICOND-NEXT: and a0, a0, a1 ; RV32ZICOND-NEXT: and a0, a1, a0
; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a3, 0(a2)
; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2)
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: uaddo.i64.constant_2049: ; RV64ZICOND-LABEL: uaddo.i64.constant_2049:
; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: addi a2, a0, 2047 ; RV64ZICOND-NEXT: addi a2, a0, 2047
; RV64ZICOND-NEXT: addi a2, a2, 2 ; RV64ZICOND-NEXT: addi a2, a2, 2
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; RV32-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV32-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a1, 0(a0) ; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a2, 4(a0) ; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: addi a0, a1, 2 ; RV32-NEXT: addi a0, a1, 2
; RV32-NEXT: sltu a3, a0, a1 ; RV32-NEXT: sltu a3, a0, a1
; RV32-NEXT: add a1, a2, a3 ; RV32-NEXT: add a1, a2, a3
; RV32-NEXT: sltu a2, a1, a2 ; RV32-NEXT: sltu a2, a1, a2
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bnez a2, .LBB69_2 ; RV32-NEXT: bnez a2, .LBB69_2
; RV32-NEXT: # %bb.1: # %IfOverflow ; RV32-NEXT: # %bb.1: # %IfOverflow
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: li a1, 0 ; RV32-NEXT: li a1, 0
; RV32-NEXT: .LBB69_2: # %IfNoOverflow ; RV32-NEXT: .LBB69_2: # %IfNoOverflow
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV64-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
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; RV32ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV32ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: lw a1, 0(a0) ; RV32ZBA-NEXT: lw a1, 0(a0)
; RV32ZBA-NEXT: lw a2, 4(a0) ; RV32ZBA-NEXT: lw a2, 4(a0)
; RV32ZBA-NEXT: addi a0, a1, 2 ; RV32ZBA-NEXT: addi a0, a1, 2
; RV32ZBA-NEXT: sltu a3, a0, a1 ; RV32ZBA-NEXT: sltu a3, a0, a1
; RV32ZBA-NEXT: add a1, a2, a3 ; RV32ZBA-NEXT: add a1, a2, a3
; RV32ZBA-NEXT: sltu a2, a1, a2 ; RV32ZBA-NEXT: sltu a2, a1, a2
; RV32ZBA-NEXT: and a2, a3, a2 ; RV32ZBA-NEXT: and a2, a2, a3
; RV32ZBA-NEXT: bnez a2, .LBB69_2 ; RV32ZBA-NEXT: bnez a2, .LBB69_2
; RV32ZBA-NEXT: # %bb.1: # %IfOverflow ; RV32ZBA-NEXT: # %bb.1: # %IfOverflow
; RV32ZBA-NEXT: li a0, 0 ; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: li a1, 0 ; RV32ZBA-NEXT: li a1, 0
; RV32ZBA-NEXT: .LBB69_2: # %IfNoOverflow ; RV32ZBA-NEXT: .LBB69_2: # %IfNoOverflow
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV64ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
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; RV32ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV32ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND: # %bb.0: # %entry
; RV32ZICOND-NEXT: lw a1, 0(a0) ; RV32ZICOND-NEXT: lw a1, 0(a0)
; RV32ZICOND-NEXT: lw a2, 4(a0) ; RV32ZICOND-NEXT: lw a2, 4(a0)
; RV32ZICOND-NEXT: addi a0, a1, 2 ; RV32ZICOND-NEXT: addi a0, a1, 2
; RV32ZICOND-NEXT: sltu a3, a0, a1 ; RV32ZICOND-NEXT: sltu a3, a0, a1
; RV32ZICOND-NEXT: add a1, a2, a3 ; RV32ZICOND-NEXT: add a1, a2, a3
; RV32ZICOND-NEXT: sltu a2, a1, a2 ; RV32ZICOND-NEXT: sltu a2, a1, a2
; RV32ZICOND-NEXT: and a2, a3, a2 ; RV32ZICOND-NEXT: and a2, a2, a3
; RV32ZICOND-NEXT: bnez a2, .LBB69_2 ; RV32ZICOND-NEXT: bnez a2, .LBB69_2
; RV32ZICOND-NEXT: # %bb.1: # %IfOverflow ; RV32ZICOND-NEXT: # %bb.1: # %IfOverflow
; RV32ZICOND-NEXT: li a0, 0 ; RV32ZICOND-NEXT: li a0, 0
; RV32ZICOND-NEXT: li a1, 0 ; RV32ZICOND-NEXT: li a1, 0
; RV32ZICOND-NEXT: .LBB69_2: # %IfNoOverflow ; RV32ZICOND-NEXT: .LBB69_2: # %IfNoOverflow
; RV32ZICOND-NEXT: ret ; RV32ZICOND-NEXT: ret
; ;
; RV64ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: ; RV64ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
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