[RISCV] Add Zce extension.

[craig.topper]

Summary

According to the spec, Zce is an alias for Zca, Zcb, Zcmp, and Zcmt.
If F is enabled on RV32 it also includes Zcf.

This patch adds the Zce and the implication rule which unfortunately
requires custom handling for adding Zcf.

I've also made all the Zc* extensions imply Zca.

I've also added an error for Zcf without RV32.

[asb]

Looking at the PDF, the behaviour I feel is slightly unclear is for RV64 with F and with Zce. You've chosing in this patch to allow it but to just not include zcf, though by my first reading of the spec I probably would have errored on the basis that "Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf" and Zcf on RV64 is of course illegal. I think we have some leeway in how we handle this, but do you happen to know if GCC does something similar?

[craig.topper]

In D153742#4449614, @asb wrote:

Looking at the PDF, the behaviour I feel is slightly unclear is for RV64 with F and with Zce. You've chosing in this patch to allow it but to just not include zcf, though by my first reading of the spec I probably would have errored on the basis that "Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf" and Zcf on RV64 is of course illegal. I think we have some leeway in how we handle this, but do you happen to know if GCC does something similar?

I don't know what gcc does. I tried godbolt with "compile to binary" enabled. binutils rejected all of the Zc* extensions.

@Nelson1225 can you provide any information about what binutils does or will do?

[jrtc27]

What does that mean for .option arch, +zce, +f with -march=rv32i? Should that result in Zcf being present or not? My guess is binutils's dodgy implementation (which only considers implications at the end, so .option arch, foo, bar is not just shorthand for .option arch, foo; .option arch, bar as it should be in a sane world) says yes but we say no.

[craig.topper]

In D153742#4449703, @jrtc27 wrote:

What does that mean for .option arch, +zce, +f with -march=rv32i? Should that result in Zcf being present or not? My guess is binutils's dodgy implementation (which only considers implications at the end, so .option arch, foo, bar is not just shorthand for .option arch, foo; .option arch, bar as it should be in a sane world) says yes but we say no.

The easiest fix for that is probably to factor Zce directly into the tablegen predicates?

[craig.topper]

Add Zce to the Zcf instruction predicate.

I'm going to pre-commit the splitting compress-float.ll and will rebase.

[craig.topper]

Rebase on D153826

[craig.topper]

In D153742#4449694, @craig.topper wrote:

In D153742#4449614, @asb wrote:

Looking at the PDF, the behaviour I feel is slightly unclear is for RV64 with F and with Zce. You've chosing in this patch to allow it but to just not include zcf, though by my first reading of the spec I probably would have errored on the basis that "Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf" and Zcf on RV64 is of course illegal. I think we have some leeway in how we handle this, but do you happen to know if GCC does something similar?

I don't know what gcc does. I tried godbolt with "compile to binary" enabled. binutils rejected all of the Zc* extensions.

@Nelson1225 can you provide any information about what binutils does or will do?

I filed https://github.com/riscv/riscv-code-size-reduction/issues/221 to get this clarified.

[craig.topper]

Ping. I think the spec has been updated now, but the pdf has not been generated.

[asb]

This LGTM. The remaining weirdness is that zcf doesn't imply F and zcd doesn't imply D. But what is implemented here matches the current spec, and can be updated again if https://github.com/riscv/riscv-code-size-reduction/pull/224 is approved.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zbkb", RISCVExtensionVersion{1, 0}},
     {"zbkc", RISCVExtensionVersion{1, 0}},
     {"zbkx", RISCVExtensionVersion{1, 0}},
     {"zbs", RISCVExtensionVersion{1, 0}},
 
     {"zca", RISCVExtensionVersion{1, 0}},
     {"zcb", RISCVExtensionVersion{1, 0}},
     {"zcd", RISCVExtensionVersion{1, 0}},
+    {"zce", RISCVExtensionVersion{1, 0}},
     {"zcf", RISCVExtensionVersion{1, 0}},
     {"zcmp", RISCVExtensionVersion{1, 0}},
     {"zcmt", RISCVExtensionVersion{1, 0}},
 
     {"zdinx", RISCVExtensionVersion{1, 0}},
 
     {"zfh", RISCVExtensionVersion{1, 0}},
     {"zfhmin", RISCVExtensionVersion{1, 0}},
Error RISCVISAInfo::checkDependency() {
   if ((HasZcmt || Exts.count("zcmp")) && Exts.count("d") &&
       (HasC || Exts.count("zcd")))
     return createStringError(
         errc::invalid_argument,
         Twine("'") + (HasZcmt ? "zcmt" : "zcmp") +
         "' extension is incompatible with '" + (HasC ? "c" : "zcd") +
         "' extension when 'd' extension is enabled");
 
+  if (XLen != 32 && Exts.count("zcf"))
+    return createStringError(errc::invalid_argument,
+                             "'zcf' is only supported for 'rv32'");
+
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   return Error::success();
 }
 
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
 static const char *ImpliedExtsZacas[] = {"a"};
 static const char *ImpliedExtsZcb[] = {"zca"};
+static const char *ImpliedExtsZcd[] = {"zca"};
+static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
+static const char *ImpliedExtsZcf[] = {"zca"};
 static const char *ImpliedExtsZcmp[] = {"zca"};
 static const char *ImpliedExtsZcmt[] = {"zca"};
 static const char *ImpliedExtsZdinx[] = {"zfinx"};
 static const char *ImpliedExtsZfa[] = {"f"};
 static const char *ImpliedExtsZfbfmin[] = {"f"};
 static const char *ImpliedExtsZfh[] = {"f"};
 static const char *ImpliedExtsZfhmin[] = {"f"};
 static const char *ImpliedExtsZfinx[] = {"zicsr"};

 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"d"}, {ImpliedExtsD}},
     {{"f"}, {ImpliedExtsF}},
     {{"v"}, {ImpliedExtsV}},
     {{"xsfvcp"}, {ImpliedExtsXsfvcp}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
     {{"zacas"}, {ImpliedExtsZacas}},
     {{"zcb"}, {ImpliedExtsZcb}},
+    {{"zcd"}, {ImpliedExtsZcd}},
+    {{"zce"}, {ImpliedExtsZce}},
+    {{"zcf"}, {ImpliedExtsZcf}},
     {{"zcmp"}, {ImpliedExtsZcmp}},
     {{"zcmt"}, {ImpliedExtsZcmt}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfa"}, {ImpliedExtsZfa}},
     {{"zfbfmin"}, {ImpliedExtsZfbfmin}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zfinx"}, {ImpliedExtsZfinx}},
if (I != std::end(ImpliedExts) && I->Name == ExtName) {
         if (Exts.count(ImpliedExt))
           continue;
         auto Version = findDefaultVersion(ImpliedExt);
         addExtension(ImpliedExt, Version->Major, Version->Minor);
         WorkList.insert(ImpliedExt);
       }
     }
   }
+
+  // Add Zcf if Zce and F are enabled on RV32.
+  if (XLen == 32 && Exts.count("zce") && Exts.count("f") &&
+      !Exts.count("zcf")) {
+    auto Version = findDefaultVersion("zcf");
+    addExtension("zcf", Version->Major, Version->Minor);
+  }
 }
 
 struct CombinedExtsEntry {
   StringLiteral CombineExt;
   ArrayRef<const char *> RequiredExts;
 };
 
 static constexpr CombinedExtsEntry CombineIntoExts[] = {

llvm/lib/Target/RISCV/RISCVFeatures.td

: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
                                    "'C' (Compressed Instructions) or "
                                    "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcf
     : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
                        "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
                        [FeatureStdExtZca]>;
 
-def HasStdExtCOrZcf
-    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
-                AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf),
-                                   "'C' (Compressed Instructions) or "
-                                   "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-
 def FeatureStdExtZcmp
     : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
-                       "'Zcmp' (sequenced instuctions for code-size reduction)", 
+                       "'Zcmp' (sequenced instuctions for code-size reduction)",
                        [FeatureStdExtZca]>;
 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
                                AssemblerPredicate<(all_of FeatureStdExtZcmp, (not FeatureStdExtC)),
                                "'Zcmp' (sequenced instuctions for code-size reduction)">;
 
 def FeatureStdExtZcmt
     : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
-                       "'Zcmt' (table jump instuctions for code-size reduction)", 
-                       [FeatureStdExtZca, FeatureStdExtZicsr]>; 
+                       "'Zcmt' (table jump instuctions for code-size reduction)",
+                       [FeatureStdExtZca, FeatureStdExtZicsr]>;
 def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
                            AssemblerPredicate<(all_of FeatureStdExtZcmt),
                            "'Zcmt' (table jump instuctions for code-size reduction)">;
 
+def FeatureStdExtZce
+    : SubtargetFeature<"zce", "HasStdExtZce", "true",
+                       "'Zce' (Compressed extensions for microcontrollers)",
+                       [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+                        FeatureStdExtZcmt]>;
+
+def HasStdExtCOrZcfOrZce
+    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
+                "Subtarget->hasStdExtZce()">,
+                AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
+                                           FeatureStdExtZce),
+                                   "'C' (Compressed Instructions) or "
+                                   "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
            Sched<[WriteLDW, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
 def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFLD32, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
            Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32]  in
+    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]  in
 def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 

 
 def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
              Sched<[WriteLDW, ReadMemBase]> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
 def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFLD32, ReadMemBase]> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
 }
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,

 
 def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
              Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
 def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};
 }
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,

 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SPMem:$rs1, 0)>;
 def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SPMem:$rs1, 0)>;
 }
 
-let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SPMem:$rs1, 0)>;
 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SPMem:$rs1, 0)>;
 }
 
 let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZcd, HasStdExtD]
 
 let Predicates = [HasStdExtCOrZca] in {
 def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtCOrZca]
 
-let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZca, IsRV64]
 
 let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
 def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZcd, HasStdExtD]
 
 let Predicates = [HasStdExtCOrZca] in {
 def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtCOrZca]
 
-let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZca, IsRV64]
def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZcd, HasStdExtD]
 
 let Predicates = [HasStdExtCOrZca] in {
 def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1,  uimm8_lsb00:$imm),
                   (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtCOrZca]
 
-let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_LDSP GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZca, IsRV64]
def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZcd, HasStdExtD]
 
 let Predicates = [HasStdExtCOrZca] in {
 def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtCOrZca]
 
-let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
 def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_SDSP GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasStdExtCOrZca, IsRV64]

llvm/test/CodeGen/RISCV/compress-float.ll

 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.mixedattr
 ; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf -filetype=obj \
 ; RUN:   -disable-block-placement < %t.mixedattr \
 ; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.tgtattr
+; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
+; RUN:   -disable-block-placement < %t.tgtattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.fnattr
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
+; RUN:   -disable-block-placement < %t.fnattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.mixedattr
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
+; RUN:   -disable-block-placement < %t.mixedattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 
 ; This acts as a basic correctness check for the codegen instruction compression
 ; path, verifying that the assembled file contains compressed instructions when
 ; expected. Handling of the compressed ISA is implemented so the same
 ; transformation patterns should be used whether compressing an input .s file or
 ; compressing codegen output. This file contains basic functionality tests using
 ; instructions which also require one of the floating point extensions.
 
 define float @float_load(ptr %a) #0 {
 ; RV32IFDC-LABEL: <float_load>:
 ; RV32IFDC:         c.flw fa0, 0(a0)
 ; RV32IFDC-NEXT:    c.jr ra
   %1 = load volatile float, ptr %a
   ret float %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute      5, "rv32i2p1_f2p2_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32izca1p0"
 # CHECK: attribute      5, "rv32i2p1_zca1p0"
 
 .attribute arch, "rv32izcd1p0"
-# CHECK: attribute      5, "rv32i2p1_zcd1p0"
+# CHECK: attribute      5, "rv32i2p1_zca1p0_zcd1p0"
 
 .attribute arch, "rv32izcf1p0"
-# CHECK: attribute      5, "rv32i2p1_zcf1p0"
+# CHECK: attribute      5, "rv32i2p1_zca1p0_zcf1p0"
 
 .attribute arch, "rv32izcb1p0"
 # CHECK: attribute      5, "rv32i2p1_zca1p0_zcb1p0"
 
 .attribute arch, "rv32izcmp1p0"
 # CHECK: attribute      5, "rv32i2p1_zca1p0_zcmp1p0"
 
 .attribute arch, "rv32izcmt1p0"

llvm/test/MC/RISCV/option-arch.s

 .option arch, rv32ic
 # CHECK-INST: c.mv a0, a1
 # CHECK: # encoding:  [0x2e,0x85]
 addi a0, a1, 0
 
 # Test extension name that has digits.
 .option arch, +zve32x
 # CHECK: .option arch, +zve32x
+
+.option arch, rv32i
+.option arch, +zce, +f
+# CHECK-INST: flw fa0, 0(a0)
+# CHECK: # encoding: [0x08,0x61]
+c.flw fa0, 0(a0)

llvm/test/MC/RISCV/rv32fc-valid.s

 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-F %s
 # RUN: not llvm-mc -triple riscv32 \
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-FC %s
 # RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+zcf,+f \
-# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck -check-prefixes=CHECK-NO-RV32 %s
 
 # FIXME: error messages for rv64fc are misleading
 
 # CHECK-ASM-AND-OBJ: c.flwsp  fs0, 252(sp)
 # CHECK-ASM: encoding: [0x7e,0x74]
 # CHECK-NO-EXT-F:  error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
 # CHECK-NO-EXT-FC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}}
 # CHECK-NO-RV32:  error: instruction requires the following: RV32I Base Instruction Set{{$}}

llvm/unittests/Support/RISCVISAInfoTest.cpp

EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "extension is enabled");
   }
 
   for (StringRef Input : {"rv32id_zcd1p0_zcmt1p0", "rv64id_zcd1p0_zcmt1p0"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "'zcmt' extension is incompatible with 'zcd' extension when 'd' "
               "extension is enabled");
   }
+
+  for (StringRef Input : {"rv64if_zcf"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'zcf' is only supported for 'rv32'");
+  }
 }
 
 TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) {
   auto MaybeISAInfo1 =
       RISCVISAInfo::parseArchString("rv64im_zihintntl", true, false);
   ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
   EXPECT_THAT((*MaybeISAInfo1)->toFeatureVector(),
               ElementsAre("+m", "+experimental-zihintntl"));
TEST(OrderedExtensionMap, ExtensionsAreCorrectlyOrdered) {
   for (const auto &Ext : Exts)
     ExtNames.push_back(Ext.first);
 
   // FIXME: 'l' and 'y' should be ordered after 'i', 'm', 'c'.
   EXPECT_THAT(ExtNames,
               ElementsAre("i", "m", "l", "c", "y", "zicsr", "zmfoo", "zfinx",
                            "zzfoo", "sbar", "sfoo", "xbar", "xfoo"));
 }
+
+TEST(ParseArchString, ZceImplication) {
+  auto MaybeRV32IZce = RISCVISAInfo::parseArchString("rv32izce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
+      (*MaybeRV32IZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zcmt"), 1U);
+
+  auto MaybeRV32IFZce = RISCVISAInfo::parseArchString("rv32ifzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IFZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IFZce =
+      (*MaybeRV32IFZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IFZce.size(), 9UL);
+  EXPECT_EQ(ExtsRV32IFZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcf"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IFZce.count("zcmt"), 1U);
+
+  auto MaybeRV32IDZce = RISCVISAInfo::parseArchString("rv32idzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IDZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV32IDZce =
+      (*MaybeRV32IDZce)->getExtensions();
+  EXPECT_EQ(ExtsRV32IDZce.size(), 10UL);
+  EXPECT_EQ(ExtsRV32IDZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("d"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcf"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV32IDZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IZce = RISCVISAInfo::parseArchString("rv64izce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
+      (*MaybeRV64IZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IFZce = RISCVISAInfo::parseArchString("rv64ifzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IFZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IFZce =
+      (*MaybeRV64IFZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IFZce.size(), 8UL);
+  EXPECT_EQ(ExtsRV64IFZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
+
+  EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
+
+  auto MaybeRV64IDZce = RISCVISAInfo::parseArchString("rv64idzce", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IDZce, Succeeded());
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64IDZce =
+      (*MaybeRV64IDZce)->getExtensions();
+  EXPECT_EQ(ExtsRV64IDZce.size(), 9UL);
+  EXPECT_EQ(ExtsRV64IDZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("d"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcb"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zce"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
+  EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
+}