[RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines.

[craig.topper]

Summary

Make Zcf/Zcd depend on Zca.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVFeatures.td

: SubtargetFeature<"zcb", "HasStdExtZcb", "true",
                        "'Zcb' (Compressed basic bit manipulation instructions)",
                        [FeatureStdExtZca]>;
 def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
                              AssemblerPredicate<(all_of FeatureStdExtZcb),
                              "'Zcb' (Compressed basic bit manipulation instructions)">;
 
 def FeatureStdExtZcd
     : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
-                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
+                       [FeatureStdExtZca]>;
 
 def HasStdExtCOrZcd
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
                                    "'C' (Compressed Instructions) or "
                                    "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcf
     : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
-                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
+                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
+                       [FeatureStdExtZca]>;
 
 def HasStdExtCOrZcf
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf),
                                    "'C' (Compressed Instructions) or "
                                    "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcmp

llvm/test/CodeGen/RISCV/attributes.ll

 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
 ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
-; RV32ZCD: .attribute 5, "rv32i2p1_zcd1p0"
-; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
+; RV32ZCD: .attribute 5, "rv32i2p1_zca1p0_zcd1p0"
+; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0"
 ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
 ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
 ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
 ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"

 ; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0"
 ; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0"
 ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0"
 ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
-; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
+; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0"
 ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
 ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
 ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
 ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"

llvm/test/CodeGen/RISCV/compress-double.ll

 ; This test is designed to run three times, once with function attributes, once
 ; with all target attributes added on the command line, and once with compress
 ; added with the command line and float added via function attributes, all
 ; three of these should result in the same output.
 ;
 ; RUN: cat %s > %t.tgtattr
 ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd,+d -filetype=obj \
 ; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcd,+d" }' >> %t.fnattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \
 ; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+d" }' >> %t.mixedattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd -filetype=obj \
 ; RUN:   -disable-block-placement < %t.mixedattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 
 ; This acts as a basic correctness check for the codegen instruction compression
 ; path, verifying that the assembled file contains compressed instructions when
 ; expected. Handling of the compressed ISA is implemented so the same
 ; transformation patterns should be used whether compressing an input .s file or
 ; compressing codegen output. This file contains basic functionality tests using
 ; instructions which also require one of the floating point extensions.
 
-define float @float_load(ptr %a) #0 {
-; RV32IFDC-LABEL: <float_load>:
-; RV32IFDC:         c.flw fa0, 0(a0)
-; RV32IFDC-NEXT:    c.jr ra
-  %1 = load volatile float, ptr %a
-  ret float %1
-}
-
 define double @double_load(ptr %a) #0 {
 ; RV32IFDC-LABEL: <double_load>:
 ; RV32IFDC:         c.fld fa0, 0(a0)
 ; RV32IFDC-NEXT:    c.jr ra
   %1 = load volatile double, ptr %a
   ret double %1
 }

llvm/test/CodeGen/RISCV/compress-float.ll

 ; This test is designed to run three times, once with function attributes, once
 ; with all target attributes added on the command line, and once with compress
 ; added with the command line and float added via function attributes, all
 ; three of these should result in the same output.
 ;
 ; RUN: cat %s > %t.tgtattr
 ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \
 ; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
 ; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \
 ; RUN:   -disable-block-placement < %t.mixedattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.tgtattr
+; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \
+; RUN:   -disable-block-placement < %t.tgtattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.fnattr
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcf,+f" }' >> %t.fnattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
+; RUN:   -disable-block-placement < %t.fnattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %s
+;
+; RUN: cat %s > %t.mixedattr
+; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf -filetype=obj \
+; RUN:   -disable-block-placement < %t.mixedattr \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 
 ; This acts as a basic correctness check for the codegen instruction compression
 ; path, verifying that the assembled file contains compressed instructions when
 ; expected. Handling of the compressed ISA is implemented so the same
 ; transformation patterns should be used whether compressing an input .s file or
 ; compressing codegen output. This file contains basic functionality tests using
 ; instructions which also require one of the floating point extensions.
 
 define float @float_load(ptr %a) #0 {
 ; RV32IFDC-LABEL: <float_load>:
 ; RV32IFDC:         c.flw fa0, 0(a0)
 ; RV32IFDC-NEXT:    c.jr ra
   %1 = load volatile float, ptr %a
   ret float %1
 }
-
-define double @double_load(ptr %a) #0 {
-; RV32IFDC-LABEL: <double_load>:
-; RV32IFDC:         c.fld fa0, 0(a0)
-; RV32IFDC-NEXT:    c.jr ra
-  %1 = load volatile double, ptr %a
-  ret double %1
-}