[RISCV] Remove experimental for zihintntl

[jacquesguan]

Summary

Since zihintntl is ratified now, we could remove the experimental prefix and change its version to 1.0.

[asb]

Thanks for the patch.

Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating the mistake we made with the V extension where we exposed intrinsics that weren't yet finalised.

[jacquesguan]

In D151547#4375613, @asb wrote:

Thanks for the patch.

Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating the mistake we made with the V extension where we exposed intrinsics that weren't yet finalised.

I don't find any information about these two intrinsics, where do they be proposed?

[asb]

@jacquesguan I'm not sure on the standardisation process or status for these intrinsics. Perhaps @kito-cheng has an idea?

[jacquesguan]

ping.

[BeMg]

llvm/docs/RISCVUsage.rst

207–208

zihintntl could add into table:: Ratified Extensions by Status, and be removed this from the Experimental Extensions section.

[BeMg]

clang/test/Preprocessor/riscv-target-features.c

150–152

The CHECK-ZIHINTNTL-EXT also need update.

[jacquesguan]

Address comment and rebase.

[jacquesguan]

clang/test/Preprocessor/riscv-target-features.c

150–152

Done, thanks.

llvm/docs/RISCVUsage.rst

207–208

Done, thanks.

[BeMg]

llvm/unittests/Support/RISCVISAInfoTest.cpp

376 ↗

(On Diff #541904)

These unit tests are used to test the experimental extension name parsing, it is not suitable to use zihintntl here because zihintntl is no longer experimental.

I update it by https://reviews.llvm.org/D155673. After rebasing, I think the test fail in RISCVISAInfoTest.cpp can be resolved.

[asb]

I remain concerned about exposing the intrinsics if they're not yet agreed as finalised. I see there is now a PR to add them to riscv-c-api doc https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47

I'd be OK with merging this now if the intrinsics were temporarily removed, or logic were added to gate them in some way (though we don't have precedent on the best way to do this I don't think). Otherwise, I'd rather wait until the intrinsics are agreed.

[jacquesguan]

rebase main and address comment.

[jacquesguan]

In D151547#4514424, @asb wrote:

I remain concerned about exposing the intrinsics if they're not yet agreed as finalised. I see there is now a PR to add them to riscv-c-api doc https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47

I'd be OK with merging this now if the intrinsics were temporarily removed, or logic were added to gate them in some way (though we don't have precedent on the best way to do this I don't think). Otherwise, I'd rather wait until the intrinsics are agreed.

I saw that https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is basically agreed and close to merge, I think we could wait it to avoid repeat patch.

[BeMg]

LGTM

[asb]

@jacquesguan yes I agree, let's hold off on merging this until that PR is merged as it looks like it's quite close.

[jacquesguan]

https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, any more advice about this patch?

[asb]

In D151547#4531062, @jacquesguan wrote:

https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, any more advice about this patch?

Just that it needs a release note, and we need the newly defined overloaded form of the intrinsics to be supported.

[asb]

@jacquesguan: I think this is good to go if you rebase now D156221 landed and add a release note.

[jacquesguan]

rebase and add release note.

[asb]

LGTM - just see the very minor corrections inline. Thanks!

clang/test/Preprocessor/riscv-target-features.c

146

Drop -menable-experimental-extensions

149

Drop Drop -menable-experimental-extensions`

llvm/docs/RISCVUsage.rst

123

zihintntl -> Zihintntl

[jacquesguan]

Address comment.

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_sm4ed, "UiUiUiIUi", "nc", "zksed")
 TARGET_BUILTIN(__builtin_riscv_sm4ks, "UiUiUiIUi", "nc", "zksed")
 
 // Zksh extension
 TARGET_BUILTIN(__builtin_riscv_sm3p0, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 
 // Zihintntl extension
-TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "experimental-zihintntl")
-TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "experimental-zihintntl")
+TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
+TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c

 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \
+// RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +zihintntl -emit-llvm %s -o - \
 // RUN:     | FileCheck %s
 
 #include <riscv_ntlh.h>
 #include <riscv_vector.h>
 
 signed char sc;
 unsigned char uc;
 signed short ss;

clang/test/Preprocessor/riscv-target-features.c

 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // CHECK-C-EXT: __riscv_c 2000000{{$}}
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
+// RUN: -march=rv32izihintntl1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64izihintntl0p2 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
-// CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
+// RUN: -march=rv64izihintntl1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
+// CHECK-ZIHINTNTL: __riscv_zihintntl 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izba1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu \

llvm/docs/RISCVUsage.rst

.. table:: Ratified Extensions by Status
      ``Zhinx``        Supported
      ``Zhinxmin``     Supported
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
      ``Zicntr``       (`See Note <#riscv-i2p1-note>`__)
      ``Zicsr``        (`See Note <#riscv-i2p1-note>`__)
      ``Zifencei``     (`See Note <#riscv-i2p1-note>`__)
+     ``zihintntl``    Supported
      ``Zihintpause``  Assembly Support
      ``Zihpm``        (`See Note <#riscv-i2p1-note>`__)
      ``Zkn``          Supported
      ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zkne``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zknh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zksed``        Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zksh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)

 ``experimental-zfa``
   LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`__.
 
 ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
   LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
 
 ``experimental-zicond``
   LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
 
-``experimental-zihintntl``
-  LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`__.
-
 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25).  The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document.  There are multiple possible mappings, and they are *not* mutually ABI compatible.  The mapping LLVM implements is ABI compatible with the default WMO mapping.  This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status.  User beware.
 
 ``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
   LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
 
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 
 Vendor Extensions

llvm/docs/ReleaseNotes.rst

 ---------------------------
 
 Changes to the PowerPC Backend
 ------------------------------
 
 Changes to the RISC-V Backend
 -----------------------------
 
+* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.
+
 Changes to the WebAssembly Backend
 ----------------------------------
 
 Changes to the Windows Target
 -----------------------------
 
 Changes to the X86 Backend
 --------------------------

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zhinxmin", RISCVExtensionVersion{1, 0}},
 
     {"zicbom", RISCVExtensionVersion{1, 0}},
     {"zicbop", RISCVExtensionVersion{1, 0}},
     {"zicboz", RISCVExtensionVersion{1, 0}},
     {"zicntr", RISCVExtensionVersion{1, 0}},
     {"zicsr", RISCVExtensionVersion{2, 0}},
     {"zifencei", RISCVExtensionVersion{2, 0}},
+    {"zihintntl", RISCVExtensionVersion{1, 0}},
     {"zihintpause", RISCVExtensionVersion{2, 0}},
     {"zihpm", RISCVExtensionVersion{1, 0}},
 
     {"zk", RISCVExtensionVersion{1, 0}},
     {"zkn", RISCVExtensionVersion{1, 0}},
     {"zknd", RISCVExtensionVersion{1, 0}},
     {"zkne", RISCVExtensionVersion{1, 0}},
     {"zknh", RISCVExtensionVersion{1, 0}},
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 
     {"zacas", RISCVExtensionVersion{1, 0}},
 
     {"zfa", RISCVExtensionVersion{0, 2}},
     {"zfbfmin", RISCVExtensionVersion{0, 8}},
 
     {"zicond", RISCVExtensionVersion{1, 0}},
 
-    {"zihintntl", RISCVExtensionVersion{0, 2}},
-
     {"ztso", RISCVExtensionVersion{0, 1}},
 
     {"zvbb", RISCVExtensionVersion{1, 0}},
     {"zvbc", RISCVExtensionVersion{1, 0}},
 
     {"zvfbfmin", RISCVExtensionVersion{0, 8}},
     {"zvfbfwma", RISCVExtensionVersion{0, 8}},
 

llvm/lib/Target/RISCV/RISCVFeatures.td

 def FeatureStdExtZihintpause
     : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
                        "'Zihintpause' (Pause Hint)">;
 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
                                      AssemblerPredicate<(all_of FeatureStdExtZihintpause),
                                      "'Zihintpause' (Pause Hint)">;
 
 def FeatureStdExtZihintntl
-    : SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
+    : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
                        "'Zihintntl' (Non-Temporal Locality Hints)">;
 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
                                     AssemblerPredicate<(all_of FeatureStdExtZihintntl),
                                     "'Zihintntl' (Non-Temporal Locality Hints)">;
 
 def FeatureStdExtZifencei
     : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
                        "'Zifencei' (fence.i)">;

llvm/test/CodeGen/RISCV/attributes.ll

 ;; Generate ELF attributes from llc.
 
 ; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV32M %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHINTPAUSE %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHINTNTL %s
+; RUN: llc -mtriple=riscv32 -mattr=+zihintntl %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefixes=CHECK,RV32ZBA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZBB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefixes=CHECK,RV32ZBC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefixes=CHECK,RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - | FileCheck --check-prefixes=CHECK,RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+h %s -o - | FileCheck --check-prefixes=CHECK,RV32H %s

 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHINTPAUSE %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHINTNTL %s
+; RUN: llc -mtriple=riscv64 -mattr=+zihintntl %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefixes=CHECK,RV64ZBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - | FileCheck --check-prefixes=CHECK,RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+h %s -o - | FileCheck --check-prefixes=CHECK,RV64H %s

 ; RV32M: .attribute 5, "rv32i2p1_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p1_a2p1"
 ; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
 ; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
 ; RV32C: .attribute 5, "rv32i2p1_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p1_zihintpause2p0"
-; RV32ZIHINTNTL: .attribute 5, "rv32i2p1_zihintntl0p2"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p1_zihintntl1p0"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p1_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p1_zbb1p0"
 ; RV32ZBC: .attribute 5, "rv32i2p1_zbc1p0"
 ; RV32ZBS: .attribute 5, "rv32i2p1_zbs1p0"
 ; RV32V: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32H: .attribute 5, "rv32i2p1_h1p0"

 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
 ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p1_a2p1"
 ; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
 ; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
 ; RV64C: .attribute 5, "rv64i2p1_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p1_zihintpause2p0"
-; RV64ZIHINTNTL: .attribute 5, "rv64i2p1_zihintntl0p2"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p1_zihintntl1p0"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p1_zba1p0"
 ; RV64ZBB: .attribute 5, "rv64i2p1_zbb1p0"
 ; RV64ZBC: .attribute 5, "rv64i2p1_zbc1p0"
 ; RV64ZBS: .attribute 5, "rv64i2p1_zbs1p0"
 ; RV64V: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64H: .attribute 5, "rv64i2p1_h1p0"

llvm/test/CodeGen/RISCV/nontemporal-scalable.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
+; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
+; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
 
 define <vscale x 2 x i64> @test_nontemporal_load_nxv2i64(ptr %p) {
 ; CHECK-RV64V-LABEL: test_nontemporal_load_nxv2i64:
 ; CHECK-RV64V:       # %bb.0:
 ; CHECK-RV64V-NEXT:    ntl.all
 ; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
 ; CHECK-RV64V-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/nontemporal.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV64C
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV32C
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
+; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV64C
+; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV32C
+; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
+; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
 
 define i64 @test_nontemporal_load_i64(ptr %p) {
 ; CHECK-RV64-LABEL: test_nontemporal_load_i64:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    ntl.all
 ; CHECK-RV64-NEXT:    ld a0, 0(a0)
 ; CHECK-RV64-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/prefetch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=zicbop -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+experimental-zihintntl -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64ZICBOPZIHINTNTL %s
 
 declare void @llvm.prefetch(ptr, i32, i32, i32)
 
 define void @test_prefetch_read_locality_0(ptr %a) nounwind {
 ; RV32I-LABEL: test_prefetch_read_locality_0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 
 .attribute arch, "rv32i_zkt1p0"
 # CHECK: attribute      5, "rv32i2p1_zkt1p0"
 
 .attribute arch, "rv32i_zk1p0"
 # CHECK: attribute      5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 
-.attribute arch, "rv32izihintntl0p2"
-# CHECK: attribute      5, "rv32i2p1_zihintntl0p2"
+.attribute arch, "rv32izihintntl1p0"
+# CHECK: attribute      5, "rv32i2p1_zihintntl1p0"
 
-.attribute arch, "rv32iczihintntl0p2"
-# CHECK: attribute      5, "rv32i2p1_c2p0_zihintntl0p2"
+.attribute arch, "rv32iczihintntl1p0"
+# CHECK: attribute      5, "rv32i2p1_c2p0_zihintntl1p0"
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute      5, "rv32i2p1_f2p2_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32izca1p0"
 # CHECK: attribute      5, "rv32i2p1_zca1p0"
 
 .attribute arch, "rv32izcd1p0"

llvm/test/MC/RISCV/rv32zihintntl-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl < %s 2>&1 | FileCheck %s
 
 ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 ntl.s1 3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.all 4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 
 ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 

llvm/test/MC/RISCV/rv32zihintntl-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN:     | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \
+# RUN:     | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: add zero, zero, sp
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
 ntl.p1
 
 # CHECK-ASM-AND-OBJ: add zero, zero, gp
 # CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]

llvm/test/MC/RISCV/rv32zihintntlc-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
 c.ntl.s1 3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.all 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
 
 c.ntl.p1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall t0, t1 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
 c.ntl.s1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.all t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
 

llvm/test/MC/RISCV/rv32zihintntlc-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN:     | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN:     | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
 ntl.p1
 
 # CHECK-ASM-AND-OBJ: ntl.pall
 # CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
 ntl.pall