This implements the v1.0-rc1 draft extension.
amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must be even registers. I've opted to implement this restriction in RISCVAsmParser::validateInstruction even though for codegen we'll need a new register class and can then remove this validation. My reasoning is that this validation is easy to implement and review, while ensuring the register class is correct as described isn't so easy without testing that is only added when codegen is implemented. Admittedly, the need to check for the aq/rl/aqrl opcode variants makes the validateInstruction
logic a bit uglier. Happy to switch approach if preferred by reviewers. EDIT: it of course also sidesteps for now the issue of amocas.d being different on rv32 vs rv64.
It's not a pre-requisite for this patch, but we likely want to have an asm constraint for even registers. I've filed an issue here https://github.com/riscv-non-isa/riscv-c-api-doc/issues/37