[AArch64][InlineAsm]Add Clang support for flag output constraints

[mingmingl]

Summary

• Mention this change in Clang release notes.

Before:

• Clang emits "invalid output constraint '=@cceq' in asm" https://gcc.godbolt.org/z/b9crfEo8h

After:

• For aarch64 targets (with __aarch64__ defined), Clang validates and parses flag output constraints to generate LLVM IR.

[mingmingl]

remove 'No newline at end of file'

[mingmingl]

While testing this patch with ./bin/clang -cc1 -S -triple=aarch64 inline-asm-aarch64-flag-output.c (which invokes global-isel for instruction selection according to print-after-all output), turns out GlobalISel doesn't support flag output yet (for x86 or aarch64).

/bin/clang -cc1 -O1 -S -triple=aarch64 file.c and /bin/clang -cc1 -O2 -S -triple=aarch64 file.c works.

I filed https://github.com/llvm/llvm-project/issues/62343 to track but but think the issue is a non-blocker of this patch and D149032 for now.

[davidxl]

clang/lib/Basic/Targets/AArch64.cpp

1216

Name is not modified in this method, so perhaps dropping '&'?

[nickdesaulniers]

clang/lib/Basic/Targets/AArch64.cpp

1216

Yeah, looks like this was copied from D57394. Probably both places should be fixed.

A char *& is a code smell.

1310

please don't use auto here.

[mingmingl]

update on the crashing issue (solved)

resolve comments.

[mingmingl]

In D149123#4294619, @mingmingl wrote:

While testing this patch with ./bin/clang -cc1 -S -triple=aarch64 inline-asm-aarch64-flag-output.c (which invokes global-isel for instruction selection according to print-after-all output), turns out GlobalISel doesn't support flag output yet (for x86 or aarch64).

/bin/clang -cc1 -O1 -S -triple=aarch64 file.c and /bin/clang -cc1 -O2 -S -triple=aarch64 file.c works.

I filed https://github.com/llvm/llvm-project/issues/62343 to track but but think the issue is a non-blocker of this patch and D149032 for now.

After relaxing the assert condition in GlobalISel/InlineAsmLowering.cpp in the parent patch, the original crash (assertion error in global-isel) command generates valid asm outputs (the reason is that global-isel will fall back to selection-dag based isel when it couldn't select or lower an instruction), The error seen in issue 62343 could be worked around with the fallback approach.

Mentioned this change in clang release notes, and resolve comments.

clang/lib/Basic/Targets/AArch64.cpp

1216

thanks for the catch! will fix the x86 cpp code in a tiny separate patch later.

1310

s/auto/const unsiged, here and above.

[nickdesaulniers]

Thanks for the patch!

clang/docs/ReleaseNotes.rst

- The hard-float ABI is now available in Armv8.1-M configurations that
   no scalar or vector floating point computation. Previously, trying
   to select the hard-float ABI on such a target (via
   ``-mfloat-abi=hard`` or a triple ending in ``hf``) would silently
   use the soft-float ABI instead.
 
 - Clang builtin ``__arithmetic_fence`` and the command line option ``-fprotect-parens``
   are now enabled for AArch64.
 
+- Clang supports flag output operands by which conditions in the NZCV could be outputs
+  of inline assembly for AArch64. This change is more consistent with the behavior of
+  GCC.
+
+   .. code-block:: c
+
+     // int a = foo(); int* b = bar();
+     asm("ands %w[a], %w[a], #3" : [a] "+r"(a), "=@cceq"(*b));
+
 Windows Support
 ^^^^^^^^^^^^^^^
 
 LoongArch Support
 ^^^^^^^^^^^^^^^^^
 
 - Patchable function entry (``-fpatchable-function-entry``) is now supported
   on LoongArch.

clang/lib/Basic/Targets/AArch64.h

public:
 
   bool isCLZForZeroUndef() const override;
 
   BuiltinVaListKind getBuiltinVaListKind() const override;
 
   ArrayRef<const char *> getGCCRegNames() const override;
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
-  std::string convertConstraint(const char *&Constraint) const override {
-    std::string R;
-    switch (*Constraint) {
-    case 'U': // Three-character constraint; add "@3" hint for later parsing.
-      R = std::string("@3") + std::string(Constraint, 3);
-      Constraint += 2;
-      break;
-    default:
-      R = TargetInfo::convertConstraint(Constraint);
-      break;
-    }
-    return R;
-  }
+  std::string convertConstraint(const char *&Constraint) const override;
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
   bool
   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
                              std::string &SuggestedModifier) const override;
   std::string_view getClobbers() const override;
 

clang/lib/Basic/Targets/AArch64.cpp

void AArch64TargetInfo::getTargetDefinesARMV94A(const LangOptions &Opts,
   // Armv9.4-A maps to Armv8.9-A
   getTargetDefinesARMV89A(Opts, Builder);
 }
 
 void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
                                          MacroBuilder &Builder) const {
   // Target identification.
   Builder.defineMacro("__aarch64__");
+  // Inline assembly supports AArch64 flag outputs.
+  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
   // For bare-metal.
   if (getTriple().getOS() == llvm::Triple::UnknownOS &&
       getTriple().isOSBinFormatELF())
     Builder.defineMacro("__ELF__");
 
   // Target properties.
   if (!getTriple().isOSWindows() && getTriple().isArch64Bit()) {
     Builder.defineMacro("_LP64");
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
     // The S/D/Q and W/X registers overlap, but aren't really aliases; we
     // don't want to substitute one of these for a different-sized one.
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
   return llvm::ArrayRef(GCCRegAliases);
 }
 
+// Returns the length of cc constraint.
+static unsigned matchAsmCCConstraint(const char *Name) {
+  constexpr unsigned len = 5;
+  auto RV = llvm::StringSwitch<unsigned>(Name)
+                .Case("@cceq", len)
+                .Case("@ccne", len)
+                .Case("@cchs", len)
+                .Case("@cccs", len)
+                .Case("@cccc", len)
+                .Case("@cclo", len)
+                .Case("@ccmi", len)
+                .Case("@ccpl", len)
+                .Case("@ccvs", len)
+                .Case("@ccvc", len)
+                .Case("@cchi", len)
+                .Case("@ccls", len)
+                .Case("@ccge", len)
+                .Case("@cclt", len)
+                .Case("@ccgt", len)
+                .Case("@ccle", len)
+                .Default(0);
+  return RV;
+}
+
+std::string
+AArch64TargetInfo::convertConstraint(const char *&Constraint) const {
+  std::string R;
+  switch (*Constraint) {
+  case 'U': // Three-character constraint; add "@3" hint for later parsing.
+    R = std::string("@3") + std::string(Constraint, 3);
+    Constraint += 2;
+    break;
+  case '@':
+    if (const unsigned Len = matchAsmCCConstraint(Constraint)) {
+      std::string Converted = "{" + std::string(Constraint, Len) + "}";
+      Constraint += Len - 1;
+      return Converted;
+    }
+    return std::string(1, *Constraint);
+  default:
+    R = TargetInfo::convertConstraint(Constraint);
+    break;
+  }
+  return R;
+}
+
 bool AArch64TargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   switch (*Name) {
   default:
     return false;
   case 'w': // Floating point and SIMD registers (V0-V31)
     Info.setAllowsRegister();
     return true;
case 'z': // Zero register, wzr or xzr
     Info.setAllowsRegister();
     return true;
   case 'x': // Floating point and SIMD registers (V0-V15)
     Info.setAllowsRegister();
     return true;
   case 'y': // SVE registers (V0-V7)
     Info.setAllowsRegister();
     return true;
+  case '@':
+    // CC condition
+    if (const unsigned Len = matchAsmCCConstraint(Name)) {
+      Name += Len - 1;
+      Info.setAllowsRegister();
+      return true;
+    }
   }
   return false;
 }
 
 bool AArch64TargetInfo::validateConstraintModifier(
     StringRef Constraint, char Modifier, unsigned Size,
     std::string &SuggestedModifier) const {
   // Strip off constraint modifiers.

clang/test/CodeGen/inline-asm-aarch64-flag-output.c

+// RUN: %clang_cc1 -O2 -emit-llvm %s -o - -triple aarch64 | FileCheck %s
+
+int test_cceq(int a, int* b) {
+// CHECK-LABEL: @test_cceq
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cceq},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cceq"(*b));
+  return a;
+}
+
+int test_ccne(int a, int* b) {
+// CHECK-LABEL: @test_ccne
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccne},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccne"(*b));
+  return a;
+}
+
+int test_cccs(int a, int* b) {
+// CHECK-LABEL: @test_cccs
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cccs},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cccs"(*b));
+  return a;
+}
+
+int test_cchs(int a, int* b) {
+// CHECK-LABEL: @test_cchs
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cchs},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cchs"(*b));
+  return a;
+}
+
+int test_cccc(int a, int* b) {
+// CHECK-LABEL: @test_cccc
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cccc},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cccc"(*b));
+  return a;
+}
+
+int test_cclo(int a, int* b) {
+// CHECK-LABEL: @test_cclo
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cclo},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cclo"(*b));
+  return a;
+}
+
+int test_ccmi(int a, int* b) {
+// CHECK-LABEL: @test_ccmi
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccmi},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccmi"(*b));
+  return a;
+}
+
+int test_ccpl(int a, int* b) {
+// CHECK-LABEL: @test_ccpl
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccpl},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccpl"(*b));
+  return a;
+}
+
+int test_ccvs(int a, int* b) {
+// CHECK-LABEL: @test_ccvs
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccvs},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccvs"(*b));
+  return a;
+}
+
+int test_ccvc(int a, int* b) {
+// CHECK-LABEL: @test_ccvc
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccvc},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccvc"(*b));
+  return a;
+}
+
+int test_cchi(int a, int* b) {
+// CHECK-LABEL: @test_cchi
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cchi},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cchi"(*b));
+  return a;
+}
+
+int test_ccls(int a, int* b) {
+// CHECK-LABEL: @test_ccls
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccls},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccls"(*b));
+  return a;
+}
+
+
+int test_ccge(int a, int* b) {
+// CHECK-LABEL: @test_ccge
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccge},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccge"(*b));
+  return a;
+}
+
+int test_cclt(int a, int* b) {
+// CHECK-LABEL: @test_cclt
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cclt},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@cclt"(*b));
+  return a;
+}
+
+int test_ccgt(int a, int* b) {
+// CHECK-LABEL: @test_ccgt
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccgt},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccgt"(*b));
+  return a;
+}
+
+int test_ccle(int a, int* b) {
+// CHECK-LABEL: @test_ccle
+// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccle},0"(i32 %a)
+  asm("ands %w[a], %w[a], #3"
+      : [a] "+r"(a), "=@ccle"(*b));
+  return a;
+}

clang/test/Preprocessor/aarch64_asm_flag_output.c

+// RUN: %clang -target aarch64-unknown-unknown -x c -E -dM -o - %s | FileCheck -match-full-lines %s
+
+// CHECK: #define __GCC_ASM_FLAG_OUTPUTS__ 1

clang/test/Preprocessor/init-aarch64.c

 // AARCH64-NEXT: #define __FLT_MAX_EXP__ 128
 // AARCH64-NEXT: #define __FLT_MAX__ 3.40282347e+38F
 // AARCH64-NEXT: #define __FLT_MIN_10_EXP__ (-37)
 // AARCH64-NEXT: #define __FLT_MIN_EXP__ (-125)
 // AARCH64-NEXT: #define __FLT_MIN__ 1.17549435e-38F
 // AARCH64-NEXT: #define __FLT_RADIX__ 2
 // AARCH64-NEXT: #define __FP_FAST_FMA 1
 // AARCH64-NEXT: #define __FP_FAST_FMAF 1
+// AARCH64-NEXT: #define __GCC_ASM_FLAG_OUTPUTS__ 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
 // AARCH64_CXX-NEXT: #define __GLIBCXX_BITSIZE_INT_N_0 128
 // AARCH64_CXX-NEXT: #define __GLIBCXX_TYPE_INT_N_0 __int128
 // AARCH64-NEXT: #define __HAVE_FUNCTION_MULTI_VERSIONING 1
 // AARCH64-NEXT: #define __INT16_C_SUFFIX__

clang/test/Preprocessor/predefined-win-macros.c

 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-ARM64-MINGW
 
 // CHECK-ARM64-MINGW-NOT: #define _M_ARM64 1
 // CHECK-ARM64-MINGW: #define WIN32 1
 // CHECK-ARM64-MINGW: #define WIN64 1
 // CHECK-ARM64-MINGW: #define WINNT 1
 // CHECK-ARM64-MINGW: #define _WIN32 1
 // CHECK-ARM64-MINGW: #define _WIN64 1
+// CHECK-ARM64-MINGW: #define __GCC_ASM_FLAG_OUTPUTS__ 1
 // CHECK-ARM64-MINGW: #define __aarch64__ 1