[ARM] Emit code alignment after .arm and .thumb directives

[antangelo]

Summary

Emit a 4-byte alignment after the .arm directive and a 2-byte alignment
after the .thumb directive. The new behavior matches GNU assembler.

Fixes #53386

[antangelo]

Fix lld tests, rebase

[MaskRay]

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

94

This address adjustment will break what the test wants to check. The tests need a proper update.

@peter.smith

[antangelo]

Fixed arm-fix-cortex-a8-nopatch test cases, added back a check in -recognized that was accidentally removed

I changed the offsets around the .arm directive such that the instruction offsets are the same as before this patch.
The only exception is that the target5 label has moved slightly, but it is still in region 1, so the test case should
be valid now to my knowledge.

[peter.smith]

Tests updates look OK to me.

A couple of comments overall.

• While I personally prefer the proposed behaviour as I don't think anyone other than CPU and toolchain validation tests should want to write an unaligned instruction; this is a difference in behaviour with GNU assembler. Can we add to the Arm section of the LLVM release notes to the next release? Could also be worth a binutils bug to see if we can get GNU to follow.
• If .arm is going to be aligning to a 4-byte boundary then .thumb should be aligning to a 2-byte boundary. It doesn't look like it is at the moment. While less likely to be a problem in practice I think it is important that it gets done so that the behaviour of the directives is consistent. Could be done in a follow up patch.

[MaskRay]

In D147763#4257334, @peter.smith wrote:

A couple of comments overall.
... Can we add to the Arm section of the LLVM release notes to the next release? Could also be worth a binutils bug to see if we can get GNU to follow.

FYI It's llvm/docs/ReleaseNotes.rst Changes to the ARM Backend

[antangelo]

Rebased, updated release notes, updated .thumb to align to a 2-byte boundary, and added a test case

To my knowledge (testing with arm-none-eabi), the GNU assembler aligns code after the .arm directive to the next
4-byte boundary when switching from thumb to ARM mode. It does not seem to emit any alignment when switching
from ARM to thumb mode with .thumb.

[antangelo]

Rebased and updated the commit message to reflect the .thumb directive changes

Also noting that I don't have commit access to commit this myself after the review is completed

[antangelo]

Ping

[MaskRay]

Sorry for the delay.

llvm/docs/ReleaseNotes.rst

110

Two backsticks in reST for something mostly equivalent in Markdown

llvm/test/MC/ARM/arm-thumb-directive-alignment.s

1 ↗

(On Diff #521544)

For directive tests, the most common filenames are directive-*.

We should test section headers as well: llvm-readelf -S -s . Define a custom section and check that its alignment is affected by .arm. Then define another section and check its alignment is affected by .thumb

22 ↗

(On Diff #521544)

The name unaligned_thumb_to_arm may be confusing as the value is actually aligned. thumb_to_arm suffices.

[MaskRay]

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

94

With this change, the test will pass even if I remove --fix-cortex-a8. This means the directive semantics change nullifies the purpose of the test. I think we should repair the test properly.

[MaskRay]

lld/test/ELF/arm-fix-cortex-a8-recognize.s

168

I suspect that this may need a proper fix as well.

[antangelo]

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

94

With this change, the test will pass even if I remove --fix-cortex-a8. This means the directive semantics change nullifies the purpose of the test. I think we should repair the test properly.

I've tried this on the current main branch and this test passes with --fix-cortex-a8 removed. Is it possible the test itself is in disrepair?

[antangelo]

Rebase and addressing feedback

Updated the release notes syntax, fixed the directive-arm-thumb-alignment test file name,
and added tests for section alignment.

After studying the tests again more closely, to my understanding, the nopatch tests
are for edge cases where the fix should not be applied, so having the same result when --fix-cortex-a8
is removed seems to be correct. I also noticed a bug where the nop.w instruction that is manually
encoded in that test is encoded incorrectly, so I have updated that. If the .arm directive
under target5 is removed, the case is now detected as requiring the cortex-a8 fix (so it is now testing
the right thing).

I have verified the offsets in both the nopatch and recognize suites and they match what is currently
in main (and match the condition that triggers the fix). I don't otherwise know what to look for in
terms of what could be incorrect there. Is there anything about those tests in particular that need updating,
or something else I should verify against?

[MaskRay]

llvm/test/MC/ARM/directive-arm-thumb-alignment.s

6

Replace Off column values with {{.*}}. The offsets are not interesting for the purpose of the test and will cause unneeded trouble for changes that shuffle section order/string table optimization/etc, see https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-too-much .

Replace Size column value of .strtab with {{.*}}

65

Delete trailing blan lines

[antangelo]

Replace offset and strtab size columns with wildcard, remove trailing newline in directive test

[antangelo]

I don't have commit access to commit the changes myself, if someone can commit on my behalf. My name and email are:

Name: Antonio Abbatangelo
Email: [e-mail]

lld/test/ELF/arm-bl-v4t.s

 // FAR-EB-PIE-NEXT:   1000020:        ldr r12, [pc, #4]           @ 0x100002c <__Thumbv4PILongThunk_thumb_target+0x10>
 // FAR-EB-PIE-NEXT:                 add r12, pc, r12
 // FAR-EB-PIE-NEXT:                 bx  r12
 // FAR-EB-PIE-EMPTY:
 // FAR-EB-PIE-NEXT:  <$d>:
 // FAR-EB-PIE-NEXT:   100002c: 04 ff ff d9    .word 0x04ffffd9
 
 // NEAR-LABEL: <_start>:
-// NEAR-NEXT:  1000000:       bl  0x100000c <thumb_start+0x4> @ imm = #4
+// NEAR-NEXT:  1000000:       bl  0x1000010 <target> @ imm = #8
 // NEAR-NEXT:                 bx  lr
 // NEAR-EMPTY:
 // NEAR-LABEL: <thumb_start>:
-// NEAR-NEXT:  1000008:       bl  0x1000012 <thumb_target> @ imm = #6
+// NEAR-NEXT:  1000008:       bl  0x1000014 <thumb_target> @ imm = #8
 // NEAR-NEXT:                 bx  lr
 
 .section .high, "ax", %progbits
  .arm
  .globl target
  .type target,%function
 target:
   bx lr

 
 // FAR-PIE-LABEL: <target>:
 // FAR-PIE-NEXT:   6000000:     bx  lr
 // FAR-PIE-EMPTY:
 // FAR-PIE-LABEL: <thumb_target>:
 // FAR-PIE-NEXT:   6000004:     bx  lr
 
 // NEAR-LABEL: <target>:
-// NEAR-LABEL:  100000e:        bx  lr
+// NEAR-LABEL:  1000010:        bx  lr
 // NEAR-EMPTY:
 // NEAR-NEXT: <thumb_target>:
-// NEAR-NEXT:  1000012:       bx  lr
+// NEAR-NEXT:  1000014:       bx  lr
 
                                      
 #--- far.lds
 SECTIONS {
   . = SIZEOF_HEADERS;
   .low 0x01000000 : { *(.low) }
   .high 0x06000000 : { *(.high) }
 }
 
 #--- near.lds
 SECTIONS {
   . = SIZEOF_HEADERS;
   .all 0x01000000 : { *(.low) *(.high) }
 }

lld/test/ELF/arm-bl-v6-inrange.s

 // CHECK-EMPTY:
 // CHECK-NEXT: Disassembly of section .caller:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
 // CHECK-NEXT:   500000:       f400 f800       bl     0x100004 <thumbfunc>
 // CHECK-NEXT:   500004:       f3ff effe       blx    0x900004 <armfunc>
 // CHECK-NEXT:   500008:       4770    bx      lr
 
-  .arm
   .section .callee_high, "ax", %progbits
+  .arm
   .globl armfunc
   .type armfunc, %function
 armfunc:
   bx lr
 // CHECK: Disassembly of section .callee2:
 // CHECK-EMPTY:
 // CHECK-NEXT: <armfunc>:
 // CHECK-NEXT:   900004:       e12fff1e        bx      lr

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

  nop.w
 
 // CALLSITE4:      00024ffa <source4>:
 // CALLSITE4-NEXT:    24ffa:            nop.w
 // CALLSITE4-NEXT:    24ffe:            beq.w   0x25002 <target4>
 // CALLSITE4:      00025002 <target4>:
 // CALLSITE4-NEXT:    25002:            nop.w
 
- .space 4084
+ .space 4082
  .type target5, %function
 
 target5:
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by the encoding of
 /// a 32-bit thumb instruction, but in ARM state (illegal instruction), we
 /// should not decode and match it as Thumb, expect no patch.
  .arm
- .inst 0x800f3af /// nop.w encoding in Thumb
+ .short 0xbf00 // nop encoding in Thumb for alignment
+ .inst 0xf3af8000 /// nop.w encoding in Thumb
  .thumb
  .thumb_func
 source5:
  beq.w target5
 
 // CALLSITE5:      00025ffe <source5>:
-// CALLSITE5-NEXT:    25ffe:            beq.w   0x25ffa <target5>
+// CALLSITE5-NEXT:    25ffe:            beq.w   0x25ff8 <target5>
 
 /// Edge case where two word sequence starts at offset 0xffc, check that
 /// we don't match. In this case the branch will be completely in the 2nd
 /// region and the branch will target the second region. This will pass a
 /// branch destination in the same region test, but not the branch must have
 /// and address of the form xxxxxffe.
  .space 4090
  .type target6, %function

lld/test/ELF/arm-fix-cortex-a8-recognize.s

 // CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 27FFE in unpatched output.
 // CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 28FFE in unpatched output.
 
 /// We do not detect errors when doing a relocatable link as we don't know what
 /// the final addresses are.
 // CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence
 
 /// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the
-/// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an
+/// erratum and the patch are in ARMErrataFix.cpp . The test creates an
 /// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit
 /// branch instruction, where the branch instruction spans two 4 KiB regions,
 /// and the branch destination is in the first 4KiB region.
 ///
 /// Test each 32-bit branch b.w, bcc.w, bl, blx. For b.w, bcc.w, and bl we
 /// check the relocated and non-relocated forms. The blx instruction
 /// always has a relocation in assembler.
  .syntax unified

 /// goes via a relocation.
  nop.w
  bne.w target7
 
 // CALLSITE7:         27ffa:            nop.w
 // CALLSITE7-NEXT:    27ffe:            bne.w   0x2901c <__CortexA8657417_27FFE>
 
  .section .text.6, "ax", %progbits
- .space 4082
+ .space 4080
  .arm
  .global target8
  .type target8, %function
 target8:
  bx lr
 
  .section .text.7, "ax", %progbits
  .space 2
  .thumb
 /// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch

lld/test/ELF/arm-thunk-multipass.s

 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
 // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x100002 --stop-address=0x10000a  | FileCheck --check-prefix=CHECK1 %s
-// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000008 --stop-address=0x1000026  | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000004 --stop-address=0x1000026  | FileCheck --check-prefix=CHECK2 %s
 // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1100014 --stop-address=0x1100022  | FileCheck --check-prefix=CHECK3 %s
 // In this test case a branch that is in range and does not need its range
 // extended can be pushed out of range by another Thunk, necessitating another
 // pass
 
  .macro FUNCTION suff
  .section .text.\suff\(), "ax", %progbits
  .thumb

  FUNCTION 15
 
  .section .text.16, "ax", %progbits
  .arm
  .globl arm_target
  .type arm_target, %function
 arm_target:
  bx lr
+// CHECK2: 01000004 <arm_target>:
 // CHECK2: <__Thumbv7ABSLongThunk_arm_target>:
-// CHECK2-NEXT:  1000008:       f240 0c02       movw    r12, #2
+// CHECK2-NEXT:  1000008:       f240 0c04       movw    r12, #4
 // CHECK2-NEXT:  100000c:       f2c0 1c00       movt    r12, #256
 // CHECK2-NEXT:  1000010:       4760    bx      r12
 // CHECK2: <__Thumbv7ABSLongThunk_target>:
 // CHECK2-NEXT:  1000012:       f0ff bfff       b.w     0x1100014 <target>
 // CHECK2: <__Thumbv7ABSLongThunk_target2>:
 // CHECK2-NEXT:  1000016:       f4ff 97fc       b.w     0x100012 <target2>
 
  .section .text.17, "ax", %progbits

llvm/docs/ReleaseNotes.rst

 
 Changes to the ARM Backend
 --------------------------
 
 - The hard-float ABI is now available in Armv8.1-M configurations that
   have integer MVE instructions (and therefore have FP registers) but
   no scalar or vector floating point computation.
 
+- The ``.arm`` directive now aligns code to the next 4-byte boundary, and
+  the ``.thumb`` directive aligns code to the next 2-byte boundary.
+
 Changes to the AVR Backend
 --------------------------
 
 * ...
 
 Changes to the DirectX Backend
 ------------------------------
 

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
   if (parseEOL() || check(!hasThumb(), L, "target does not support Thumb mode"))
     return true;
 
   if (!isThumb())
     SwitchMode();
 
   getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
+  getParser().getStreamer().emitCodeAlignment(Align(2), &getSTI(), 0);
   return false;
 }
 
 /// parseDirectiveARM
 ///  ::= .arm
 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
   if (parseEOL() || check(!hasARM(), L, "target does not support ARM mode"))
     return true;
 
   if (isThumb())
     SwitchMode();
   getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
+  getParser().getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0);
   return false;
 }
 
 void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) {
   // We need to flush the current implicit IT block on a label, because it is
   // not legal to branch into an IT block.
   flushPendingInstructions(getStreamer());
 }

llvm/test/MC/ARM/directive-arch-mode-switch.s

 @ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
 @ CHECK-NOT: .code
 @ CHECK: .cpu cortex-a8
 @ CHECK-NOT: .code
 
 @ Switch to ARM mode
   .arm
 @ CHECK: .code 32
+@ CHECK: .p2align 2
 
 @ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode)
   .cpu cortex-a8
 @ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
 @ CHECK-NOT: .code
 @ CHECK: .cpu cortex-a8
 @ CHECK-NOT: .code
 
 @ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive
   .cpu cortex-m3
 @ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode
 @ CHECK: .cpu    cortex-m3
 @ CHECK: .code   16
 
 @ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case

llvm/test/MC/ARM/directive-arm-thumb-alignment.s

+@ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s | llvm-readelf -S -s - | FileCheck %s
+
+@ CHECK:   [Nr] Name              Type            Address  Off    Size   ES Flg Lk Inf Al
+@ CHECK-NEXT:   [ 0]                   NULL            00000000 000000 000000 00      0   0  0
+@ CHECK-NEXT:   [ 1] .strtab           STRTAB          00000000 {{.*}} {{.*}} 00      0   0  1
+@ CHECK-NEXT:   [ 2] .text             PROGBITS        00000000 {{.*}} 00000d 00  AX  0   0  4
+@ CHECK-NEXT:   [ 3] .arm_aligned      PROGBITS        00000000 {{.*}} 000005 00  AX  0   0  4
+@ CHECK-NEXT:   [ 4] .thumb_aligned    PROGBITS        00000000 {{.*}} 000002 00  AX  0   0  2
+
+@ CHECK:      Num:    Value  Size Type    Bind   Vis      Ndx Name
+@ CHECK-NEXT:   0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND
+@ CHECK-NEXT:   1: 00000001     0 FUNC    LOCAL  DEFAULT    2 aligned_thumb
+@ CHECK-NEXT:   2: 00000000     0 NOTYPE  LOCAL  DEFAULT    2 $t.0
+@ CHECK-NEXT:   3: 00000004     0 FUNC    LOCAL  DEFAULT    2 thumb_to_arm
+@ CHECK-NEXT:   4: 00000004     0 NOTYPE  LOCAL  DEFAULT    2 $a.1
+@ CHECK-NEXT:   5: 00000008     0 NOTYPE  LOCAL  DEFAULT    2 $d.2
+@ CHECK-NEXT:   6: 0000000b     0 FUNC    LOCAL  DEFAULT    2 unaligned_arm_to_thumb
+@ CHECK-NEXT:   7: 0000000a     0 NOTYPE  LOCAL  DEFAULT    2 $t.3
+
+.thumb
+
+.type aligned_thumb,%function
+aligned_thumb:
+    nop
+
+@ Above function has size 2 (at offset 0)
+@ Expect alignment of +2 (to offset 4)
+.arm
+
+.type thumb_to_arm,%function
+thumb_to_arm:
+    nop
+
+.byte 0
+
+@ Above function has size 5 (at offset 4)
+@ Expect alignment of +1 (to offset 10)
+.thumb
+.type unaligned_arm_to_thumb,%function
+unaligned_arm_to_thumb:
+    nop
+
+.byte 0
+
+@ Above section has size 13 (at offset 34)
+@ Expect alignment of +3 (to offset 44)
+.section .arm_aligned, "ax"
+.arm
+
+.type arm_aligned_section,%function
+arm_aligned_section:
+    nop
+
+.byte 0
+
+@ Above section has size 5 (at offset 44)
+@ Expect alignment of +1 (to offset 4a)
+.section .thumb_aligned, "ax"
+.thumb
+
+.type thumb_aligned_section,%function
+thumb_aligned_section:
+    nop

llvm/test/MC/ARM/misaligned-blx.s

 @ RUN: not llvm-mc -triple thumbv7-apple-ios -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s
         @ Size: 2 bytes
         .thumb_func _f1
         .thumb
         .globl _f1
 _f1:
         bx lr
 
         @ A misaligned ARM destination.
         .arm
+        .byte 0x0
         .globl _misaligned
 _misaligned:
         bx lr
 
         @ And a properly aligned one.
         .globl _aligned
         .p2align 2
         .arm

llvm/test/MC/ARM/thumb-function-address.s

 @ CHECK:      Value Size Type   Bind  Vis     Ndx Name
 @ CHECK-NEXT: 00000000 0 NOTYPE LOCAL DEFAULT     UND
 @ CHECK-NEXT: 00000001 0 FUNC   LOCAL DEFAULT 2   func_label
 @ CHECK-NEXT: 00000001 0 FUNC   LOCAL DEFAULT 2   foo_impl
 @ CHECK-NEXT: 00000000 0 NOTYPE LOCAL DEFAULT 2   $t.0
 @ CHECK-NEXT: 00000003 0 FUNC   LOCAL DEFAULT 2   foo_resolver
 @ CHECK-NEXT: 00000003 0 IFUNC  LOCAL DEFAULT 2   foo
 @ CHECK-NEXT: 00000004 0 FUNC   LOCAL DEFAULT 2   label
-@ CHECK-NEXT: 00000006 0 NOTYPE LOCAL DEFAULT 2   $a.1
+@ CHECK-NEXT: 00000008 0 NOTYPE LOCAL DEFAULT 2   $a.1

llvm/test/MC/ARM/thumb-types.s

 @ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s | llvm-readelf -s - | FileCheck %s
 
 @ CHECK:      Num:    Value  Size Type    Bind   Vis      Ndx Name
 @ CHECK-NEXT:   0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND
 @ CHECK-NEXT:   1: 00000001     0 FUNC    LOCAL  DEFAULT    2 implicit_function
 @ CHECK-NEXT:   2: 00000000     0 NOTYPE  LOCAL  DEFAULT    2 $t.0
 @ CHECK-NEXT:   3: 00000002     0 OBJECT  LOCAL  DEFAULT    2 implicit_data
 @ CHECK-NEXT:   4: 00000002     0 NOTYPE  LOCAL  DEFAULT    2 $d.1
-@ CHECK-NEXT:   5: 00000006     0 FUNC    LOCAL  DEFAULT    2 arm_function
-@ CHECK-NEXT:   6: 00000006     0 NOTYPE  LOCAL  DEFAULT    2 $a.2
-@ CHECK-NEXT:   7: 0000000a     0 NOTYPE  LOCAL  DEFAULT    2 untyped_text_label
-@ CHECK-NEXT:   8: 0000000a     0 NOTYPE  LOCAL  DEFAULT    2 $t.3
-@ CHECK-NEXT:   9: 0000000d     0 FUNC    LOCAL  DEFAULT    2 explicit_function
-@ CHECK-NEXT:  10: 0000000e     0 NOTYPE  LOCAL  DEFAULT    2 $d.4
+@ CHECK-NEXT:   5: 00000008     0 FUNC    LOCAL  DEFAULT    2 arm_function
+@ CHECK-NEXT:   6: 00000008     0 NOTYPE  LOCAL  DEFAULT    2 $a.2
+@ CHECK-NEXT:   7: 0000000c     0 NOTYPE  LOCAL  DEFAULT    2 untyped_text_label
+@ CHECK-NEXT:   8: 0000000c     0 NOTYPE  LOCAL  DEFAULT    2 $t.3
+@ CHECK-NEXT:   9: 0000000f     0 FUNC    LOCAL  DEFAULT    2 explicit_function
+@ CHECK-NEXT:  10: 00000010     0 NOTYPE  LOCAL  DEFAULT    2 $d.4
 @ CHECK-NEXT:  11: 00000000     4 TLS     LOCAL  DEFAULT    5 tls
-@ CHECK-NEXT:  12: 00000013     0 IFUNC   LOCAL  DEFAULT    2 indirect_function
-@ CHECK-NEXT:  13: 00000012     0 NOTYPE  LOCAL  DEFAULT    2 $t.5
+@ CHECK-NEXT:  12: 00000015     0 IFUNC   LOCAL  DEFAULT    2 indirect_function
+@ CHECK-NEXT:  13: 00000014     0 NOTYPE  LOCAL  DEFAULT    2 $t.5
 @ CHECK-NEXT:  14: 00000000     0 NOTYPE  LOCAL  DEFAULT    4 untyped_data_label
 @ CHECK-NEXT:  15: 00000000     0 NOTYPE  LOCAL  DEFAULT    4 $t.6
 @ CHECK-NEXT:  16: 00000002     0 OBJECT  LOCAL  DEFAULT    4 explicit_data
 @ CHECK-NEXT:  17: 00000002     0 NOTYPE  LOCAL  DEFAULT    4 $d.7
 
 
   .syntax unified