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Differential D147184

[clang][CodeGenCXX] Improve handling of itanium ABI member function alignment requirements
ClosedPublic

Authored by daltenty on Mar 29 2023, 2:05 PM.

Details

Reviewers
hubert.reinterpretcast
MikeStump
Commits
rG196c144d0bc1: [clang][CodeGenCXX] Improve handling of itanium ABI member function alignment…
Summary

The itanium ABI for certain platforms requires a minimum alignments for
member function pointers to reserve certain bits for distinguishing
virtual and non-virtual functions.

Clang's implementation of this however depends on the alignment of the
function involved, which may however not reflect the true alignment of
function pointers on certain targets for which the alignment is
independent of the function (e.g. AIX). Worse, the 2-byte alignment
we use may be less than the ABI minimum for the target, and in the case
we are using explicit sections will result in invalid codegen.

This patch attempts to correct this situation by considering the target
alignment of function pointers as part of making the decision about
whether we need to adjust the function alignment to conform to the ABI.
Targets which do not provide the function ptr alignment information
will return a value of 1 when queried and will conservatively retain
the old alignment.

Diff Detail

Unit TestsFailed

TimeTest
1,240 mslibcxx CI C++2b > llvm-libc++-shared-cfg-in.std/utilities/utility/mem_res/mem_poly_allocator_class/mem_poly_allocator_mem::construct_pair.pass.cpp
320 mslibcxx CI Modules > llvm-libc++-shared-cfg-in.std/utilities/utility/mem_res/mem_poly_allocator_class/mem_poly_allocator_mem::construct_pair.pass.cpp

Event Timeline

daltenty created this revision.Mar 29 2023, 2:05 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2023, 2:05 PM
Herald added subscribers: mattd, asavonic, abrachet and 2 others. · View Herald Transcript
daltenty requested review of this revision.Mar 29 2023, 2:05 PM
Herald added a subscriber: aheejin. · View Herald TranscriptMar 29 2023, 2:05 PM
daltenty added a reviewer: MikeStump.Mar 29 2023, 2:11 PM
daltenty added a parent revision: D147016: [PowerPC] Add function pointer alignment to DataLayout.
Harbormaster completed remote builds in B222594: Diff 509475.Mar 29 2023, 3:48 PM
hubert.reinterpretcast added inline comments.Jul 3 2023, 9:05 PM
clang/lib/CodeGen/CodeGenModule.cpp
2152

Out-of-scope comment: Only non-static member functions need this.

2153

Is there a platform where the pointer alignment is less than 2 when the function has a higher alignment? If there is one, then let's test the effect of this line explicitly.

daltenty mentioned this in rGcf08c103266b: [NFC][clang] add extra member-alignment testcase.Jul 5 2023, 1:44 PM
daltenty added inline comments.Jul 5 2023, 1:52 PM
clang/lib/CodeGen/CodeGenModule.cpp
2153

Is there a platform where the pointer alignment is less than 2 when the function has a higher alignment?

TL;DR: ARM is a platform like this. I've added an extra test in https://reviews.llvm.org/rGcf08c103266b7ee59cbc2352c4d20f27472cb257 to demonstrate nothing changes.

  1. Function ptr alignment follows function alignment
  2. Function ptr alignment follows function alignment; and: a) function ptr alignment > 2 b) function ptr alignment < 2

Previous to this patch, this code assumed 1. Afterwards, we handle 1 and 2a here.

For a platform which case 2b, which is what you describe, you can't use this mechanism for discriminating between virtual and non-virtual member functions, so such a platform should really return false for getCXXABI().areMemberFunctionsAligned(). But platforms in this case don't like ARM, which notes that TODO here: https://github.com/llvm/llvm-project/blob/cfbcbc8f88eda598a42806fdb92bef107d23c898/clang/include/clang/Basic/TargetCXXABI.h#L168. Those platforms will simply continue to observe the extra unneeded alignment (2) or the specified alignment, which ever is greater, as they did before.

daltenty updated this revision to Diff 537486.Jul 5 2023, 1:55 PM

Rebase on latest main

Harbormaster completed remote builds in B243299: Diff 537486.Jul 5 2023, 2:23 PM
hubert.reinterpretcast accepted this revision.Jul 5 2023, 4:02 PM

LGTM; thanks!

This revision is now accepted and ready to land.Jul 5 2023, 4:02 PM
This revision was landed with ongoing or failed builds.Jul 6 2023, 7:36 AM
Closed by commit rG196c144d0bc1: [clang][CodeGenCXX] Improve handling of itanium ABI member function alignment… (authored by daltenty). · Explain Why
This revision was automatically updated to reflect the committed changes.
daltenty added a commit: rG196c144d0bc1: [clang][CodeGenCXX] Improve handling of itanium ABI member function alignment….
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 7:36 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
daltenty mentioned this in D154673: [test-suite] Add a simple test for class member functions in a custom section.Jul 6 2023, 6:55 PM
daltenty mentioned this in rT15b1eb67b79b: Add a test for class members in a custom section.Jul 13 2023, 11:16 AM

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Diff 509475

clang/lib/CodeGen/CodeGenModule.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,143 Lines • ▼ Show 20 Lines if (!D->hasAttr<AlignedAttr>())
if (LangOpts.FunctionAlignment) if (LangOpts.FunctionAlignment)
F->setAlignment(llvm::Align(1ull << LangOpts.FunctionAlignment)); F->setAlignment(llvm::Align(1ull << LangOpts.FunctionAlignment));
// Some C++ ABIs require 2-byte alignment for member functions, in order to // Some C++ ABIs require 2-byte alignment for member functions, in order to
// reserve a bit for differentiating between virtual and non-virtual member // reserve a bit for differentiating between virtual and non-virtual member
// functions. If the current target's C++ ABI requires this and this is a // functions. If the current target's C++ ABI requires this and this is a
// member function, set its alignment accordingly. // member function, set its alignment accordingly.
if (getTarget().getCXXABI().areMemberFunctionsAligned()) { if (getTarget().getCXXABI().areMemberFunctionsAligned()) {
if (F->getAlignment() < 2 && isa<CXXMethodDecl>(D)) if (F->getPointerAlignment(getDataLayout()) < 2 && isa<CXXMethodDecl>(D))
hubert.reinterpretcastUnsubmitted
Not Done
ReplyInline Actions

Out-of-scope comment: Only non-static member functions need this.

hubert.reinterpretcast: Out-of-scope comment: Only non-static member functions need this.
F->setAlignment(llvm::Align(2)); F->setAlignment(std::max(llvm::Align(2), F->getAlign().valueOrOne()));
hubert.reinterpretcastUnsubmitted
Not Done
ReplyInline Actions

Is there a platform where the pointer alignment is less than 2 when the function has a higher alignment? If there is one, then let's test the effect of this line explicitly.

hubert.reinterpretcast: Is there a platform where the pointer alignment is less than 2 when the function has a higher…
daltentyAuthorUnsubmitted
Done
ReplyInline Actions

Is there a platform where the pointer alignment is less than 2 when the function has a higher alignment?

TL;DR: ARM is a platform like this. I've added an extra test in https://reviews.llvm.org/rGcf08c103266b7ee59cbc2352c4d20f27472cb257 to demonstrate nothing changes.

  1. Function ptr alignment follows function alignment
  2. Function ptr alignment follows function alignment; and: a) function ptr alignment > 2 b) function ptr alignment < 2

Previous to this patch, this code assumed 1. Afterwards, we handle 1 and 2a here.

For a platform which case 2b, which is what you describe, you can't use this mechanism for discriminating between virtual and non-virtual member functions, so such a platform should really return false for getCXXABI().areMemberFunctionsAligned(). But platforms in this case don't like ARM, which notes that TODO here: https://github.com/llvm/llvm-project/blob/cfbcbc8f88eda598a42806fdb92bef107d23c898/clang/include/clang/Basic/TargetCXXABI.h#L168. Those platforms will simply continue to observe the extra unneeded alignment (2) or the specified alignment, which ever is greater, as they did before.

daltenty: > Is there a platform where the pointer alignment is less than 2 when the function has a higher…
} }
// In the cross-dso CFI mode with canonical jump tables, we want !type // In the cross-dso CFI mode with canonical jump tables, we want !type
// attributes on definitions only. // attributes on definitions only.
if (CodeGenOpts.SanitizeCfiCrossDso && if (CodeGenOpts.SanitizeCfiCrossDso &&
CodeGenOpts.SanitizeCfiCanonicalJumpTables) { CodeGenOpts.SanitizeCfiCanonicalJumpTables) {
if (auto *FD = dyn_cast<FunctionDecl>(D)) { if (auto *FD = dyn_cast<FunctionDecl>(D)) {
// Skip available_externally functions. They won't be codegen'ed in the // Skip available_externally functions. They won't be codegen'ed in the
▲ Show 20 Lines • Show All 5,085 Lines • Show Last 20 Lines

clang/test/CodeGenCXX/member-alignment.cpp

// RUN: %clang_cc1 -emit-llvm -triple %itanium_abi_triple %s -o - | \
// RUN: FileCheck -check-prefix CHECK-ITANIUM %s
// RUN: %clang_cc1 -emit-llvm -triple wasm32-unknown-unknown %s -o - | \ // RUN: %clang_cc1 -emit-llvm -triple wasm32-unknown-unknown %s -o - | \
// RUN: FileCheck -check-prefix CHECK-WEBASSEMBLY32 %s // RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple wasm64-unknown-unknown %s -o - | \ // RUN: %clang_cc1 -emit-llvm -triple wasm64-unknown-unknown %s -o - | \
// RUN: FileCheck -check-prefix CHECK-WEBASSEMBLY64 %s // RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple ppc64le-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple arm64-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple arm64-apple-ios %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple aarch64-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple mips-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple x86_64-unknown-fuchsia %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple powerpc-unknown-aix %s -o - | \
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple x86_64-unknown-windows-msvc %s -o - | \
// RUN: FileCheck -check-prefix CHECK-MSVC %s
// rdar://7268289 // rdar://7268289
class t { class t {
public: public:
virtual void foo(void); virtual void foo(void);
void bar(void); void bar(void);
}; };
void void
t::bar(void) { t::bar(void) {
// CHECK-ITANIUM: @_ZN1t3barEv({{.*}}) #0 align 2 { // CHECK-NOEXTRAALIGN: @_ZN1t3barEv({{.*}}) #0 {
// CHECK-WEBASSEMBLY32: @_ZN1t3barEv({{.*}}) #0 { // CHECK-EXTRAALIGN: @_ZN1t3barEv({{.*}}) #0 align 2 {
// CHECK-WEBASSEMBLY64: @_ZN1t3barEv({{.*}}) #0 { // CHECK-MSVC: @"?bar@t@@QEAAXXZ"({{.*}}) #0 align 2 {
} }
void void
t::foo(void) { t::foo(void) {
// CHECK-ITANIUM: @_ZN1t3fooEv({{.*}}) unnamed_addr #0 align 2 { // CHECK-NOEXTRAALIGN: @_ZN1t3fooEv({{.*}}) unnamed_addr #0 {
// CHECK-WEBASSEMBLY32: @_ZN1t3fooEv({{.*}}) unnamed_addr #0 { // CHECK-EXTRAALIGN: @_ZN1t3fooEv({{.*}}) unnamed_addr #0 align 2 {
// CHECK-WEBASSEMBLY64: @_ZN1t3fooEv({{.*}}) unnamed_addr #0 { // CHECK-MSVC: @"?foo@t@@UEAAXXZ"({{.*}}) unnamed_addr #0 align 2 {
} }

clang/test/Modules/cxx-irgen.cpp

Show All 21 Lines
namespace EmitInlineMethods { namespace EmitInlineMethods {
// CHECK-DAG: define linkonce_odr {{(dso_local )?}}[[CC]]void @_ZN17EmitInlineMethods1D1fEPNS_1BE( // CHECK-DAG: define linkonce_odr {{(dso_local )?}}[[CC]]void @_ZN17EmitInlineMethods1D1fEPNS_1BE(
// CHECK-DAG: define linkonce_odr {{(dso_local )?}}[[CC]]void @_ZN17EmitInlineMethods1B1gEv( // CHECK-DAG: define linkonce_odr {{(dso_local )?}}[[CC]]void @_ZN17EmitInlineMethods1B1gEv(
struct D { struct D {
__attribute__((used)) void f(B *p) { p->g(); } __attribute__((used)) void f(B *p) { p->g(); }
}; };
} }
// CHECK-DAG: define available_externally hidden {{.*}}{{signext i32|i32}} @_ZN1SIiE1gEv({{.*}} #[[ALWAYS_INLINE:.*]] align // CHECK-DAG: define available_externally hidden {{.*}}{{signext i32|i32}} @_ZN1SIiE1gEv({{.*}} #[[#ALWAYS_INLINE:]]
int a = S<int>::g(); int a = S<int>::g();
int b = h(); int b = h();
// CHECK-DAG: define linkonce_odr {{.*}}{{signext i32|i32}} @_Z3minIiET_S0_S0_(i32 // CHECK-DAG: define linkonce_odr {{.*}}{{signext i32|i32}} @_Z3minIiET_S0_S0_(i32
int c = min(1, 2); int c = min(1, 2);
// CHECK: define available_externally {{.*}}{{signext i32|i32}} @_ZN1SIiE1fEv({{.*}} #[[ALWAYS_INLINE]] align // CHECK: define available_externally {{.*}}{{signext i32|i32}} @_ZN1SIiE1fEv({{.*}} #[[#ALWAYS_INLINE]]
namespace ImplicitSpecialMembers { namespace ImplicitSpecialMembers {
// CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1BC2ERKS0_( // CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1BC2ERKS0_(
// CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_( // CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_(
// CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1BC2EOS0_( // CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1BC2EOS0_(
// CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_( // CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_(
// CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1CC2ERKS0_( // CHECK-LABEL: define {{.*}} @_ZN22ImplicitSpecialMembers1CC2ERKS0_(
// CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_( // CHECK: call {{.*}} @_ZN22ImplicitSpecialMembers1AC1ERKS0_(
Show All 23 Lines
namespace OperatorDeleteLookup { namespace OperatorDeleteLookup {
// Trigger emission of B's vtable and deleting dtor. // Trigger emission of B's vtable and deleting dtor.
// This requires us to know what operator delete was selected. // This requires us to know what operator delete was selected.
void g() { f(); } void g() { f(); }
} }
// CHECK: attributes #[[ALWAYS_INLINE]] = {{.*}} alwaysinline // CHECK: attributes #[[#ALWAYS_INLINE]] = {{.*}} alwaysinline

clang/test/OpenMP/distribute_firstprivate_codegen.cpp

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done2: // CHECK8: arraydestroy.done2:
// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK8-NEXT: ret i32 [[TMP41]] // CHECK8-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done13: // CHECK8: arraydestroy.done13:
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
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// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done2: // CHECK8: arraydestroy.done2:
// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK8-NEXT: ret i32 [[TMP36]] // CHECK8-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done13: // CHECK8: arraydestroy.done13:
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: store i32 0, ptr [[F]], align 4 // CHECK8-NEXT: store i32 0, ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp

Show First 20 Lines • Show All 579 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done9: // CHECK9: arraydestroy.done9:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done9: // CHECK9: arraydestroy.done9:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp

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// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done2: // CHECK8: arraydestroy.done2:
// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK8-NEXT: ret i32 [[TMP41]] // CHECK8-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done13: // CHECK8: arraydestroy.done13:
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
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// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done2: // CHECK8: arraydestroy.done2:
// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK8-NEXT: ret i32 [[TMP36]] // CHECK8-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK8-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK8-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK8: arraydestroy.done13: // CHECK8: arraydestroy.done13:
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: store i32 0, ptr [[F]], align 4 // CHECK8-NEXT: store i32 0, ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK12: arraydestroy.done7: // CHECK12: arraydestroy.done7:
// CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK12-NEXT: ret i32 [[TMP14]] // CHECK12-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK12-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK12: arraydestroy.done7: // CHECK12: arraydestroy.done7:
// CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK12-NEXT: ret i32 [[TMP14]] // CHECK12-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK12-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK12-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK12-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK12-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK12-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK12-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK12-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK12-NEXT: store i32 0, ptr [[F]], align 4 // CHECK12-NEXT: store i32 0, ptr [[F]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@main // CHECK14-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]]
// CHECK13: arraydestroy.done22: // CHECK13: arraydestroy.done22:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP20]] // CHECK13-NEXT: ret i32 [[TMP20]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]]
// CHECK13: arraydestroy.done21: // CHECK13: arraydestroy.done21:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done9: // CHECK9: arraydestroy.done9:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done9: // CHECK9: arraydestroy.done9:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK13: arraydestroy.done17: // CHECK13: arraydestroy.done17:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP11]] // CHECK13-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK13: arraydestroy.done17: // CHECK13: arraydestroy.done17:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP11]] // CHECK13-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/distribute_private_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done6: // CHECK9: arraydestroy.done6:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP31]] // CHECK9-NEXT: ret i32 [[TMP31]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done7: // CHECK13: arraydestroy.done7:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP14]] // CHECK13-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done7: // CHECK13: arraydestroy.done7:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP14]] // CHECK13-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]]
// CHECK13: arraydestroy.done22: // CHECK13: arraydestroy.done22:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP20]] // CHECK13-NEXT: ret i32 [[TMP20]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]]
// CHECK13: arraydestroy.done21: // CHECK13: arraydestroy.done21:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/distribute_simd_private_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done6: // CHECK9: arraydestroy.done6:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP38]] // CHECK9-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]]
// CHECK13: arraydestroy.done32: // CHECK13: arraydestroy.done32:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP16]] // CHECK13-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK13: arraydestroy.done17: // CHECK13: arraydestroy.done17:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP11]] // CHECK13-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/nvptx_lambda_capturing.cpp

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// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP12]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP12]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1S3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN1S3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
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// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false)
// CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8 // CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv // CHECK1-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR3]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR3]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
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clang/test/OpenMP/reduction_implicit_map.cpp

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// CHECK1: omp_offload.failed5: // CHECK1: omp_offload.failed5:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55(ptr [[B]]) #[[ATTR8]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55(ptr [[B]]) #[[ATTR8]]
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]]
// CHECK1: omp_offload.cont6: // CHECK1: omp_offload.cont6:
// CHECK1-NEXT: ret i32 0 // CHECK1-NEXT: ret i32 0
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr double, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr double, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]]
// CHECK1: omp.arraycpy.done2: // CHECK1: omp.arraycpy.done2:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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clang/test/OpenMP/target_data_use_device_ptr_inheritance_codegen.cpp

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// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1A, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8 // CHECK-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1A, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8
// CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [[CLASS_A:%.*]], ptr [[THIS1]], i32 0, i32 1 // CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [[CLASS_A:%.*]], ptr [[THIS1]], i32 0, i32 1
// CHECK-NEXT: store ptr null, ptr [[PTR]], align 8 // CHECK-NEXT: store ptr null, ptr [[PTR]], align 8
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// CHECK1-LABEL: define {{[^@]+}}@_ZN1B3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN1B3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
// CHECK1-NEXT: [[PTR4:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[PTR4:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[B:%.*]] = alloca [[CLASS_B:%.*]], align 8 // CHECK1-NEXT: [[B:%.*]] = alloca [[CLASS_B:%.*]], align 8
// CHECK1-NEXT: call void @_ZN1BC1Ev(ptr noundef nonnull align 8 dereferenceable(16) [[B]]) #[[ATTR1:[0-9]+]] // CHECK1-NEXT: call void @_ZN1BC1Ev(ptr noundef nonnull align 8 dereferenceable(16) [[B]]) #[[ATTR1:[0-9]+]]
// CHECK1-NEXT: call void @_ZN1B3fooEv(ptr noundef nonnull align 8 dereferenceable(16) [[B]]) // CHECK1-NEXT: call void @_ZN1B3fooEv(ptr noundef nonnull align 8 dereferenceable(16) [[B]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1BC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1BC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1BC2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR1]] // CHECK1-NEXT: call void @_ZN1BC2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR1]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1BC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1BC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1AC2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR1]] // CHECK1-NEXT: call void @_ZN1AC2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR1]]
// CHECK1-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1B, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8 // CHECK1-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1B, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1AC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1AC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1A, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8 // CHECK1-NEXT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1A, i32 0, inrange i32 0, i32 2), ptr [[THIS1]], align 8
// CHECK1-NEXT: [[PTR:%.*]] = getelementptr inbounds [[CLASS_A:%.*]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[PTR:%.*]] = getelementptr inbounds [[CLASS_A:%.*]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store ptr null, ptr [[PTR]], align 8 // CHECK1-NEXT: store ptr null, ptr [[PTR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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clang/test/OpenMP/target_firstprivate_codegen.cpp

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// CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// CHECK0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // CHECK0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// CHECK0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// CHECK0-NEXT: ret i32 [[TMP9]] // CHECK0-NEXT: ret i32 [[TMP9]]
// //
// //
// CHECK0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK0-NEXT: entry: // CHECK0-NEXT: entry:
// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK0-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK0-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 // CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
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// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP9]] // CHECK1-NEXT: ret i32 [[TMP9]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
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// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // SIMD-ONLY0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// SIMD-ONLY0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // SIMD-ONLY0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY0-NEXT: ret i32 [[TMP9]] // SIMD-ONLY0-NEXT: ret i32 [[TMP9]]
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// SIMD-ONLY0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// SIMD-ONLY0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY01-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // SIMD-ONLY01-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// SIMD-ONLY01-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // SIMD-ONLY01-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY01-NEXT: ret i32 [[TMP9]] // SIMD-ONLY01-NEXT: ret i32 [[TMP9]]
// //
// //
// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// SIMD-ONLY01-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY01-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY01-NEXT: entry: // SIMD-ONLY01-NEXT: entry:
// SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// SIMD-ONLY01-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD-ONLY01-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // SIMD-ONLY1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// SIMD-ONLY1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // SIMD-ONLY1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY1-NEXT: ret i32 [[TMP9]] // SIMD-ONLY1-NEXT: ret i32 [[TMP9]]
// //
// //
// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// SIMD-ONLY1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: entry:
// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// SIMD-ONLY1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] // SIMD-ONLY11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
// SIMD-ONLY11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 // SIMD-ONLY11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
// SIMD-ONLY11-NEXT: ret i32 [[TMP9]] // SIMD-ONLY11-NEXT: ret i32 [[TMP9]]
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// SIMD-ONLY11-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY11-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
// SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// SIMD-ONLY11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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clang/test/OpenMP/target_has_device_addr_codegen.cpp

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// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init
// CHECK-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1b) // CHECK-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1b)
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN2S2C1Ev // CHECK-LABEL: define {{[^@]+}}@_ZN2S2C1Ev
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN2S2C2Ev // CHECK-LABEL: define {{[^@]+}}@_ZN2S2C2Ev
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: store i32 0, ptr [[A]], align 4 // CHECK-NEXT: store i32 0, ptr [[A]], align 4
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
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// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
// CHECK-SAME: () #[[ATTR0]] { // CHECK-SAME: () #[[ATTR0]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: call void @_ZN2S3C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1c) // CHECK-NEXT: call void @_ZN2S3C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1c)
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN2S3C1Ev // CHECK-LABEL: define {{[^@]+}}@_ZN2S3C1Ev
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: call void @_ZN2S3C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK-NEXT: call void @_ZN2S3C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN2S3C2Ev // CHECK-LABEL: define {{[^@]+}}@_ZN2S3C2Ev
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S3:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S3:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: store i32 0, ptr [[A]], align 4 // CHECK-NEXT: store i32 0, ptr [[A]], align 4
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
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// CHECK-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4 // CHECK-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4
// CHECK-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // CHECK-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]])
// CHECK-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // CHECK-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]])
// CHECK-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR5]] // CHECK-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR5]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN10SomeKernel5applyILj32EEEvv // CHECK-LABEL: define {{[^@]+}}@_ZN10SomeKernel5applyILj32EEEvv
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR6]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR6]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init
// SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] { // SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1b) // SIMD-ONLY0-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1b)
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S2C1Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S2C1Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY0-NEXT: call void @_ZN2S2C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
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// SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // SIMD-ONLY0-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
// SIMD-ONLY0-SAME: () #[[ATTR0]] { // SIMD-ONLY0-SAME: () #[[ATTR0]] {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: call void @_ZN2S3C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1c) // SIMD-ONLY0-NEXT: call void @_ZN2S3C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @_ZL1c)
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S3C1Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S3C1Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: call void @_ZN2S3C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY0-NEXT: call void @_ZN2S3C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
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// SIMD-ONLY0-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4 // SIMD-ONLY0-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4
// SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]])
// SIMD-ONLY0-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // SIMD-ONLY0-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]])
// SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR7:[0-9]+]] // SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR7:[0-9]+]]
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN10SomeKernel5applyILj32EEEvv // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN10SomeKernel5applyILj32EEEvv
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[TARGETDEV:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TARGETDEV:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[TARGETDEV]], align 4 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[TARGETDEV]], align 4
// SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
// SIMD-ONLY0-NEXT: [[DEVPTR:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL]], ptr [[THIS1]], i32 0, i32 1 // SIMD-ONLY0-NEXT: [[DEVPTR:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL]], ptr [[THIS1]], i32 0, i32 1
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load float, ptr [[DEVPTR]], align 4 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load float, ptr [[DEVPTR]], align 4
// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd float [[TMP1]], 1.000000e+00 // SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd float [[TMP1]], 1.000000e+00
// SIMD-ONLY0-NEXT: store float [[INC]], ptr [[DEVPTR]], align 4 // SIMD-ONLY0-NEXT: store float [[INC]], ptr [[DEVPTR]], align 4
// SIMD-ONLY0-NEXT: [[TARGETDEV2:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TARGETDEV2:%.*]] = getelementptr inbounds [[STRUCT_SOMEKERNEL]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[TARGETDEV2]], align 4 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[TARGETDEV2]], align 4
// SIMD-ONLY0-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY0-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP2]], 1
// SIMD-ONLY0-NEXT: store i32 [[INC3]], ptr [[TARGETDEV2]], align 4 // SIMD-ONLY0-NEXT: store i32 [[INC3]], ptr [[TARGETDEV2]], align 4
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S2C2Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S2C2Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S3C2Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S3C2Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S3:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_S3:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
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clang/test/OpenMP/target_has_device_addr_codegen_01.cpp

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
// CHECK-NEXT: store i32 [[CONV1]], ptr [[RETVAL]], align 4 // CHECK-NEXT: store i32 [[CONV1]], ptr [[RETVAL]], align 4
// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP42]]) // CHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP42]])
// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK-NEXT: ret i32 [[TMP43]] // CHECK-NEXT: ret i32 [[TMP43]]
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN1SC1Ev // CHECK-LABEL: define {{[^@]+}}@_ZN1SC1Ev
// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 8 dereferenceable(40) [[THIS1]]) // CHECK-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 8 dereferenceable(40) [[THIS1]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN1S3fooEv // CHECK-LABEL: define {{[^@]+}}@_ZN1S3fooEv
// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 // CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
// CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 // CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 0 // CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 0
// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 // CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
// CHECK-NEXT: [[INC7:%.*]] = fadd float [[TMP11]], 1.000000e+00 // CHECK-NEXT: [[INC7:%.*]] = fadd float [[TMP11]], 1.000000e+00
// CHECK-NEXT: store float [[INC7]], ptr [[ARRAYIDX6]], align 4 // CHECK-NEXT: store float [[INC7]], ptr [[ARRAYIDX6]], align 4
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN1SC2Ev // CHECK-LABEL: define {{[^@]+}}@_ZN1SC2Ev
// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: store i32 0, ptr [[A]], align 8 // CHECK-NEXT: store i32 0, ptr [[A]], align 8
// CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 1 // CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 1
// CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY0-NEXT: store i32 [[CONV6]], ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: store i32 [[CONV6]], ptr [[RETVAL]], align 4
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP13]])
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// SIMD-ONLY0-NEXT: ret i32 [[TMP14]] // SIMD-ONLY0-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC1Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC1Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 8 dereferenceable(40) [[THIS1]]) // SIMD-ONLY0-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 8 dereferenceable(40) [[THIS1]])
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1S3fooEv // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1S3fooEv
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 8 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 8
// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[A]], align 8 // SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[A]], align 8
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// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 0 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 0
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 8 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 8
// SIMD-ONLY0-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP5]], 1 // SIMD-ONLY0-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP5]], 1
// SIMD-ONLY0-NEXT: store i32 [[INC4]], ptr [[ARRAYIDX]], align 8 // SIMD-ONLY0-NEXT: store i32 [[INC4]], ptr [[ARRAYIDX]], align 8
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC2Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC2Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 8 // SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 8
// SIMD-ONLY0-NEXT: [[PTR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 1 // SIMD-ONLY0-NEXT: [[PTR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 1
// SIMD-ONLY0-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: store ptr [[A2]], ptr [[PTR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[A2]], ptr [[PTR]], align 8
// SIMD-ONLY0-NEXT: [[REF:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 2 // SIMD-ONLY0-NEXT: [[REF:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 2
// SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY0-NEXT: store ptr [[A3]], ptr [[REF]], align 8 // SIMD-ONLY0-NEXT: store ptr [[A3]], ptr [[REF]], align 8
// SIMD-ONLY0-NEXT: ret void // SIMD-ONLY0-NEXT: ret void
// //

clang/test/OpenMP/target_is_device_ptr_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CK20-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]]) // CK20-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8 // CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
// CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1 // CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
// CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8 // CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
// CK20-NEXT: ret void // CK20-NEXT: ret void
// //
// //
// CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd // CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CK20-NEXT: entry: // CK20-NEXT: entry:
// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// CK20-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]]) // CK20-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
// CK20-NEXT: ret void // CK20-NEXT: ret void
// //
// //
// CK20-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd // CK20-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 { // CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat {
// CK20-NEXT: entry: // CK20-NEXT: entry:
// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: [[LA:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[LA:%.*]] = alloca ptr, align 8
// CK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CK20-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CK20-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CK20: omp_offload.failed15: // CK20: omp_offload.failed15:
// CK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]] // CK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
// CK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CK20-NEXT: br label [[OMP_OFFLOAD_CONT16]]
// CK20: omp_offload.cont16: // CK20: omp_offload.cont16:
// CK20-NEXT: ret void // CK20-NEXT: ret void
// //
// //
// CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd // CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CK20-NEXT: entry: // CK20-NEXT: entry:
// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CK20-NEXT: store ptr null, ptr [[A]], align 8 // CK20-NEXT: store ptr null, ptr [[A]], align 8
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// CK21-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]]) // CK21-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8 // CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
// CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1 // CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
// CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8 // CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
// CK21-NEXT: ret void // CK21-NEXT: ret void
// //
// //
// CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd // CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CK21-NEXT: entry: // CK21-NEXT: entry:
// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// CK21-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]]) // CK21-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
// CK21-NEXT: ret void // CK21-NEXT: ret void
// //
// //
// CK21-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd // CK21-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 { // CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat {
// CK21-NEXT: entry: // CK21-NEXT: entry:
// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: [[LA:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[LA:%.*]] = alloca ptr, align 8
// CK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CK21-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CK21-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CK21-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CK21-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CK21-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CK21-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CK21: omp_offload.failed15: // CK21: omp_offload.failed15:
// CK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]] // CK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
// CK21-NEXT: br label [[OMP_OFFLOAD_CONT16]] // CK21-NEXT: br label [[OMP_OFFLOAD_CONT16]]
// CK21: omp_offload.cont16: // CK21: omp_offload.cont16:
// CK21-NEXT: ret void // CK21-NEXT: ret void
// //
// //
// CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd // CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CK21-NEXT: entry: // CK21-NEXT: entry:
// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CK21-NEXT: store ptr null, ptr [[A]], align 8 // CK21-NEXT: store ptr null, ptr [[A]], align 8
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// SIMD-ONLY10-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]]) // SIMD-ONLY10-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8 // SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1 // SIMD-ONLY10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
// SIMD-ONLY10-NEXT: ret void // SIMD-ONLY10-NEXT: ret void
// //
// //
// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd // SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// SIMD-ONLY10-NEXT: entry: // SIMD-ONLY10-NEXT: entry:
// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// SIMD-ONLY10-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]]) // SIMD-ONLY10-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
// SIMD-ONLY10-NEXT: ret void // SIMD-ONLY10-NEXT: ret void
// //
// //
// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd // SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY10-NEXT: entry: // SIMD-ONLY10-NEXT: entry:
// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: [[LA:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[LA:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: store ptr null, ptr [[LA]], align 8 // SIMD-ONLY10-NEXT: store ptr null, ptr [[LA]], align 8
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// SIMD-ONLY10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8 // SIMD-ONLY10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8
// SIMD-ONLY10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// SIMD-ONLY10-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1 // SIMD-ONLY10-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8 // SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8
// SIMD-ONLY10-NEXT: ret void // SIMD-ONLY10-NEXT: ret void
// //
// //
// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd // SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// SIMD-ONLY10-NEXT: entry: // SIMD-ONLY10-NEXT: entry:
// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY10-NEXT: store ptr null, ptr [[A]], align 8 // SIMD-ONLY10-NEXT: store ptr null, ptr [[A]], align 8
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// SIMD-ONLY11-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]]) // SIMD-ONLY11-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1 // SIMD-ONLY11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
// SIMD-ONLY11-NEXT: ret void // SIMD-ONLY11-NEXT: ret void
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// SIMD-ONLY11-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]]) // SIMD-ONLY11-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
// SIMD-ONLY11-NEXT: ret void // SIMD-ONLY11-NEXT: ret void
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: [[LA:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[LA:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store ptr null, ptr [[LA]], align 8 // SIMD-ONLY11-NEXT: store ptr null, ptr [[LA]], align 8
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// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8 // SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8
// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// SIMD-ONLY11-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1 // SIMD-ONLY11-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8 // SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8
// SIMD-ONLY11-NEXT: ret void // SIMD-ONLY11-NEXT: ret void
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// SIMD-ONLY11-NEXT: store ptr null, ptr [[A]], align 8 // SIMD-ONLY11-NEXT: store ptr null, ptr [[A]], align 8
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clang/test/OpenMP/target_map_codegen_hold.cpp

Show First 20 Lines • Show All 362 Lines • ▼ Show 20 Lines
// CHECK-USE-PPC64LE-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK-USE-PPC64LE-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK-USE-PPC64LE-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK-USE-PPC64LE-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK-USE-PPC64LE-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK-USE-PPC64LE-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK-USE-PPC64LE-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 // CHECK-USE-PPC64LE-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4
// CHECK-USE-PPC64LE-NEXT: ret void // CHECK-USE-PPC64LE-NEXT: ret void
// //
// //
// CHECK-USE-PPC64LE-LABEL: define {{[^@]+}}@_ZN2ST20test_present_membersEv // CHECK-USE-PPC64LE-LABEL: define {{[^@]+}}@_ZN2ST20test_present_membersEv
// CHECK-USE-PPC64LE-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK-USE-PPC64LE-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] {
// CHECK-USE-PPC64LE-NEXT: entry: // CHECK-USE-PPC64LE-NEXT: entry:
// CHECK-USE-PPC64LE-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-USE-PPC64LE-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
// CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK-USE-PPC64LE-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK-USE-PPC64LE-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK-USE-PPC64LE-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK-USE-PPC64LE-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-USE-PPC64LE-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// //
// CHECK-NOUSE-PPC64LE-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l114 // CHECK-NOUSE-PPC64LE-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l114
// CHECK-NOUSE-PPC64LE-SAME: () #[[ATTR1]] { // CHECK-NOUSE-PPC64LE-SAME: () #[[ATTR1]] {
// CHECK-NOUSE-PPC64LE-NEXT: entry: // CHECK-NOUSE-PPC64LE-NEXT: entry:
// CHECK-NOUSE-PPC64LE-NEXT: ret void // CHECK-NOUSE-PPC64LE-NEXT: ret void
// //
// //
// CHECK-NOUSE-PPC64LE-LABEL: define {{[^@]+}}@_ZN2ST20test_present_membersEv // CHECK-NOUSE-PPC64LE-LABEL: define {{[^@]+}}@_ZN2ST20test_present_membersEv
// CHECK-NOUSE-PPC64LE-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK-NOUSE-PPC64LE-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] {
// CHECK-NOUSE-PPC64LE-NEXT: entry: // CHECK-NOUSE-PPC64LE-NEXT: entry:
// CHECK-NOUSE-PPC64LE-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK-NOUSE-PPC64LE-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK-NOUSE-PPC64LE-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK-NOUSE-PPC64LE-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NOUSE-PPC64LE-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK-NOUSE-I386-NEXT: ret void // CHECK-NOUSE-I386-NEXT: ret void
// //
// //
// CHECK-NOUSE-I386-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK-NOUSE-I386-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK-NOUSE-I386-SAME: () #[[ATTR4:[0-9]+]] { // CHECK-NOUSE-I386-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK-NOUSE-I386-NEXT: entry: // CHECK-NOUSE-I386-NEXT: entry:
// CHECK-NOUSE-I386-NEXT: call void @__tgt_register_requires(i64 1) // CHECK-NOUSE-I386-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK-NOUSE-I386-NEXT: ret void // CHECK-NOUSE-I386-NEXT: ret void
//

clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP6]] // CHECK1-NEXT: ret i32 [[TMP6]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
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clang/test/OpenMP/target_parallel_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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clang/test/OpenMP/target_parallel_for_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK17-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK17-NEXT: ret i32 [[TMP8]] // CHECK17-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK17-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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clang/test/OpenMP/target_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: ret i32 [[TMP8]] // CHECK5-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: ret i32 [[TMP8]] // CHECK9-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: ret i32 [[TMP8]] // CHECK13-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8
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clang/test/OpenMP/target_parallel_if_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP6]] // CHECK1-NEXT: ret i32 [[TMP6]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
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clang/test/OpenMP/target_parallel_num_threads_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP6]] // CHECK1-NEXT: ret i32 [[TMP6]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
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clang/test/OpenMP/target_teams_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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clang/test/OpenMP/target_teams_distribute_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done12: // CHECK1: arraydestroy.done12:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP34]] // CHECK1-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done13: // CHECK1: arraydestroy.done13:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP39]] // CHECK9-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP34]] // CHECK9-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP34]] // CHECK1-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done10: // CHECK1: arraydestroy.done10:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done14: // CHECK1: arraydestroy.done14:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done1: // CHECK5: arraydestroy.done1:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done8: // CHECK13: arraydestroy.done8:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done13: // CHECK13: arraydestroy.done13:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done10: // CHECK13: arraydestroy.done10:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done14: // CHECK13: arraydestroy.done14:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[A]], align 4 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4
// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK13-NEXT: store i32 0, ptr [[B]], align 4 // CHECK13-NEXT: store i32 0, ptr [[B]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp

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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done2: // CHECK5: arraydestroy.done2:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP39]] // CHECK5-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done16: // CHECK5: arraydestroy.done16:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done2: // CHECK5: arraydestroy.done2:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP34]] // CHECK5-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done15: // CHECK5: arraydestroy.done15:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: store i32 0, ptr [[F]], align 4 // CHECK5-NEXT: store i32 0, ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done9: // CHECK1: arraydestroy.done9:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done1: // CHECK5: arraydestroy.done1:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done3: // CHECK13: arraydestroy.done3:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done8: // CHECK13: arraydestroy.done8:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done5: // CHECK13: arraydestroy.done5:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done9: // CHECK13: arraydestroy.done9:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
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clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
▲ Show 20 Lines • Show All 4,315 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP34]] // CHECK1-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done10: // CHECK1: arraydestroy.done10:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done14: // CHECK1: arraydestroy.done14:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done1: // CHECK5: arraydestroy.done1:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK7-SAME: () #[[ATTR0]] { // CHECK7-SAME: () #[[ATTR0]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK7: arraydestroy.done5: // CHECK7: arraydestroy.done5:
// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK7-NEXT: ret i32 [[TMP14]] // CHECK7-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done8: // CHECK13: arraydestroy.done8:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done13: // CHECK13: arraydestroy.done13:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done10: // CHECK13: arraydestroy.done10:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done14: // CHECK13: arraydestroy.done14:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[A]], align 4 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4
// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK13-NEXT: store i32 0, ptr [[B]], align 4 // CHECK13-NEXT: store i32 0, ptr [[B]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK13-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK13-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp

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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done2: // CHECK5: arraydestroy.done2:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP39]] // CHECK5-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done16: // CHECK5: arraydestroy.done16:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done2: // CHECK5: arraydestroy.done2:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP34]] // CHECK5-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done15: // CHECK5: arraydestroy.done15:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: store i32 0, ptr [[F]], align 4 // CHECK5-NEXT: store i32 0, ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]]
// CHECK13: arraydestroy.done20: // CHECK13: arraydestroy.done20:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP20]] // CHECK13-NEXT: ret i32 [[TMP20]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]]
// CHECK13: arraydestroy.done19: // CHECK13: arraydestroy.done19:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp

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Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done9: // CHECK1: arraydestroy.done9:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done1: // CHECK5: arraydestroy.done1:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK7-SAME: () #[[ATTR0]] { // CHECK7-SAME: () #[[ATTR0]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK7: arraydestroy.done17: // CHECK7: arraydestroy.done17:
// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK7-NEXT: ret i32 [[TMP11]] // CHECK7-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_simd_private_codegen.cpp
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done3: // CHECK13: arraydestroy.done3:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done8: // CHECK13: arraydestroy.done8:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done5: // CHECK13: arraydestroy.done5:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK13: arraydestroy.done9: // CHECK13: arraydestroy.done9:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK9-NEXT: ret i32 [[CALL]] // CHECK9-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP8]] // CHECK1-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
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// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: ret i32 [[TMP8]] // CHECK5-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: ret i32 [[TMP8]] // CHECK9-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
// CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 // CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: ret i32 [[TMP8]] // CHECK13-NEXT: ret i32 [[TMP8]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done12: // CHECK1: arraydestroy.done12:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP34]] // CHECK1-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done13: // CHECK1: arraydestroy.done13:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done5: // CHECK5: arraydestroy.done5:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP13]] // CHECK5-NEXT: ret i32 [[TMP13]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]]
// CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP39]] // CHECK9-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]]
// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP34]] // CHECK9-NEXT: ret i32 [[TMP34]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]]
// CHECK13: arraydestroy.done20: // CHECK13: arraydestroy.done20:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]]
// CHECK13: arraydestroy.done19: // CHECK13: arraydestroy.done19:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP18]] // CHECK13-NEXT: ret i32 [[TMP18]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK5: arraydestroy.done17: // CHECK5: arraydestroy.done17:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP11]] // CHECK5-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/target_teams_num_teams_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP6]] // CHECK1-NEXT: ret i32 [[TMP6]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
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clang/test/OpenMP/target_teams_thread_limit_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: ret i32 [[TMP6]] // CHECK1-NEXT: ret i32 [[TMP6]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
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clang/test/OpenMP/teams_codegen.cpp

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// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(8) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(8) [[V]])
// CHECK17-NEXT: ret i32 [[CALL]] // CHECK17-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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clang/test/OpenMP/teams_distribute_codegen.cpp

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// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK17-NEXT: ret i32 [[CALL]] // CHECK17-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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clang/test/OpenMP/teams_distribute_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done12: // CHECK1: arraydestroy.done12:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP36]] // CHECK1-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done13: // CHECK1: arraydestroy.done13:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp

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// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK17-NEXT: ret i32 [[CALL]] // CHECK17-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP36]] // CHECK1-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done10: // CHECK1: arraydestroy.done10:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done14: // CHECK1: arraydestroy.done14:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp

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// CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
// CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
// CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
// CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
// CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
// CHECK1-NEXT: ret i8 [[CONV]] // CHECK1-NEXT: ret i8 [[CONV]]
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// CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 }
// CHECK1-NEXT: catch ptr null // CHECK1-NEXT: catch ptr null
// CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 // CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]] // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]]
// CHECK1-NEXT: unreachable // CHECK1-NEXT: unreachable
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
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// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
// CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
// CHECK5-NEXT: ret i8 [[CONV]] // CHECK5-NEXT: ret i8 [[CONV]]
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// CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 }
// CHECK5-NEXT: catch ptr null // CHECK5-NEXT: catch ptr null
// CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 // CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]] // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]]
// CHECK5-NEXT: unreachable // CHECK5-NEXT: unreachable
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
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// CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 }
// CHECK5-NEXT: catch ptr null // CHECK5-NEXT: catch ptr null
// CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0
// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR9]] // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR9]]
// CHECK5-NEXT: unreachable // CHECK5-NEXT: unreachable
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { // CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //

clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done9: // CHECK1: arraydestroy.done9:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp

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// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK17-NEXT: ret i32 [[CALL]] // CHECK17-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
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// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK21-NEXT: ret i32 [[CALL]] // CHECK21-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK21-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK21-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP36]] // CHECK1-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done10: // CHECK1: arraydestroy.done10:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done14: // CHECK1: arraydestroy.done14:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done6: // CHECK5: arraydestroy.done6:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP14]] // CHECK5-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
▲ Show 20 Lines • Show All 328 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done16: // CHECK9: arraydestroy.done16:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
▲ Show 20 Lines • Show All 314 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
▲ Show 20 Lines • Show All 1,147 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]]
// CHECK13: arraydestroy.done21: // CHECK13: arraydestroy.done21:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP20]] // CHECK13-NEXT: ret i32 [[TMP20]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]]
// CHECK13: arraydestroy.done20: // CHECK13: arraydestroy.done20:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp

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// CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
// CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
// CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
// CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
// CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
// CHECK1-NEXT: ret i8 [[CONV]] // CHECK1-NEXT: ret i8 [[CONV]]
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// CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 }
// CHECK1-NEXT: catch ptr null // CHECK1-NEXT: catch ptr null
// CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 // CHECK1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]] // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]]
// CHECK1-NEXT: unreachable // CHECK1-NEXT: unreachable
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36
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// CHECK3-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } // CHECK3-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 }
// CHECK3-NEXT: catch ptr null // CHECK3-NEXT: catch ptr null
// CHECK3-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 // CHECK3-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0
// CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP2]] // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP2]]
// CHECK3-NEXT: unreachable // CHECK3-NEXT: unreachable
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK3-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) // CHECK3-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv // CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
// CHECK3-NEXT: ret i8 [[CONV]] // CHECK3-NEXT: ret i8 [[CONV]]
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// CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 }
// CHECK3-NEXT: catch ptr null // CHECK3-NEXT: catch ptr null
// CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0
// CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP15]] // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP15]]
// CHECK3-NEXT: unreachable // CHECK3-NEXT: unreachable
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK3-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 // CHECK3-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@main // CHECK5-LABEL: define {{[^@]+}}@main
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// CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
// CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
// CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
// CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SC2El(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i64 noundef [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8
// CHECK5-NEXT: ret i8 [[CONV]] // CHECK5-NEXT: ret i8 [[CONV]]
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// CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 }
// CHECK5-NEXT: catch ptr null // CHECK5-NEXT: catch ptr null
// CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0 // CHECK5-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]] // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP34]]) #[[ATTR9]]
// CHECK5-NEXT: unreachable // CHECK5-NEXT: unreachable
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
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// CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 }
// CHECK5-NEXT: catch ptr null // CHECK5-NEXT: catch ptr null
// CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0
// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: unreachable // CHECK5-NEXT: unreachable
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { // CHECK5-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @__tgt_register_requires(i64 1) // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //

clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done9: // CHECK1: arraydestroy.done9:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK5: arraydestroy.done17: // CHECK5: arraydestroy.done17:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP11]] // CHECK5-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK2-NEXT: ret i32 [[CALL]] // CHECK2-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK9-NEXT: ret i32 [[CALL]] // CHECK9-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_distribute_simd_codegen.cpp

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// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK17-NEXT: ret i32 [[CALL]] // CHECK17-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK21-NEXT: ret i32 [[CALL]] // CHECK21-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK21-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK21-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK21-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 // CHECK21-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
// CHECK21-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK21-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
// CHECK21-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK21-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK21-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK25-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK25-NEXT: ret i32 [[CALL]] // CHECK25-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK25-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK25-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK25-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK25-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK25-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK29-SAME: () #[[ATTR0:[0-9]+]] { // CHECK29-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK29-NEXT: entry: // CHECK29-NEXT: entry:
// CHECK29-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK29-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK29-NEXT: ret i32 [[CALL]] // CHECK29-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK29-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK29-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK29-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK29-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK29-NEXT: entry: // CHECK29-NEXT: entry:
// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK1-NEXT: ret i32 [[CALL]] // CHECK1-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x ptr], align 8
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
// CHECK5-NEXT: ret i32 [[CALL]] // CHECK5-NEXT: ret i32 [[CALL]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done12: // CHECK1: arraydestroy.done12:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP36]] // CHECK1-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: store i32 0, ptr [[B]], align 4 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done13: // CHECK1: arraydestroy.done13:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]]) // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK5: arraydestroy.done6: // CHECK5: arraydestroy.done6:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP13]] // CHECK5-NEXT: ret i32 [[TMP13]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
Show All 15 Lines

clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9-NEXT: ret i32 [[TMP41]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done15: // CHECK9: arraydestroy.done15:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done2: // CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP36]] // CHECK9-NEXT: ret i32 [[TMP36]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done14: // CHECK9: arraydestroy.done14:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]]
// CHECK13: arraydestroy.done21: // CHECK13: arraydestroy.done21:
// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP19]] // CHECK13-NEXT: ret i32 [[TMP19]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]]
// CHECK13: arraydestroy.done20: // CHECK13: arraydestroy.done20:
// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP18]] // CHECK13-NEXT: ret i32 [[TMP18]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 // CHECK13-NEXT: store i32 0, ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@main // CHECK15-LABEL: define {{[^@]+}}@main
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clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp

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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done1: // CHECK1: arraydestroy.done1:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done2: // CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP16]] // CHECK1-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done8: // CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
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// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-SAME: () #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
// CHECK5: arraydestroy.done17: // CHECK5: arraydestroy.done17:
// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK5-NEXT: ret i32 [[TMP11]] // CHECK5-NEXT: ret i32 [[TMP11]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
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// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK9-SAME: () #[[ATTR0]] { // CHECK9-SAME: () #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
// CHECK11-SAME: () #[[ATTR0]] { // CHECK11-SAME: () #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
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// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK11-NEXT: ret i32 0 // CHECK11-NEXT: ret i32 0
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
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clang/test/OpenMP/teams_firstprivate_codegen.cpp

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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP59]] // CHECK9-NEXT: ret i32 [[TMP59]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK9-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP54]] // CHECK9-NEXT: ret i32 [[TMP54]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[A]], align 4 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4
// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
// CHECK9-NEXT: store i32 0, ptr [[B]], align 4 // CHECK9-NEXT: store i32 0, ptr [[B]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done8: // CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]]) // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]])
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP13]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg
// CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
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clang/test/OpenMP/teams_private_codegen.cpp

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// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
// CHECK1-NEXT: ret i32 0 // CHECK1-NEXT: ret i32 0
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
// CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
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// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK9-NEXT: call void @_ZN2SSC2ERi(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done3: // CHECK9: arraydestroy.done3:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done1: // CHECK9: arraydestroy.done1:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP16]] // CHECK9-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
// CHECK9-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 // CHECK9-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
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// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK9: arraydestroy.done3: // CHECK9: arraydestroy.done3:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 // CHECK9-NEXT: store i32 0, ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK9-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK9-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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