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Differential D146488

[RISCV] Move compressible registers to the beginning of the FP allocation order.
ClosedPublic

Authored by craig.topper on Mar 20 2023, 6:11 PM.

Details

Reviewers
asb
luismarques
reames
kito-cheng
frasercrmck
Commits
rG7b0c41841eb7: [RISCV] Move compressible registers to the beginning of the FP allocation order.
Summary

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register to be f8-f15.

This patch changes the FP allocation order to prioritize f10-f15 first.
These are also the FP argument registers. So I allocated them in reverse
order starting at f15 to avoid taking the first argument registers.
This appears to match gcc allocation order.

Diff Detail

Event Timeline

craig.topper created this revision.Mar 20 2023, 6:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 20 2023, 6:11 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 26 others. · View Herald Transcript
craig.topper requested review of this revision.Mar 20 2023, 6:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 20 2023, 6:11 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B220601: Diff 506811.Mar 20 2023, 7:25 PM
• pcwang-thead mentioned this in D122209: [RISCV] Allocate argument floating-point registers first.Mar 20 2023, 7:41 PM
• pcwang-thead added a comment.Mar 20 2023, 8:22 PM

Vote +1 from me. Thanks!
Performance and code size should have some improvements according to my previous assessment in D118020.

asb accepted this revision.EditedMar 27 2023, 2:29 AM

I can't say I've done any real performance analysis (I think the analysis from the previous thread should still be valid), but this seems sensible to me and I didn't spot any obvious regressions from kicking the tires.

This revision is now accepted and ready to land.Mar 27 2023, 2:29 AM
Closed by commit rG7b0c41841eb7: [RISCV] Move compressible registers to the beginning of the FP allocation order. (authored by craig.topper). · Explain WhyMar 27 2023, 5:30 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG7b0c41841eb7: [RISCV] Move compressible registers to the beginning of the FP allocation order..
wangpc mentioned this in D154837: [RISCV] Simplify the definitions of interrupt CSRs.Jul 10 2023, 5:31 AM
wangpc mentioned this in rG99809f43779f: [RISCV] Simplify the definitions of interrupt CSRs.Jul 10 2023, 8:21 PM
wangpc mentioned this in D118020: [RISCV] Set CostPerUse for floating point registers.Jul 13 2023, 7:50 PM

Large Diff

This large diff affects 118 files. Files without inline comments have been collapsed. Expand All Files

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Diff 508855

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

llvm/test/CodeGen/RISCV/calling-conv-half.ll

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

llvm/test/CodeGen/RISCV/copysign-casts.ll

llvm/test/CodeGen/RISCV/double-arith-strict.ll

llvm/test/CodeGen/RISCV/double-arith.ll

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

llvm/test/CodeGen/RISCV/double-calling-conv.ll

llvm/test/CodeGen/RISCV/double-convert-strict.ll

llvm/test/CodeGen/RISCV/double-convert.ll

llvm/test/CodeGen/RISCV/double-imm.ll

llvm/test/CodeGen/RISCV/double-intrinsics.ll

llvm/test/CodeGen/RISCV/double-mem.ll

llvm/test/CodeGen/RISCV/double-previous-failure.ll

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

llvm/test/CodeGen/RISCV/double-round-conv.ll

llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

llvm/test/CodeGen/RISCV/double_reduct.ll

llvm/test/CodeGen/RISCV/float-arith-strict.ll

llvm/test/CodeGen/RISCV/float-arith.ll

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

llvm/test/CodeGen/RISCV/float-convert-strict.ll

llvm/test/CodeGen/RISCV/float-convert.ll

llvm/test/CodeGen/RISCV/float-imm.ll

llvm/test/CodeGen/RISCV/float-intrinsics.ll

llvm/test/CodeGen/RISCV/float-mem.ll

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

llvm/test/CodeGen/RISCV/float-round-conv.ll

llvm/test/CodeGen/RISCV/fp-imm.ll

llvm/test/CodeGen/RISCV/half-arith-strict.ll

llvm/test/CodeGen/RISCV/half-arith.ll

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

llvm/test/CodeGen/RISCV/half-convert-strict.ll

llvm/test/CodeGen/RISCV/half-convert.ll

llvm/test/CodeGen/RISCV/half-fcmp.ll

llvm/test/CodeGen/RISCV/half-imm.ll

llvm/test/CodeGen/RISCV/half-intrinsics.ll

llvm/test/CodeGen/RISCV/half-isnan.ll

llvm/test/CodeGen/RISCV/half-mem.ll

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

llvm/test/CodeGen/RISCV/half-round-conv.ll

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

llvm/test/CodeGen/RISCV/half-select-icmp.ll

llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll

llvm/test/CodeGen/RISCV/libcall-tail-calls.ll

llvm/test/CodeGen/RISCV/machine-combiner.ll

llvm/test/CodeGen/RISCV/machine-cse.ll

llvm/test/CodeGen/RISCV/make-compressible.mir

llvm/test/CodeGen/RISCV/module-target-abi.ll

llvm/test/CodeGen/RISCV/repeated-fp-divisors.ll

llvm/test/CodeGen/RISCV/rv64f-float-convert.ll

llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll

llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll

llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll

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llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll

llvm/test/CodeGen/RISCV/vararg.ll

llvm/test/CodeGen/RISCV/xtheadfmemidx.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll