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Differential D122209

[RISCV] Allocate argument floating-point registers first
AbandonedPublic

Authored by • pcwang-thead on Mar 21 2022, 10:51 PM.

Details

Reviewers
asb
craig.topper
Summary

Performance and code size have some mild improvements.

Diff Detail

Event Timeline

• pcwang-thead created this revision.Mar 21 2022, 10:51 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 21 2022, 10:51 PM
Herald added subscribers: • s, VincentWu, luke957 and 29 others. · View Herald Transcript
• pcwang-thead requested review of this revision.Mar 21 2022, 10:51 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 21 2022, 10:51 PM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
• pcwang-thead mentioned this in D118020: [RISCV] Set CostPerUse for floating point registers.Mar 21 2022, 11:01 PM
• pcwang-thead updated this revision to Diff 417193.Mar 21 2022, 11:03 PM

Fix typo.

• pcwang-thead edited the summary of this revision. (Show Details)Mar 21 2022, 11:04 PM
Harbormaster completed remote builds in B155565: Diff 417193.Mar 21 2022, 11:51 PM
• pcwang-thead abandoned this revision.Mar 20 2023, 7:41 PM

See D146488.

Herald added subscribers: jobnoorman, luke, shiva0217. · View Herald TranscriptMar 20 2023, 7:41 PM
craig.topper added a comment.Mar 20 2023, 7:52 PM

I had forgotten we had this patch pending. Sorry @pcwang-thead

• pcwang-thead added a comment.Mar 20 2023, 8:14 PM
In D122209#4208514, @craig.topper wrote:

I had forgotten we had this patch pending. Sorry @pcwang-thead

Not a big deal. :-)
I think you have done it further.

Revision Contents

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Diff 417193

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Lines foreach Index = 0-31 in {
def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
DwarfRegNum<[!add(Index, 32)]>; DwarfRegNum<[!add(Index, 32)]>;
} }
} }
// The order of registers represents the preferred allocation sequence, // The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save. // meaning caller-save regs are listed before callee-save.
def FPR16 : RegisterClass<"RISCV", [f16], 16, (add def FPR16 : RegisterClass<"RISCV", [f16], 16, (add
(sequence "F%u_H", 0, 7),
(sequence "F%u_H", 10, 17), (sequence "F%u_H", 10, 17),
(sequence "F%u_H", 0, 7),
(sequence "F%u_H", 28, 31), (sequence "F%u_H", 28, 31),
(sequence "F%u_H", 8, 9), (sequence "F%u_H", 8, 9),
(sequence "F%u_H", 18, 27) (sequence "F%u_H", 18, 27)
)>; )>;
def FPR32 : RegisterClass<"RISCV", [f32], 32, (add def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
(sequence "F%u_F", 0, 7),
(sequence "F%u_F", 10, 17), (sequence "F%u_F", 10, 17),
(sequence "F%u_F", 0, 7),
(sequence "F%u_F", 28, 31), (sequence "F%u_F", 28, 31),
(sequence "F%u_F", 8, 9), (sequence "F%u_F", 8, 9),
(sequence "F%u_F", 18, 27) (sequence "F%u_F", 18, 27)
)>; )>;
def FPR32C : RegisterClass<"RISCV", [f32], 32, (add def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
(sequence "F%u_F", 10, 15), (sequence "F%u_F", 10, 15),
(sequence "F%u_F", 8, 9) (sequence "F%u_F", 8, 9)
)>; )>;
// The order of registers represents the preferred allocation sequence, // The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save. // meaning caller-save regs are listed before callee-save.
def FPR64 : RegisterClass<"RISCV", [f64], 64, (add def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
(sequence "F%u_D", 0, 7),
(sequence "F%u_D", 10, 17), (sequence "F%u_D", 10, 17),
(sequence "F%u_D", 0, 7),
(sequence "F%u_D", 28, 31), (sequence "F%u_D", 28, 31),
(sequence "F%u_D", 8, 9), (sequence "F%u_D", 8, 9),
(sequence "F%u_D", 18, 27) (sequence "F%u_D", 18, 27)
)>; )>;
def FPR64C : RegisterClass<"RISCV", [f64], 64, (add def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
(sequence "F%u_D", 10, 15), (sequence "F%u_D", 10, 15),
(sequence "F%u_D", 8, 9) (sequence "F%u_D", 8, 9)
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

Show All 18 Lines
; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
; something appropriate. ; something appropriate.
define void @callee() nounwind { define void @callee() nounwind {
; ILP32-LABEL: callee: ; ILP32-LABEL: callee:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var) ; ILP32-NEXT: lui a0, %hi(var)
; ILP32-NEXT: flw ft0, %lo(var)(a0) ; ILP32-NEXT: flw fa0, %lo(var)(a0)
; ILP32-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32-NEXT: flw fa1, %lo(var+4)(a0)
; ILP32-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32-NEXT: flw fa2, %lo(var+8)(a0)
; ILP32-NEXT: flw ft3, %lo(var+12)(a0) ; ILP32-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32-NEXT: addi a1, a0, %lo(var) ; ILP32-NEXT: addi a1, a0, %lo(var)
; ILP32-NEXT: flw ft4, 16(a1) ; ILP32-NEXT: flw fa4, 16(a1)
; ILP32-NEXT: flw ft5, 20(a1) ; ILP32-NEXT: flw fa5, 20(a1)
; ILP32-NEXT: flw ft6, 24(a1) ; ILP32-NEXT: flw fa6, 24(a1)
; ILP32-NEXT: flw ft7, 28(a1) ; ILP32-NEXT: flw fa7, 28(a1)
; ILP32-NEXT: flw fa0, 32(a1) ; ILP32-NEXT: flw ft0, 32(a1)
; ILP32-NEXT: flw fa1, 36(a1) ; ILP32-NEXT: flw ft1, 36(a1)
; ILP32-NEXT: flw fa2, 40(a1) ; ILP32-NEXT: flw ft2, 40(a1)
; ILP32-NEXT: flw fa3, 44(a1) ; ILP32-NEXT: flw ft3, 44(a1)
; ILP32-NEXT: flw fa4, 48(a1) ; ILP32-NEXT: flw ft4, 48(a1)
; ILP32-NEXT: flw fa5, 52(a1) ; ILP32-NEXT: flw ft5, 52(a1)
; ILP32-NEXT: flw fa6, 56(a1) ; ILP32-NEXT: flw ft6, 56(a1)
; ILP32-NEXT: flw fa7, 60(a1) ; ILP32-NEXT: flw ft7, 60(a1)
; ILP32-NEXT: flw ft8, 64(a1) ; ILP32-NEXT: flw ft8, 64(a1)
; ILP32-NEXT: flw ft9, 68(a1) ; ILP32-NEXT: flw ft9, 68(a1)
; ILP32-NEXT: flw ft10, 72(a1) ; ILP32-NEXT: flw ft10, 72(a1)
; ILP32-NEXT: flw ft11, 76(a1) ; ILP32-NEXT: flw ft11, 76(a1)
; ILP32-NEXT: flw fs0, 80(a1) ; ILP32-NEXT: flw fs0, 80(a1)
; ILP32-NEXT: flw fs1, 84(a1) ; ILP32-NEXT: flw fs1, 84(a1)
; ILP32-NEXT: flw fs2, 88(a1) ; ILP32-NEXT: flw fs2, 88(a1)
; ILP32-NEXT: flw fs3, 92(a1) ; ILP32-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; ILP32-NEXT: fsw fs3, 92(a1) ; ILP32-NEXT: fsw fs3, 92(a1)
; ILP32-NEXT: fsw fs2, 88(a1) ; ILP32-NEXT: fsw fs2, 88(a1)
; ILP32-NEXT: fsw fs1, 84(a1) ; ILP32-NEXT: fsw fs1, 84(a1)
; ILP32-NEXT: fsw fs0, 80(a1) ; ILP32-NEXT: fsw fs0, 80(a1)
; ILP32-NEXT: fsw ft11, 76(a1) ; ILP32-NEXT: fsw ft11, 76(a1)
; ILP32-NEXT: fsw ft10, 72(a1) ; ILP32-NEXT: fsw ft10, 72(a1)
; ILP32-NEXT: fsw ft9, 68(a1) ; ILP32-NEXT: fsw ft9, 68(a1)
; ILP32-NEXT: fsw ft8, 64(a1) ; ILP32-NEXT: fsw ft8, 64(a1)
; ILP32-NEXT: fsw fa7, 60(a1) ; ILP32-NEXT: fsw ft7, 60(a1)
; ILP32-NEXT: fsw fa6, 56(a1) ; ILP32-NEXT: fsw ft6, 56(a1)
; ILP32-NEXT: fsw fa5, 52(a1) ; ILP32-NEXT: fsw ft5, 52(a1)
; ILP32-NEXT: fsw fa4, 48(a1) ; ILP32-NEXT: fsw ft4, 48(a1)
; ILP32-NEXT: fsw fa3, 44(a1) ; ILP32-NEXT: fsw ft3, 44(a1)
; ILP32-NEXT: fsw fa2, 40(a1) ; ILP32-NEXT: fsw ft2, 40(a1)
; ILP32-NEXT: fsw fa1, 36(a1) ; ILP32-NEXT: fsw ft1, 36(a1)
; ILP32-NEXT: fsw fa0, 32(a1) ; ILP32-NEXT: fsw ft0, 32(a1)
; ILP32-NEXT: fsw ft7, 28(a1) ; ILP32-NEXT: fsw fa7, 28(a1)
; ILP32-NEXT: fsw ft6, 24(a1) ; ILP32-NEXT: fsw fa6, 24(a1)
; ILP32-NEXT: fsw ft5, 20(a1) ; ILP32-NEXT: fsw fa5, 20(a1)
; ILP32-NEXT: fsw ft4, 16(a1) ; ILP32-NEXT: fsw fa4, 16(a1)
; ILP32-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32-NEXT: fsw fa3, %lo(var+12)(a0)
; ILP32-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32-NEXT: fsw fa2, %lo(var+8)(a0)
; ILP32-NEXT: fsw ft1, %lo(var+4)(a0) ; ILP32-NEXT: fsw fa1, %lo(var+4)(a0)
; ILP32-NEXT: fsw ft0, %lo(var)(a0) ; ILP32-NEXT: fsw fa0, %lo(var)(a0)
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: callee: ; LP64-LABEL: callee:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var) ; LP64-NEXT: lui a0, %hi(var)
; LP64-NEXT: flw ft0, %lo(var)(a0) ; LP64-NEXT: flw fa0, %lo(var)(a0)
; LP64-NEXT: flw ft1, %lo(var+4)(a0) ; LP64-NEXT: flw fa1, %lo(var+4)(a0)
; LP64-NEXT: flw ft2, %lo(var+8)(a0) ; LP64-NEXT: flw fa2, %lo(var+8)(a0)
; LP64-NEXT: flw ft3, %lo(var+12)(a0) ; LP64-NEXT: flw fa3, %lo(var+12)(a0)
; LP64-NEXT: addi a1, a0, %lo(var) ; LP64-NEXT: addi a1, a0, %lo(var)
; LP64-NEXT: flw ft4, 16(a1) ; LP64-NEXT: flw fa4, 16(a1)
; LP64-NEXT: flw ft5, 20(a1) ; LP64-NEXT: flw fa5, 20(a1)
; LP64-NEXT: flw ft6, 24(a1) ; LP64-NEXT: flw fa6, 24(a1)
; LP64-NEXT: flw ft7, 28(a1) ; LP64-NEXT: flw fa7, 28(a1)
; LP64-NEXT: flw fa0, 32(a1) ; LP64-NEXT: flw ft0, 32(a1)
; LP64-NEXT: flw fa1, 36(a1) ; LP64-NEXT: flw ft1, 36(a1)
; LP64-NEXT: flw fa2, 40(a1) ; LP64-NEXT: flw ft2, 40(a1)
; LP64-NEXT: flw fa3, 44(a1) ; LP64-NEXT: flw ft3, 44(a1)
; LP64-NEXT: flw fa4, 48(a1) ; LP64-NEXT: flw ft4, 48(a1)
; LP64-NEXT: flw fa5, 52(a1) ; LP64-NEXT: flw ft5, 52(a1)
; LP64-NEXT: flw fa6, 56(a1) ; LP64-NEXT: flw ft6, 56(a1)
; LP64-NEXT: flw fa7, 60(a1) ; LP64-NEXT: flw ft7, 60(a1)
; LP64-NEXT: flw ft8, 64(a1) ; LP64-NEXT: flw ft8, 64(a1)
; LP64-NEXT: flw ft9, 68(a1) ; LP64-NEXT: flw ft9, 68(a1)
; LP64-NEXT: flw ft10, 72(a1) ; LP64-NEXT: flw ft10, 72(a1)
; LP64-NEXT: flw ft11, 76(a1) ; LP64-NEXT: flw ft11, 76(a1)
; LP64-NEXT: flw fs0, 80(a1) ; LP64-NEXT: flw fs0, 80(a1)
; LP64-NEXT: flw fs1, 84(a1) ; LP64-NEXT: flw fs1, 84(a1)
; LP64-NEXT: flw fs2, 88(a1) ; LP64-NEXT: flw fs2, 88(a1)
; LP64-NEXT: flw fs3, 92(a1) ; LP64-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; LP64-NEXT: fsw fs3, 92(a1) ; LP64-NEXT: fsw fs3, 92(a1)
; LP64-NEXT: fsw fs2, 88(a1) ; LP64-NEXT: fsw fs2, 88(a1)
; LP64-NEXT: fsw fs1, 84(a1) ; LP64-NEXT: fsw fs1, 84(a1)
; LP64-NEXT: fsw fs0, 80(a1) ; LP64-NEXT: fsw fs0, 80(a1)
; LP64-NEXT: fsw ft11, 76(a1) ; LP64-NEXT: fsw ft11, 76(a1)
; LP64-NEXT: fsw ft10, 72(a1) ; LP64-NEXT: fsw ft10, 72(a1)
; LP64-NEXT: fsw ft9, 68(a1) ; LP64-NEXT: fsw ft9, 68(a1)
; LP64-NEXT: fsw ft8, 64(a1) ; LP64-NEXT: fsw ft8, 64(a1)
; LP64-NEXT: fsw fa7, 60(a1) ; LP64-NEXT: fsw ft7, 60(a1)
; LP64-NEXT: fsw fa6, 56(a1) ; LP64-NEXT: fsw ft6, 56(a1)
; LP64-NEXT: fsw fa5, 52(a1) ; LP64-NEXT: fsw ft5, 52(a1)
; LP64-NEXT: fsw fa4, 48(a1) ; LP64-NEXT: fsw ft4, 48(a1)
; LP64-NEXT: fsw fa3, 44(a1) ; LP64-NEXT: fsw ft3, 44(a1)
; LP64-NEXT: fsw fa2, 40(a1) ; LP64-NEXT: fsw ft2, 40(a1)
; LP64-NEXT: fsw fa1, 36(a1) ; LP64-NEXT: fsw ft1, 36(a1)
; LP64-NEXT: fsw fa0, 32(a1) ; LP64-NEXT: fsw ft0, 32(a1)
; LP64-NEXT: fsw ft7, 28(a1) ; LP64-NEXT: fsw fa7, 28(a1)
; LP64-NEXT: fsw ft6, 24(a1) ; LP64-NEXT: fsw fa6, 24(a1)
; LP64-NEXT: fsw ft5, 20(a1) ; LP64-NEXT: fsw fa5, 20(a1)
; LP64-NEXT: fsw ft4, 16(a1) ; LP64-NEXT: fsw fa4, 16(a1)
; LP64-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64-NEXT: fsw fa3, %lo(var+12)(a0)
; LP64-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64-NEXT: fsw fa2, %lo(var+8)(a0)
; LP64-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64-NEXT: fsw fa1, %lo(var+4)(a0)
; LP64-NEXT: fsw ft0, %lo(var)(a0) ; LP64-NEXT: fsw fa0, %lo(var)(a0)
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32F-LABEL: callee: ; ILP32F-LABEL: callee:
; ILP32F: # %bb.0: ; ILP32F: # %bb.0:
; ILP32F-NEXT: addi sp, sp, -48 ; ILP32F-NEXT: addi sp, sp, -48
; ILP32F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui a0, %hi(var) ; ILP32F-NEXT: lui a0, %hi(var)
; ILP32F-NEXT: flw ft0, %lo(var)(a0) ; ILP32F-NEXT: flw fa0, %lo(var)(a0)
; ILP32F-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32F-NEXT: flw fa1, %lo(var+4)(a0)
; ILP32F-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: flw fa2, %lo(var+8)(a0)
; ILP32F-NEXT: flw ft3, %lo(var+12)(a0) ; ILP32F-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32F-NEXT: addi a1, a0, %lo(var) ; ILP32F-NEXT: addi a1, a0, %lo(var)
; ILP32F-NEXT: flw ft4, 16(a1) ; ILP32F-NEXT: flw fa4, 16(a1)
; ILP32F-NEXT: flw ft5, 20(a1) ; ILP32F-NEXT: flw fa5, 20(a1)
; ILP32F-NEXT: flw ft6, 24(a1) ; ILP32F-NEXT: flw fa6, 24(a1)
; ILP32F-NEXT: flw ft7, 28(a1) ; ILP32F-NEXT: flw fa7, 28(a1)
; ILP32F-NEXT: flw fa0, 32(a1) ; ILP32F-NEXT: flw ft0, 32(a1)
; ILP32F-NEXT: flw fa1, 36(a1) ; ILP32F-NEXT: flw ft1, 36(a1)
; ILP32F-NEXT: flw fa2, 40(a1) ; ILP32F-NEXT: flw ft2, 40(a1)
; ILP32F-NEXT: flw fa3, 44(a1) ; ILP32F-NEXT: flw ft3, 44(a1)
; ILP32F-NEXT: flw fa4, 48(a1) ; ILP32F-NEXT: flw ft4, 48(a1)
; ILP32F-NEXT: flw fa5, 52(a1) ; ILP32F-NEXT: flw ft5, 52(a1)
; ILP32F-NEXT: flw fa6, 56(a1) ; ILP32F-NEXT: flw ft6, 56(a1)
; ILP32F-NEXT: flw fa7, 60(a1) ; ILP32F-NEXT: flw ft7, 60(a1)
; ILP32F-NEXT: flw ft8, 64(a1) ; ILP32F-NEXT: flw ft8, 64(a1)
; ILP32F-NEXT: flw ft9, 68(a1) ; ILP32F-NEXT: flw ft9, 68(a1)
; ILP32F-NEXT: flw ft10, 72(a1) ; ILP32F-NEXT: flw ft10, 72(a1)
; ILP32F-NEXT: flw ft11, 76(a1) ; ILP32F-NEXT: flw ft11, 76(a1)
; ILP32F-NEXT: flw fs0, 80(a1) ; ILP32F-NEXT: flw fs0, 80(a1)
; ILP32F-NEXT: flw fs1, 84(a1) ; ILP32F-NEXT: flw fs1, 84(a1)
; ILP32F-NEXT: flw fs2, 88(a1) ; ILP32F-NEXT: flw fs2, 88(a1)
; ILP32F-NEXT: flw fs3, 92(a1) ; ILP32F-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; ILP32F-NEXT: fsw fs3, 92(a1) ; ILP32F-NEXT: fsw fs3, 92(a1)
; ILP32F-NEXT: fsw fs2, 88(a1) ; ILP32F-NEXT: fsw fs2, 88(a1)
; ILP32F-NEXT: fsw fs1, 84(a1) ; ILP32F-NEXT: fsw fs1, 84(a1)
; ILP32F-NEXT: fsw fs0, 80(a1) ; ILP32F-NEXT: fsw fs0, 80(a1)
; ILP32F-NEXT: fsw ft11, 76(a1) ; ILP32F-NEXT: fsw ft11, 76(a1)
; ILP32F-NEXT: fsw ft10, 72(a1) ; ILP32F-NEXT: fsw ft10, 72(a1)
; ILP32F-NEXT: fsw ft9, 68(a1) ; ILP32F-NEXT: fsw ft9, 68(a1)
; ILP32F-NEXT: fsw ft8, 64(a1) ; ILP32F-NEXT: fsw ft8, 64(a1)
; ILP32F-NEXT: fsw fa7, 60(a1) ; ILP32F-NEXT: fsw ft7, 60(a1)
; ILP32F-NEXT: fsw fa6, 56(a1) ; ILP32F-NEXT: fsw ft6, 56(a1)
; ILP32F-NEXT: fsw fa5, 52(a1) ; ILP32F-NEXT: fsw ft5, 52(a1)
; ILP32F-NEXT: fsw fa4, 48(a1) ; ILP32F-NEXT: fsw ft4, 48(a1)
; ILP32F-NEXT: fsw fa3, 44(a1) ; ILP32F-NEXT: fsw ft3, 44(a1)
; ILP32F-NEXT: fsw fa2, 40(a1) ; ILP32F-NEXT: fsw ft2, 40(a1)
; ILP32F-NEXT: fsw fa1, 36(a1) ; ILP32F-NEXT: fsw ft1, 36(a1)
; ILP32F-NEXT: fsw fa0, 32(a1) ; ILP32F-NEXT: fsw ft0, 32(a1)
; ILP32F-NEXT: fsw ft7, 28(a1) ; ILP32F-NEXT: fsw fa7, 28(a1)
; ILP32F-NEXT: fsw ft6, 24(a1) ; ILP32F-NEXT: fsw fa6, 24(a1)
; ILP32F-NEXT: fsw ft5, 20(a1) ; ILP32F-NEXT: fsw fa5, 20(a1)
; ILP32F-NEXT: fsw ft4, 16(a1) ; ILP32F-NEXT: fsw fa4, 16(a1)
; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32F-NEXT: fsw fa3, %lo(var+12)(a0)
; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: fsw fa2, %lo(var+8)(a0)
; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0) ; ILP32F-NEXT: fsw fa1, %lo(var+4)(a0)
; ILP32F-NEXT: fsw ft0, %lo(var)(a0) ; ILP32F-NEXT: fsw fa0, %lo(var)(a0)
; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
Show All 15 Lines
; LP64F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui a0, %hi(var) ; LP64F-NEXT: lui a0, %hi(var)
; LP64F-NEXT: flw ft0, %lo(var)(a0) ; LP64F-NEXT: flw fa0, %lo(var)(a0)
; LP64F-NEXT: flw ft1, %lo(var+4)(a0) ; LP64F-NEXT: flw fa1, %lo(var+4)(a0)
; LP64F-NEXT: flw ft2, %lo(var+8)(a0) ; LP64F-NEXT: flw fa2, %lo(var+8)(a0)
; LP64F-NEXT: flw ft3, %lo(var+12)(a0) ; LP64F-NEXT: flw fa3, %lo(var+12)(a0)
; LP64F-NEXT: addi a1, a0, %lo(var) ; LP64F-NEXT: addi a1, a0, %lo(var)
; LP64F-NEXT: flw ft4, 16(a1) ; LP64F-NEXT: flw fa4, 16(a1)
; LP64F-NEXT: flw ft5, 20(a1) ; LP64F-NEXT: flw fa5, 20(a1)
; LP64F-NEXT: flw ft6, 24(a1) ; LP64F-NEXT: flw fa6, 24(a1)
; LP64F-NEXT: flw ft7, 28(a1) ; LP64F-NEXT: flw fa7, 28(a1)
; LP64F-NEXT: flw fa0, 32(a1) ; LP64F-NEXT: flw ft0, 32(a1)
; LP64F-NEXT: flw fa1, 36(a1) ; LP64F-NEXT: flw ft1, 36(a1)
; LP64F-NEXT: flw fa2, 40(a1) ; LP64F-NEXT: flw ft2, 40(a1)
; LP64F-NEXT: flw fa3, 44(a1) ; LP64F-NEXT: flw ft3, 44(a1)
; LP64F-NEXT: flw fa4, 48(a1) ; LP64F-NEXT: flw ft4, 48(a1)
; LP64F-NEXT: flw fa5, 52(a1) ; LP64F-NEXT: flw ft5, 52(a1)
; LP64F-NEXT: flw fa6, 56(a1) ; LP64F-NEXT: flw ft6, 56(a1)
; LP64F-NEXT: flw fa7, 60(a1) ; LP64F-NEXT: flw ft7, 60(a1)
; LP64F-NEXT: flw ft8, 64(a1) ; LP64F-NEXT: flw ft8, 64(a1)
; LP64F-NEXT: flw ft9, 68(a1) ; LP64F-NEXT: flw ft9, 68(a1)
; LP64F-NEXT: flw ft10, 72(a1) ; LP64F-NEXT: flw ft10, 72(a1)
; LP64F-NEXT: flw ft11, 76(a1) ; LP64F-NEXT: flw ft11, 76(a1)
; LP64F-NEXT: flw fs0, 80(a1) ; LP64F-NEXT: flw fs0, 80(a1)
; LP64F-NEXT: flw fs1, 84(a1) ; LP64F-NEXT: flw fs1, 84(a1)
; LP64F-NEXT: flw fs2, 88(a1) ; LP64F-NEXT: flw fs2, 88(a1)
; LP64F-NEXT: flw fs3, 92(a1) ; LP64F-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; LP64F-NEXT: fsw fs3, 92(a1) ; LP64F-NEXT: fsw fs3, 92(a1)
; LP64F-NEXT: fsw fs2, 88(a1) ; LP64F-NEXT: fsw fs2, 88(a1)
; LP64F-NEXT: fsw fs1, 84(a1) ; LP64F-NEXT: fsw fs1, 84(a1)
; LP64F-NEXT: fsw fs0, 80(a1) ; LP64F-NEXT: fsw fs0, 80(a1)
; LP64F-NEXT: fsw ft11, 76(a1) ; LP64F-NEXT: fsw ft11, 76(a1)
; LP64F-NEXT: fsw ft10, 72(a1) ; LP64F-NEXT: fsw ft10, 72(a1)
; LP64F-NEXT: fsw ft9, 68(a1) ; LP64F-NEXT: fsw ft9, 68(a1)
; LP64F-NEXT: fsw ft8, 64(a1) ; LP64F-NEXT: fsw ft8, 64(a1)
; LP64F-NEXT: fsw fa7, 60(a1) ; LP64F-NEXT: fsw ft7, 60(a1)
; LP64F-NEXT: fsw fa6, 56(a1) ; LP64F-NEXT: fsw ft6, 56(a1)
; LP64F-NEXT: fsw fa5, 52(a1) ; LP64F-NEXT: fsw ft5, 52(a1)
; LP64F-NEXT: fsw fa4, 48(a1) ; LP64F-NEXT: fsw ft4, 48(a1)
; LP64F-NEXT: fsw fa3, 44(a1) ; LP64F-NEXT: fsw ft3, 44(a1)
; LP64F-NEXT: fsw fa2, 40(a1) ; LP64F-NEXT: fsw ft2, 40(a1)
; LP64F-NEXT: fsw fa1, 36(a1) ; LP64F-NEXT: fsw ft1, 36(a1)
; LP64F-NEXT: fsw fa0, 32(a1) ; LP64F-NEXT: fsw ft0, 32(a1)
; LP64F-NEXT: fsw ft7, 28(a1) ; LP64F-NEXT: fsw fa7, 28(a1)
; LP64F-NEXT: fsw ft6, 24(a1) ; LP64F-NEXT: fsw fa6, 24(a1)
; LP64F-NEXT: fsw ft5, 20(a1) ; LP64F-NEXT: fsw fa5, 20(a1)
; LP64F-NEXT: fsw ft4, 16(a1) ; LP64F-NEXT: fsw fa4, 16(a1)
; LP64F-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64F-NEXT: fsw fa3, %lo(var+12)(a0)
; LP64F-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64F-NEXT: fsw fa2, %lo(var+8)(a0)
; LP64F-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64F-NEXT: fsw fa1, %lo(var+4)(a0)
; LP64F-NEXT: fsw ft0, %lo(var)(a0) ; LP64F-NEXT: fsw fa0, %lo(var)(a0)
; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
Show All 15 Lines
; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var) ; ILP32D-NEXT: lui a0, %hi(var)
; ILP32D-NEXT: flw ft0, %lo(var)(a0) ; ILP32D-NEXT: flw fa0, %lo(var)(a0)
; ILP32D-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32D-NEXT: flw fa1, %lo(var+4)(a0)
; ILP32D-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: flw fa2, %lo(var+8)(a0)
; ILP32D-NEXT: flw ft3, %lo(var+12)(a0) ; ILP32D-NEXT: flw fa3, %lo(var+12)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var) ; ILP32D-NEXT: addi a1, a0, %lo(var)
; ILP32D-NEXT: flw ft4, 16(a1) ; ILP32D-NEXT: flw fa4, 16(a1)
; ILP32D-NEXT: flw ft5, 20(a1) ; ILP32D-NEXT: flw fa5, 20(a1)
; ILP32D-NEXT: flw ft6, 24(a1) ; ILP32D-NEXT: flw fa6, 24(a1)
; ILP32D-NEXT: flw ft7, 28(a1) ; ILP32D-NEXT: flw fa7, 28(a1)
; ILP32D-NEXT: flw fa0, 32(a1) ; ILP32D-NEXT: flw ft0, 32(a1)
; ILP32D-NEXT: flw fa1, 36(a1) ; ILP32D-NEXT: flw ft1, 36(a1)
; ILP32D-NEXT: flw fa2, 40(a1) ; ILP32D-NEXT: flw ft2, 40(a1)
; ILP32D-NEXT: flw fa3, 44(a1) ; ILP32D-NEXT: flw ft3, 44(a1)
; ILP32D-NEXT: flw fa4, 48(a1) ; ILP32D-NEXT: flw ft4, 48(a1)
; ILP32D-NEXT: flw fa5, 52(a1) ; ILP32D-NEXT: flw ft5, 52(a1)
; ILP32D-NEXT: flw fa6, 56(a1) ; ILP32D-NEXT: flw ft6, 56(a1)
; ILP32D-NEXT: flw fa7, 60(a1) ; ILP32D-NEXT: flw ft7, 60(a1)
; ILP32D-NEXT: flw ft8, 64(a1) ; ILP32D-NEXT: flw ft8, 64(a1)
; ILP32D-NEXT: flw ft9, 68(a1) ; ILP32D-NEXT: flw ft9, 68(a1)
; ILP32D-NEXT: flw ft10, 72(a1) ; ILP32D-NEXT: flw ft10, 72(a1)
; ILP32D-NEXT: flw ft11, 76(a1) ; ILP32D-NEXT: flw ft11, 76(a1)
; ILP32D-NEXT: flw fs0, 80(a1) ; ILP32D-NEXT: flw fs0, 80(a1)
; ILP32D-NEXT: flw fs1, 84(a1) ; ILP32D-NEXT: flw fs1, 84(a1)
; ILP32D-NEXT: flw fs2, 88(a1) ; ILP32D-NEXT: flw fs2, 88(a1)
; ILP32D-NEXT: flw fs3, 92(a1) ; ILP32D-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; ILP32D-NEXT: fsw fs3, 92(a1) ; ILP32D-NEXT: fsw fs3, 92(a1)
; ILP32D-NEXT: fsw fs2, 88(a1) ; ILP32D-NEXT: fsw fs2, 88(a1)
; ILP32D-NEXT: fsw fs1, 84(a1) ; ILP32D-NEXT: fsw fs1, 84(a1)
; ILP32D-NEXT: fsw fs0, 80(a1) ; ILP32D-NEXT: fsw fs0, 80(a1)
; ILP32D-NEXT: fsw ft11, 76(a1) ; ILP32D-NEXT: fsw ft11, 76(a1)
; ILP32D-NEXT: fsw ft10, 72(a1) ; ILP32D-NEXT: fsw ft10, 72(a1)
; ILP32D-NEXT: fsw ft9, 68(a1) ; ILP32D-NEXT: fsw ft9, 68(a1)
; ILP32D-NEXT: fsw ft8, 64(a1) ; ILP32D-NEXT: fsw ft8, 64(a1)
; ILP32D-NEXT: fsw fa7, 60(a1) ; ILP32D-NEXT: fsw ft7, 60(a1)
; ILP32D-NEXT: fsw fa6, 56(a1) ; ILP32D-NEXT: fsw ft6, 56(a1)
; ILP32D-NEXT: fsw fa5, 52(a1) ; ILP32D-NEXT: fsw ft5, 52(a1)
; ILP32D-NEXT: fsw fa4, 48(a1) ; ILP32D-NEXT: fsw ft4, 48(a1)
; ILP32D-NEXT: fsw fa3, 44(a1) ; ILP32D-NEXT: fsw ft3, 44(a1)
; ILP32D-NEXT: fsw fa2, 40(a1) ; ILP32D-NEXT: fsw ft2, 40(a1)
; ILP32D-NEXT: fsw fa1, 36(a1) ; ILP32D-NEXT: fsw ft1, 36(a1)
; ILP32D-NEXT: fsw fa0, 32(a1) ; ILP32D-NEXT: fsw ft0, 32(a1)
; ILP32D-NEXT: fsw ft7, 28(a1) ; ILP32D-NEXT: fsw fa7, 28(a1)
; ILP32D-NEXT: fsw ft6, 24(a1) ; ILP32D-NEXT: fsw fa6, 24(a1)
; ILP32D-NEXT: fsw ft5, 20(a1) ; ILP32D-NEXT: fsw fa5, 20(a1)
; ILP32D-NEXT: fsw ft4, 16(a1) ; ILP32D-NEXT: fsw fa4, 16(a1)
; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32D-NEXT: fsw fa3, %lo(var+12)(a0)
; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: fsw fa2, %lo(var+8)(a0)
; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0) ; ILP32D-NEXT: fsw fa1, %lo(var+4)(a0)
; ILP32D-NEXT: fsw ft0, %lo(var)(a0) ; ILP32D-NEXT: fsw fa0, %lo(var)(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
Show All 15 Lines
; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var) ; LP64D-NEXT: lui a0, %hi(var)
; LP64D-NEXT: flw ft0, %lo(var)(a0) ; LP64D-NEXT: flw fa0, %lo(var)(a0)
; LP64D-NEXT: flw ft1, %lo(var+4)(a0) ; LP64D-NEXT: flw fa1, %lo(var+4)(a0)
; LP64D-NEXT: flw ft2, %lo(var+8)(a0) ; LP64D-NEXT: flw fa2, %lo(var+8)(a0)
; LP64D-NEXT: flw ft3, %lo(var+12)(a0) ; LP64D-NEXT: flw fa3, %lo(var+12)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var) ; LP64D-NEXT: addi a1, a0, %lo(var)
; LP64D-NEXT: flw ft4, 16(a1) ; LP64D-NEXT: flw fa4, 16(a1)
; LP64D-NEXT: flw ft5, 20(a1) ; LP64D-NEXT: flw fa5, 20(a1)
; LP64D-NEXT: flw ft6, 24(a1) ; LP64D-NEXT: flw fa6, 24(a1)
; LP64D-NEXT: flw ft7, 28(a1) ; LP64D-NEXT: flw fa7, 28(a1)
; LP64D-NEXT: flw fa0, 32(a1) ; LP64D-NEXT: flw ft0, 32(a1)
; LP64D-NEXT: flw fa1, 36(a1) ; LP64D-NEXT: flw ft1, 36(a1)
; LP64D-NEXT: flw fa2, 40(a1) ; LP64D-NEXT: flw ft2, 40(a1)
; LP64D-NEXT: flw fa3, 44(a1) ; LP64D-NEXT: flw ft3, 44(a1)
; LP64D-NEXT: flw fa4, 48(a1) ; LP64D-NEXT: flw ft4, 48(a1)
; LP64D-NEXT: flw fa5, 52(a1) ; LP64D-NEXT: flw ft5, 52(a1)
; LP64D-NEXT: flw fa6, 56(a1) ; LP64D-NEXT: flw ft6, 56(a1)
; LP64D-NEXT: flw fa7, 60(a1) ; LP64D-NEXT: flw ft7, 60(a1)
; LP64D-NEXT: flw ft8, 64(a1) ; LP64D-NEXT: flw ft8, 64(a1)
; LP64D-NEXT: flw ft9, 68(a1) ; LP64D-NEXT: flw ft9, 68(a1)
; LP64D-NEXT: flw ft10, 72(a1) ; LP64D-NEXT: flw ft10, 72(a1)
; LP64D-NEXT: flw ft11, 76(a1) ; LP64D-NEXT: flw ft11, 76(a1)
; LP64D-NEXT: flw fs0, 80(a1) ; LP64D-NEXT: flw fs0, 80(a1)
; LP64D-NEXT: flw fs1, 84(a1) ; LP64D-NEXT: flw fs1, 84(a1)
; LP64D-NEXT: flw fs2, 88(a1) ; LP64D-NEXT: flw fs2, 88(a1)
; LP64D-NEXT: flw fs3, 92(a1) ; LP64D-NEXT: flw fs3, 92(a1)
Show All 16 Lines
; LP64D-NEXT: fsw fs3, 92(a1) ; LP64D-NEXT: fsw fs3, 92(a1)
; LP64D-NEXT: fsw fs2, 88(a1) ; LP64D-NEXT: fsw fs2, 88(a1)
; LP64D-NEXT: fsw fs1, 84(a1) ; LP64D-NEXT: fsw fs1, 84(a1)
; LP64D-NEXT: fsw fs0, 80(a1) ; LP64D-NEXT: fsw fs0, 80(a1)
; LP64D-NEXT: fsw ft11, 76(a1) ; LP64D-NEXT: fsw ft11, 76(a1)
; LP64D-NEXT: fsw ft10, 72(a1) ; LP64D-NEXT: fsw ft10, 72(a1)
; LP64D-NEXT: fsw ft9, 68(a1) ; LP64D-NEXT: fsw ft9, 68(a1)
; LP64D-NEXT: fsw ft8, 64(a1) ; LP64D-NEXT: fsw ft8, 64(a1)
; LP64D-NEXT: fsw fa7, 60(a1) ; LP64D-NEXT: fsw ft7, 60(a1)
; LP64D-NEXT: fsw fa6, 56(a1) ; LP64D-NEXT: fsw ft6, 56(a1)
; LP64D-NEXT: fsw fa5, 52(a1) ; LP64D-NEXT: fsw ft5, 52(a1)
; LP64D-NEXT: fsw fa4, 48(a1) ; LP64D-NEXT: fsw ft4, 48(a1)
; LP64D-NEXT: fsw fa3, 44(a1) ; LP64D-NEXT: fsw ft3, 44(a1)
; LP64D-NEXT: fsw fa2, 40(a1) ; LP64D-NEXT: fsw ft2, 40(a1)
; LP64D-NEXT: fsw fa1, 36(a1) ; LP64D-NEXT: fsw ft1, 36(a1)
; LP64D-NEXT: fsw fa0, 32(a1) ; LP64D-NEXT: fsw ft0, 32(a1)
; LP64D-NEXT: fsw ft7, 28(a1) ; LP64D-NEXT: fsw fa7, 28(a1)
; LP64D-NEXT: fsw ft6, 24(a1) ; LP64D-NEXT: fsw fa6, 24(a1)
; LP64D-NEXT: fsw ft5, 20(a1) ; LP64D-NEXT: fsw fa5, 20(a1)
; LP64D-NEXT: fsw ft4, 16(a1) ; LP64D-NEXT: fsw fa4, 16(a1)
; LP64D-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64D-NEXT: fsw fa3, %lo(var+12)(a0)
; LP64D-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64D-NEXT: fsw fa2, %lo(var+8)(a0)
; LP64D-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64D-NEXT: fsw fa1, %lo(var+4)(a0)
; LP64D-NEXT: fsw ft0, %lo(var)(a0) ; LP64D-NEXT: fsw fa0, %lo(var)(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
Show All 18 Lines
define void @caller() nounwind { define void @caller() nounwind {
; ILP32-LABEL: caller: ; ILP32-LABEL: caller:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: addi sp, sp, -144 ; ILP32-NEXT: addi sp, sp, -144
; ILP32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var) ; ILP32-NEXT: lui s0, %hi(var)
; ILP32-NEXT: flw ft0, %lo(var)(s0) ; ILP32-NEXT: flw fa0, %lo(var)(s0)
; ILP32-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 128(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32-NEXT: flw fa0, %lo(var+4)(s0)
; ILP32-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 124(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32-NEXT: flw fa0, %lo(var+8)(s0)
; ILP32-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 120(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32-NEXT: flw fa0, %lo(var+12)(s0)
; ILP32-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 116(sp) # 4-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: addi s1, s0, %lo(var)
; ILP32-NEXT: flw ft0, 16(s1) ; ILP32-NEXT: flw fa0, 16(s1)
; ILP32-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 112(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 20(s1) ; ILP32-NEXT: flw fa0, 20(s1)
; ILP32-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 108(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 24(s1) ; ILP32-NEXT: flw fa0, 24(s1)
; ILP32-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 28(s1) ; ILP32-NEXT: flw fa0, 28(s1)
; ILP32-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 100(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 32(s1) ; ILP32-NEXT: flw fa0, 32(s1)
; ILP32-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 36(s1) ; ILP32-NEXT: flw fa0, 36(s1)
; ILP32-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 40(s1) ; ILP32-NEXT: flw fa0, 40(s1)
; ILP32-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 88(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 44(s1) ; ILP32-NEXT: flw fa0, 44(s1)
; ILP32-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 48(s1) ; ILP32-NEXT: flw fa0, 48(s1)
; ILP32-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 52(s1) ; ILP32-NEXT: flw fa0, 52(s1)
; ILP32-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 56(s1) ; ILP32-NEXT: flw fa0, 56(s1)
; ILP32-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 60(s1) ; ILP32-NEXT: flw fa0, 60(s1)
; ILP32-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 64(s1) ; ILP32-NEXT: flw fa0, 64(s1)
; ILP32-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 68(s1) ; ILP32-NEXT: flw fa0, 68(s1)
; ILP32-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 72(s1) ; ILP32-NEXT: flw fa0, 72(s1)
; ILP32-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 76(s1) ; ILP32-NEXT: flw fa0, 76(s1)
; ILP32-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 80(s1) ; ILP32-NEXT: flw fa0, 80(s1)
; ILP32-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 84(s1) ; ILP32-NEXT: flw fa0, 84(s1)
; ILP32-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 88(s1) ; ILP32-NEXT: flw fa0, 88(s1)
; ILP32-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 92(s1) ; ILP32-NEXT: flw fa0, 92(s1)
; ILP32-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 96(s1) ; ILP32-NEXT: flw fa0, 96(s1)
; ILP32-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 100(s1) ; ILP32-NEXT: flw fa0, 100(s1)
; ILP32-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 104(s1) ; ILP32-NEXT: flw fa0, 104(s1)
; ILP32-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 108(s1) ; ILP32-NEXT: flw fa0, 108(s1)
; ILP32-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 112(s1) ; ILP32-NEXT: flw fa0, 112(s1)
; ILP32-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 116(s1) ; ILP32-NEXT: flw fa0, 116(s1)
; ILP32-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 120(s1) ; ILP32-NEXT: flw fa0, 120(s1)
; ILP32-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 124(s1) ; ILP32-NEXT: flw fa0, 124(s1)
; ILP32-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; ILP32-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
; ILP32-NEXT: call callee@plt ; ILP32-NEXT: call callee@plt
; ILP32-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 124(s1) ; ILP32-NEXT: fsw fa0, 124(s1)
; ILP32-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 120(s1) ; ILP32-NEXT: fsw fa0, 120(s1)
; ILP32-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 116(s1) ; ILP32-NEXT: fsw fa0, 116(s1)
; ILP32-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 112(s1) ; ILP32-NEXT: fsw fa0, 112(s1)
; ILP32-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 108(s1) ; ILP32-NEXT: fsw fa0, 108(s1)
; ILP32-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 104(s1) ; ILP32-NEXT: fsw fa0, 104(s1)
; ILP32-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 100(s1) ; ILP32-NEXT: fsw fa0, 100(s1)
; ILP32-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 96(s1) ; ILP32-NEXT: fsw fa0, 96(s1)
; ILP32-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 92(s1) ; ILP32-NEXT: fsw fa0, 92(s1)
; ILP32-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 88(s1) ; ILP32-NEXT: fsw fa0, 88(s1)
; ILP32-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 84(s1) ; ILP32-NEXT: fsw fa0, 84(s1)
; ILP32-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 80(s1) ; ILP32-NEXT: fsw fa0, 80(s1)
; ILP32-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 76(s1) ; ILP32-NEXT: fsw fa0, 76(s1)
; ILP32-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 72(s1) ; ILP32-NEXT: fsw fa0, 72(s1)
; ILP32-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 68(s1) ; ILP32-NEXT: fsw fa0, 68(s1)
; ILP32-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 64(s1) ; ILP32-NEXT: fsw fa0, 64(s1)
; ILP32-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 60(s1) ; ILP32-NEXT: fsw fa0, 60(s1)
; ILP32-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 56(s1) ; ILP32-NEXT: fsw fa0, 56(s1)
; ILP32-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 52(s1) ; ILP32-NEXT: fsw fa0, 52(s1)
; ILP32-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 48(s1) ; ILP32-NEXT: fsw fa0, 48(s1)
; ILP32-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 44(s1) ; ILP32-NEXT: fsw fa0, 44(s1)
; ILP32-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 88(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 40(s1) ; ILP32-NEXT: fsw fa0, 40(s1)
; ILP32-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 36(s1) ; ILP32-NEXT: fsw fa0, 36(s1)
; ILP32-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 32(s1) ; ILP32-NEXT: fsw fa0, 32(s1)
; ILP32-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 100(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 28(s1) ; ILP32-NEXT: fsw fa0, 28(s1)
; ILP32-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 24(s1) ; ILP32-NEXT: fsw fa0, 24(s1)
; ILP32-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 108(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 20(s1) ; ILP32-NEXT: fsw fa0, 20(s1)
; ILP32-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 112(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 16(s1) ; ILP32-NEXT: fsw fa0, 16(s1)
; ILP32-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 116(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32-NEXT: fsw fa0, %lo(var+12)(s0)
; ILP32-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 120(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32-NEXT: fsw fa0, %lo(var+8)(s0)
; ILP32-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 124(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32-NEXT: fsw fa0, %lo(var+4)(s0)
; ILP32-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload ; ILP32-NEXT: flw fa0, 128(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var)(s0) ; ILP32-NEXT: fsw fa0, %lo(var)(s0)
; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 144 ; ILP32-NEXT: addi sp, sp, 144
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: caller: ; LP64-LABEL: caller:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: addi sp, sp, -160 ; LP64-NEXT: addi sp, sp, -160
; LP64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LP64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var) ; LP64-NEXT: lui s0, %hi(var)
; LP64-NEXT: flw ft0, %lo(var)(s0) ; LP64-NEXT: flw fa0, %lo(var)(s0)
; LP64-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 132(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+4)(s0) ; LP64-NEXT: flw fa0, %lo(var+4)(s0)
; LP64-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 128(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+8)(s0) ; LP64-NEXT: flw fa0, %lo(var+8)(s0)
; LP64-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 124(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+12)(s0) ; LP64-NEXT: flw fa0, %lo(var+12)(s0)
; LP64-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 120(sp) # 4-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: addi s1, s0, %lo(var)
; LP64-NEXT: flw ft0, 16(s1) ; LP64-NEXT: flw fa0, 16(s1)
; LP64-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 116(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 20(s1) ; LP64-NEXT: flw fa0, 20(s1)
; LP64-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 112(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 24(s1) ; LP64-NEXT: flw fa0, 24(s1)
; LP64-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 108(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 28(s1) ; LP64-NEXT: flw fa0, 28(s1)
; LP64-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 32(s1) ; LP64-NEXT: flw fa0, 32(s1)
; LP64-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 100(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 36(s1) ; LP64-NEXT: flw fa0, 36(s1)
; LP64-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 40(s1) ; LP64-NEXT: flw fa0, 40(s1)
; LP64-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 44(s1) ; LP64-NEXT: flw fa0, 44(s1)
; LP64-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 88(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 48(s1) ; LP64-NEXT: flw fa0, 48(s1)
; LP64-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 52(s1) ; LP64-NEXT: flw fa0, 52(s1)
; LP64-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 56(s1) ; LP64-NEXT: flw fa0, 56(s1)
; LP64-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 60(s1) ; LP64-NEXT: flw fa0, 60(s1)
; LP64-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 64(s1) ; LP64-NEXT: flw fa0, 64(s1)
; LP64-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 68(s1) ; LP64-NEXT: flw fa0, 68(s1)
; LP64-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 72(s1) ; LP64-NEXT: flw fa0, 72(s1)
; LP64-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 76(s1) ; LP64-NEXT: flw fa0, 76(s1)
; LP64-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 80(s1) ; LP64-NEXT: flw fa0, 80(s1)
; LP64-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 84(s1) ; LP64-NEXT: flw fa0, 84(s1)
; LP64-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 88(s1) ; LP64-NEXT: flw fa0, 88(s1)
; LP64-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 92(s1) ; LP64-NEXT: flw fa0, 92(s1)
; LP64-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 96(s1) ; LP64-NEXT: flw fa0, 96(s1)
; LP64-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 100(s1) ; LP64-NEXT: flw fa0, 100(s1)
; LP64-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 104(s1) ; LP64-NEXT: flw fa0, 104(s1)
; LP64-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 108(s1) ; LP64-NEXT: flw fa0, 108(s1)
; LP64-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 112(s1) ; LP64-NEXT: flw fa0, 112(s1)
; LP64-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 116(s1) ; LP64-NEXT: flw fa0, 116(s1)
; LP64-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 120(s1) ; LP64-NEXT: flw fa0, 120(s1)
; LP64-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 124(s1) ; LP64-NEXT: flw fa0, 124(s1)
; LP64-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; LP64-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64-NEXT: call callee@plt ; LP64-NEXT: call callee@plt
; LP64-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 124(s1) ; LP64-NEXT: fsw fa0, 124(s1)
; LP64-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 120(s1) ; LP64-NEXT: fsw fa0, 120(s1)
; LP64-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 116(s1) ; LP64-NEXT: fsw fa0, 116(s1)
; LP64-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 112(s1) ; LP64-NEXT: fsw fa0, 112(s1)
; LP64-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 108(s1) ; LP64-NEXT: fsw fa0, 108(s1)
; LP64-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 104(s1) ; LP64-NEXT: fsw fa0, 104(s1)
; LP64-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 100(s1) ; LP64-NEXT: fsw fa0, 100(s1)
; LP64-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 96(s1) ; LP64-NEXT: fsw fa0, 96(s1)
; LP64-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 92(s1) ; LP64-NEXT: fsw fa0, 92(s1)
; LP64-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 88(s1) ; LP64-NEXT: fsw fa0, 88(s1)
; LP64-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 84(s1) ; LP64-NEXT: fsw fa0, 84(s1)
; LP64-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 80(s1) ; LP64-NEXT: fsw fa0, 80(s1)
; LP64-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 76(s1) ; LP64-NEXT: fsw fa0, 76(s1)
; LP64-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 72(s1) ; LP64-NEXT: fsw fa0, 72(s1)
; LP64-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 68(s1) ; LP64-NEXT: fsw fa0, 68(s1)
; LP64-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 64(s1) ; LP64-NEXT: fsw fa0, 64(s1)
; LP64-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 60(s1) ; LP64-NEXT: fsw fa0, 60(s1)
; LP64-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 56(s1) ; LP64-NEXT: fsw fa0, 56(s1)
; LP64-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 52(s1) ; LP64-NEXT: fsw fa0, 52(s1)
; LP64-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 48(s1) ; LP64-NEXT: fsw fa0, 48(s1)
; LP64-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 88(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 44(s1) ; LP64-NEXT: fsw fa0, 44(s1)
; LP64-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 40(s1) ; LP64-NEXT: fsw fa0, 40(s1)
; LP64-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 36(s1) ; LP64-NEXT: fsw fa0, 36(s1)
; LP64-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 100(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 32(s1) ; LP64-NEXT: fsw fa0, 32(s1)
; LP64-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 28(s1) ; LP64-NEXT: fsw fa0, 28(s1)
; LP64-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 108(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 24(s1) ; LP64-NEXT: fsw fa0, 24(s1)
; LP64-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 112(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 20(s1) ; LP64-NEXT: fsw fa0, 20(s1)
; LP64-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 116(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 16(s1) ; LP64-NEXT: fsw fa0, 16(s1)
; LP64-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 120(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64-NEXT: fsw fa0, %lo(var+12)(s0)
; LP64-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 124(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64-NEXT: fsw fa0, %lo(var+8)(s0)
; LP64-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 128(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64-NEXT: fsw fa0, %lo(var+4)(s0)
; LP64-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload ; LP64-NEXT: flw fa0, 132(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var)(s0) ; LP64-NEXT: fsw fa0, %lo(var)(s0)
; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; LP64-NEXT: addi sp, sp, 160 ; LP64-NEXT: addi sp, sp, 160
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32F-LABEL: caller: ; ILP32F-LABEL: caller:
; ILP32F: # %bb.0: ; ILP32F: # %bb.0:
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; ILP32F-NEXT: fsw fs5, 108(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs5, 108(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs6, 104(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs6, 104(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs7, 100(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs7, 100(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs8, 96(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs8, 96(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs9, 92(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs9, 92(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui s0, %hi(var) ; ILP32F-NEXT: lui s0, %hi(var)
; ILP32F-NEXT: flw ft0, %lo(var)(s0) ; ILP32F-NEXT: flw fa0, %lo(var)(s0)
; ILP32F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: flw fa0, %lo(var+4)(s0)
; ILP32F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32F-NEXT: flw fa0, %lo(var+8)(s0)
; ILP32F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32F-NEXT: flw fa0, %lo(var+12)(s0)
; ILP32F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; ILP32F-NEXT: addi s1, s0, %lo(var) ; ILP32F-NEXT: addi s1, s0, %lo(var)
; ILP32F-NEXT: flw ft0, 16(s1) ; ILP32F-NEXT: flw fa0, 16(s1)
; ILP32F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 20(s1) ; ILP32F-NEXT: flw fa0, 20(s1)
; ILP32F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 24(s1) ; ILP32F-NEXT: flw fa0, 24(s1)
; ILP32F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 28(s1) ; ILP32F-NEXT: flw fa0, 28(s1)
; ILP32F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 32(s1) ; ILP32F-NEXT: flw fa0, 32(s1)
; ILP32F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 36(s1) ; ILP32F-NEXT: flw fa0, 36(s1)
; ILP32F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 40(s1) ; ILP32F-NEXT: flw fa0, 40(s1)
; ILP32F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 44(s1) ; ILP32F-NEXT: flw fa0, 44(s1)
; ILP32F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 48(s1) ; ILP32F-NEXT: flw fa0, 48(s1)
; ILP32F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 52(s1) ; ILP32F-NEXT: flw fa0, 52(s1)
; ILP32F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 56(s1) ; ILP32F-NEXT: flw fa0, 56(s1)
; ILP32F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 60(s1) ; ILP32F-NEXT: flw fa0, 60(s1)
; ILP32F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 64(s1) ; ILP32F-NEXT: flw fa0, 64(s1)
; ILP32F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 68(s1) ; ILP32F-NEXT: flw fa0, 68(s1)
; ILP32F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 72(s1) ; ILP32F-NEXT: flw fa0, 72(s1)
; ILP32F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 76(s1) ; ILP32F-NEXT: flw fa0, 76(s1)
; ILP32F-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw fs8, 80(s1) ; ILP32F-NEXT: flw fs8, 80(s1)
; ILP32F-NEXT: flw fs9, 84(s1) ; ILP32F-NEXT: flw fs9, 84(s1)
; ILP32F-NEXT: flw fs10, 88(s1) ; ILP32F-NEXT: flw fs10, 88(s1)
; ILP32F-NEXT: flw fs11, 92(s1) ; ILP32F-NEXT: flw fs11, 92(s1)
; ILP32F-NEXT: flw fs0, 96(s1) ; ILP32F-NEXT: flw fs0, 96(s1)
; ILP32F-NEXT: flw fs1, 100(s1) ; ILP32F-NEXT: flw fs1, 100(s1)
; ILP32F-NEXT: flw fs2, 104(s1) ; ILP32F-NEXT: flw fs2, 104(s1)
; ILP32F-NEXT: flw fs3, 108(s1) ; ILP32F-NEXT: flw fs3, 108(s1)
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; ILP32F-NEXT: fsw fs3, 108(s1) ; ILP32F-NEXT: fsw fs3, 108(s1)
; ILP32F-NEXT: fsw fs2, 104(s1) ; ILP32F-NEXT: fsw fs2, 104(s1)
; ILP32F-NEXT: fsw fs1, 100(s1) ; ILP32F-NEXT: fsw fs1, 100(s1)
; ILP32F-NEXT: fsw fs0, 96(s1) ; ILP32F-NEXT: fsw fs0, 96(s1)
; ILP32F-NEXT: fsw fs11, 92(s1) ; ILP32F-NEXT: fsw fs11, 92(s1)
; ILP32F-NEXT: fsw fs10, 88(s1) ; ILP32F-NEXT: fsw fs10, 88(s1)
; ILP32F-NEXT: fsw fs9, 84(s1) ; ILP32F-NEXT: fsw fs9, 84(s1)
; ILP32F-NEXT: fsw fs8, 80(s1) ; ILP32F-NEXT: fsw fs8, 80(s1)
; ILP32F-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 76(s1) ; ILP32F-NEXT: fsw fa0, 76(s1)
; ILP32F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 72(s1) ; ILP32F-NEXT: fsw fa0, 72(s1)
; ILP32F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 68(s1) ; ILP32F-NEXT: fsw fa0, 68(s1)
; ILP32F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 64(s1) ; ILP32F-NEXT: fsw fa0, 64(s1)
; ILP32F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 60(s1) ; ILP32F-NEXT: fsw fa0, 60(s1)
; ILP32F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 56(s1) ; ILP32F-NEXT: fsw fa0, 56(s1)
; ILP32F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 52(s1) ; ILP32F-NEXT: fsw fa0, 52(s1)
; ILP32F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 48(s1) ; ILP32F-NEXT: fsw fa0, 48(s1)
; ILP32F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 44(s1) ; ILP32F-NEXT: fsw fa0, 44(s1)
; ILP32F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 40(s1) ; ILP32F-NEXT: fsw fa0, 40(s1)
; ILP32F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 36(s1) ; ILP32F-NEXT: fsw fa0, 36(s1)
; ILP32F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 32(s1) ; ILP32F-NEXT: fsw fa0, 32(s1)
; ILP32F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 28(s1) ; ILP32F-NEXT: fsw fa0, 28(s1)
; ILP32F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 24(s1) ; ILP32F-NEXT: fsw fa0, 24(s1)
; ILP32F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 20(s1) ; ILP32F-NEXT: fsw fa0, 20(s1)
; ILP32F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 16(s1) ; ILP32F-NEXT: fsw fa0, 16(s1)
; ILP32F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32F-NEXT: fsw fa0, %lo(var+12)(s0)
; ILP32F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32F-NEXT: fsw fa0, %lo(var+8)(s0)
; ILP32F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: fsw fa0, %lo(var+4)(s0)
; ILP32F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var)(s0) ; ILP32F-NEXT: fsw fa0, %lo(var)(s0)
; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload ; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs0, 128(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs0, 128(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 124(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs1, 124(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 120(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs2, 120(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs3, 116(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs3, 116(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs4, 112(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs4, 112(sp) # 4-byte Folded Reload
Show All 21 Lines
; LP64F-NEXT: fsw fs5, 112(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs5, 112(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs6, 108(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs6, 108(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs7, 104(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs7, 104(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs8, 100(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs8, 100(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs9, 96(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs9, 96(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui s0, %hi(var) ; LP64F-NEXT: lui s0, %hi(var)
; LP64F-NEXT: flw ft0, %lo(var)(s0) ; LP64F-NEXT: flw fa0, %lo(var)(s0)
; LP64F-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+4)(s0) ; LP64F-NEXT: flw fa0, %lo(var+4)(s0)
; LP64F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+8)(s0) ; LP64F-NEXT: flw fa0, %lo(var+8)(s0)
; LP64F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+12)(s0) ; LP64F-NEXT: flw fa0, %lo(var+12)(s0)
; LP64F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; LP64F-NEXT: addi s1, s0, %lo(var) ; LP64F-NEXT: addi s1, s0, %lo(var)
; LP64F-NEXT: flw ft0, 16(s1) ; LP64F-NEXT: flw fa0, 16(s1)
; LP64F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 20(s1) ; LP64F-NEXT: flw fa0, 20(s1)
; LP64F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 24(s1) ; LP64F-NEXT: flw fa0, 24(s1)
; LP64F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 28(s1) ; LP64F-NEXT: flw fa0, 28(s1)
; LP64F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 32(s1) ; LP64F-NEXT: flw fa0, 32(s1)
; LP64F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 36(s1) ; LP64F-NEXT: flw fa0, 36(s1)
; LP64F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 40(s1) ; LP64F-NEXT: flw fa0, 40(s1)
; LP64F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 44(s1) ; LP64F-NEXT: flw fa0, 44(s1)
; LP64F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 48(s1) ; LP64F-NEXT: flw fa0, 48(s1)
; LP64F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 52(s1) ; LP64F-NEXT: flw fa0, 52(s1)
; LP64F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 56(s1) ; LP64F-NEXT: flw fa0, 56(s1)
; LP64F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 60(s1) ; LP64F-NEXT: flw fa0, 60(s1)
; LP64F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 64(s1) ; LP64F-NEXT: flw fa0, 64(s1)
; LP64F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 68(s1) ; LP64F-NEXT: flw fa0, 68(s1)
; LP64F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 72(s1) ; LP64F-NEXT: flw fa0, 72(s1)
; LP64F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 76(s1) ; LP64F-NEXT: flw fa0, 76(s1)
; LP64F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw fs8, 80(s1) ; LP64F-NEXT: flw fs8, 80(s1)
; LP64F-NEXT: flw fs9, 84(s1) ; LP64F-NEXT: flw fs9, 84(s1)
; LP64F-NEXT: flw fs10, 88(s1) ; LP64F-NEXT: flw fs10, 88(s1)
; LP64F-NEXT: flw fs11, 92(s1) ; LP64F-NEXT: flw fs11, 92(s1)
; LP64F-NEXT: flw fs0, 96(s1) ; LP64F-NEXT: flw fs0, 96(s1)
; LP64F-NEXT: flw fs1, 100(s1) ; LP64F-NEXT: flw fs1, 100(s1)
; LP64F-NEXT: flw fs2, 104(s1) ; LP64F-NEXT: flw fs2, 104(s1)
; LP64F-NEXT: flw fs3, 108(s1) ; LP64F-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; LP64F-NEXT: fsw fs3, 108(s1) ; LP64F-NEXT: fsw fs3, 108(s1)
; LP64F-NEXT: fsw fs2, 104(s1) ; LP64F-NEXT: fsw fs2, 104(s1)
; LP64F-NEXT: fsw fs1, 100(s1) ; LP64F-NEXT: fsw fs1, 100(s1)
; LP64F-NEXT: fsw fs0, 96(s1) ; LP64F-NEXT: fsw fs0, 96(s1)
; LP64F-NEXT: fsw fs11, 92(s1) ; LP64F-NEXT: fsw fs11, 92(s1)
; LP64F-NEXT: fsw fs10, 88(s1) ; LP64F-NEXT: fsw fs10, 88(s1)
; LP64F-NEXT: fsw fs9, 84(s1) ; LP64F-NEXT: fsw fs9, 84(s1)
; LP64F-NEXT: fsw fs8, 80(s1) ; LP64F-NEXT: fsw fs8, 80(s1)
; LP64F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 76(s1) ; LP64F-NEXT: fsw fa0, 76(s1)
; LP64F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 72(s1) ; LP64F-NEXT: fsw fa0, 72(s1)
; LP64F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 68(s1) ; LP64F-NEXT: fsw fa0, 68(s1)
; LP64F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 64(s1) ; LP64F-NEXT: fsw fa0, 64(s1)
; LP64F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 60(s1) ; LP64F-NEXT: fsw fa0, 60(s1)
; LP64F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 56(s1) ; LP64F-NEXT: fsw fa0, 56(s1)
; LP64F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 52(s1) ; LP64F-NEXT: fsw fa0, 52(s1)
; LP64F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 48(s1) ; LP64F-NEXT: fsw fa0, 48(s1)
; LP64F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 44(s1) ; LP64F-NEXT: fsw fa0, 44(s1)
; LP64F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 40(s1) ; LP64F-NEXT: fsw fa0, 40(s1)
; LP64F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 36(s1) ; LP64F-NEXT: fsw fa0, 36(s1)
; LP64F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 32(s1) ; LP64F-NEXT: fsw fa0, 32(s1)
; LP64F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 28(s1) ; LP64F-NEXT: fsw fa0, 28(s1)
; LP64F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 24(s1) ; LP64F-NEXT: fsw fa0, 24(s1)
; LP64F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 20(s1) ; LP64F-NEXT: fsw fa0, 20(s1)
; LP64F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 16(s1) ; LP64F-NEXT: fsw fa0, 16(s1)
; LP64F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64F-NEXT: fsw fa0, %lo(var+12)(s0)
; LP64F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64F-NEXT: fsw fa0, %lo(var+8)(s0)
; LP64F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64F-NEXT: fsw fa0, %lo(var+4)(s0)
; LP64F-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var)(s0) ; LP64F-NEXT: fsw fa0, %lo(var)(s0)
; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload ; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; LP64F-NEXT: flw fs0, 132(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs0, 132(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 128(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs1, 128(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 124(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs2, 124(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs3, 120(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs3, 120(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs4, 116(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs4, 116(sp) # 4-byte Folded Reload
Show All 21 Lines
; ILP32D-NEXT: fsd fs5, 128(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs5, 128(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 120(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs6, 120(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 112(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs7, 112(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 104(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs8, 104(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 96(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs9, 96(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var) ; ILP32D-NEXT: lui s0, %hi(var)
; ILP32D-NEXT: flw ft0, %lo(var)(s0) ; ILP32D-NEXT: flw fa0, %lo(var)(s0)
; ILP32D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: flw fa0, %lo(var+4)(s0)
; ILP32D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32D-NEXT: flw fa0, %lo(var+8)(s0)
; ILP32D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32D-NEXT: flw fa0, %lo(var+12)(s0)
; ILP32D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: addi s1, s0, %lo(var)
; ILP32D-NEXT: flw ft0, 16(s1) ; ILP32D-NEXT: flw fa0, 16(s1)
; ILP32D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 20(s1) ; ILP32D-NEXT: flw fa0, 20(s1)
; ILP32D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 24(s1) ; ILP32D-NEXT: flw fa0, 24(s1)
; ILP32D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 28(s1) ; ILP32D-NEXT: flw fa0, 28(s1)
; ILP32D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 32(s1) ; ILP32D-NEXT: flw fa0, 32(s1)
; ILP32D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 36(s1) ; ILP32D-NEXT: flw fa0, 36(s1)
; ILP32D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 40(s1) ; ILP32D-NEXT: flw fa0, 40(s1)
; ILP32D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 44(s1) ; ILP32D-NEXT: flw fa0, 44(s1)
; ILP32D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 48(s1) ; ILP32D-NEXT: flw fa0, 48(s1)
; ILP32D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 52(s1) ; ILP32D-NEXT: flw fa0, 52(s1)
; ILP32D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 56(s1) ; ILP32D-NEXT: flw fa0, 56(s1)
; ILP32D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 60(s1) ; ILP32D-NEXT: flw fa0, 60(s1)
; ILP32D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 64(s1) ; ILP32D-NEXT: flw fa0, 64(s1)
; ILP32D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 68(s1) ; ILP32D-NEXT: flw fa0, 68(s1)
; ILP32D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 72(s1) ; ILP32D-NEXT: flw fa0, 72(s1)
; ILP32D-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 4(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 76(s1) ; ILP32D-NEXT: flw fa0, 76(s1)
; ILP32D-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill ; ILP32D-NEXT: fsw fa0, 0(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw fs8, 80(s1) ; ILP32D-NEXT: flw fs8, 80(s1)
; ILP32D-NEXT: flw fs9, 84(s1) ; ILP32D-NEXT: flw fs9, 84(s1)
; ILP32D-NEXT: flw fs10, 88(s1) ; ILP32D-NEXT: flw fs10, 88(s1)
; ILP32D-NEXT: flw fs11, 92(s1) ; ILP32D-NEXT: flw fs11, 92(s1)
; ILP32D-NEXT: flw fs0, 96(s1) ; ILP32D-NEXT: flw fs0, 96(s1)
; ILP32D-NEXT: flw fs1, 100(s1) ; ILP32D-NEXT: flw fs1, 100(s1)
; ILP32D-NEXT: flw fs2, 104(s1) ; ILP32D-NEXT: flw fs2, 104(s1)
; ILP32D-NEXT: flw fs3, 108(s1) ; ILP32D-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; ILP32D-NEXT: fsw fs3, 108(s1) ; ILP32D-NEXT: fsw fs3, 108(s1)
; ILP32D-NEXT: fsw fs2, 104(s1) ; ILP32D-NEXT: fsw fs2, 104(s1)
; ILP32D-NEXT: fsw fs1, 100(s1) ; ILP32D-NEXT: fsw fs1, 100(s1)
; ILP32D-NEXT: fsw fs0, 96(s1) ; ILP32D-NEXT: fsw fs0, 96(s1)
; ILP32D-NEXT: fsw fs11, 92(s1) ; ILP32D-NEXT: fsw fs11, 92(s1)
; ILP32D-NEXT: fsw fs10, 88(s1) ; ILP32D-NEXT: fsw fs10, 88(s1)
; ILP32D-NEXT: fsw fs9, 84(s1) ; ILP32D-NEXT: fsw fs9, 84(s1)
; ILP32D-NEXT: fsw fs8, 80(s1) ; ILP32D-NEXT: fsw fs8, 80(s1)
; ILP32D-NEXT: flw ft0, 0(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 0(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 76(s1) ; ILP32D-NEXT: fsw fa0, 76(s1)
; ILP32D-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 4(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 72(s1) ; ILP32D-NEXT: fsw fa0, 72(s1)
; ILP32D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 68(s1) ; ILP32D-NEXT: fsw fa0, 68(s1)
; ILP32D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 64(s1) ; ILP32D-NEXT: fsw fa0, 64(s1)
; ILP32D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 60(s1) ; ILP32D-NEXT: fsw fa0, 60(s1)
; ILP32D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 56(s1) ; ILP32D-NEXT: fsw fa0, 56(s1)
; ILP32D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 52(s1) ; ILP32D-NEXT: fsw fa0, 52(s1)
; ILP32D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 48(s1) ; ILP32D-NEXT: fsw fa0, 48(s1)
; ILP32D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 44(s1) ; ILP32D-NEXT: fsw fa0, 44(s1)
; ILP32D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 40(s1) ; ILP32D-NEXT: fsw fa0, 40(s1)
; ILP32D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 36(s1) ; ILP32D-NEXT: fsw fa0, 36(s1)
; ILP32D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 32(s1) ; ILP32D-NEXT: fsw fa0, 32(s1)
; ILP32D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 28(s1) ; ILP32D-NEXT: fsw fa0, 28(s1)
; ILP32D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 24(s1) ; ILP32D-NEXT: fsw fa0, 24(s1)
; ILP32D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 20(s1) ; ILP32D-NEXT: fsw fa0, 20(s1)
; ILP32D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 16(s1) ; ILP32D-NEXT: fsw fa0, 16(s1)
; ILP32D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32D-NEXT: fsw fa0, %lo(var+12)(s0)
; ILP32D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fsw fa0, %lo(var+8)(s0)
; ILP32D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: fsw fa0, %lo(var+4)(s0)
; ILP32D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; ILP32D-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var)(s0) ; ILP32D-NEXT: fsw fa0, %lo(var)(s0)
; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fld fs0, 168(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs0, 168(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 160(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 160(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 152(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 152(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 144(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs3, 144(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 136(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs4, 136(sp) # 8-byte Folded Reload
Show All 21 Lines
; LP64D-NEXT: fsd fs5, 136(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs5, 136(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 128(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs6, 128(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 120(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs7, 120(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 112(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs8, 112(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 104(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs9, 104(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var) ; LP64D-NEXT: lui s0, %hi(var)
; LP64D-NEXT: flw ft0, %lo(var)(s0) ; LP64D-NEXT: flw fa0, %lo(var)(s0)
; LP64D-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+4)(s0) ; LP64D-NEXT: flw fa0, %lo(var+4)(s0)
; LP64D-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 80(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+8)(s0) ; LP64D-NEXT: flw fa0, %lo(var+8)(s0)
; LP64D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 76(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+12)(s0) ; LP64D-NEXT: flw fa0, %lo(var+12)(s0)
; LP64D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 72(sp) # 4-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: addi s1, s0, %lo(var)
; LP64D-NEXT: flw ft0, 16(s1) ; LP64D-NEXT: flw fa0, 16(s1)
; LP64D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 68(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 20(s1) ; LP64D-NEXT: flw fa0, 20(s1)
; LP64D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 64(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 24(s1) ; LP64D-NEXT: flw fa0, 24(s1)
; LP64D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 60(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 28(s1) ; LP64D-NEXT: flw fa0, 28(s1)
; LP64D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 32(s1) ; LP64D-NEXT: flw fa0, 32(s1)
; LP64D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 36(s1) ; LP64D-NEXT: flw fa0, 36(s1)
; LP64D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 48(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 40(s1) ; LP64D-NEXT: flw fa0, 40(s1)
; LP64D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 44(s1) ; LP64D-NEXT: flw fa0, 44(s1)
; LP64D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 40(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 48(s1) ; LP64D-NEXT: flw fa0, 48(s1)
; LP64D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 36(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 52(s1) ; LP64D-NEXT: flw fa0, 52(s1)
; LP64D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 32(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 56(s1) ; LP64D-NEXT: flw fa0, 56(s1)
; LP64D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 28(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 60(s1) ; LP64D-NEXT: flw fa0, 60(s1)
; LP64D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 24(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 64(s1) ; LP64D-NEXT: flw fa0, 64(s1)
; LP64D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 20(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 68(s1) ; LP64D-NEXT: flw fa0, 68(s1)
; LP64D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 72(s1) ; LP64D-NEXT: flw fa0, 72(s1)
; LP64D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 76(s1) ; LP64D-NEXT: flw fa0, 76(s1)
; LP64D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; LP64D-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw fs8, 80(s1) ; LP64D-NEXT: flw fs8, 80(s1)
; LP64D-NEXT: flw fs9, 84(s1) ; LP64D-NEXT: flw fs9, 84(s1)
; LP64D-NEXT: flw fs10, 88(s1) ; LP64D-NEXT: flw fs10, 88(s1)
; LP64D-NEXT: flw fs11, 92(s1) ; LP64D-NEXT: flw fs11, 92(s1)
; LP64D-NEXT: flw fs0, 96(s1) ; LP64D-NEXT: flw fs0, 96(s1)
; LP64D-NEXT: flw fs1, 100(s1) ; LP64D-NEXT: flw fs1, 100(s1)
; LP64D-NEXT: flw fs2, 104(s1) ; LP64D-NEXT: flw fs2, 104(s1)
; LP64D-NEXT: flw fs3, 108(s1) ; LP64D-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; LP64D-NEXT: fsw fs3, 108(s1) ; LP64D-NEXT: fsw fs3, 108(s1)
; LP64D-NEXT: fsw fs2, 104(s1) ; LP64D-NEXT: fsw fs2, 104(s1)
; LP64D-NEXT: fsw fs1, 100(s1) ; LP64D-NEXT: fsw fs1, 100(s1)
; LP64D-NEXT: fsw fs0, 96(s1) ; LP64D-NEXT: fsw fs0, 96(s1)
; LP64D-NEXT: fsw fs11, 92(s1) ; LP64D-NEXT: fsw fs11, 92(s1)
; LP64D-NEXT: fsw fs10, 88(s1) ; LP64D-NEXT: fsw fs10, 88(s1)
; LP64D-NEXT: fsw fs9, 84(s1) ; LP64D-NEXT: fsw fs9, 84(s1)
; LP64D-NEXT: fsw fs8, 80(s1) ; LP64D-NEXT: fsw fs8, 80(s1)
; LP64D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 76(s1) ; LP64D-NEXT: fsw fa0, 76(s1)
; LP64D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 72(s1) ; LP64D-NEXT: fsw fa0, 72(s1)
; LP64D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 68(s1) ; LP64D-NEXT: fsw fa0, 68(s1)
; LP64D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 20(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 64(s1) ; LP64D-NEXT: fsw fa0, 64(s1)
; LP64D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 24(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 60(s1) ; LP64D-NEXT: fsw fa0, 60(s1)
; LP64D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 28(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 56(s1) ; LP64D-NEXT: fsw fa0, 56(s1)
; LP64D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 32(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 52(s1) ; LP64D-NEXT: fsw fa0, 52(s1)
; LP64D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 36(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 48(s1) ; LP64D-NEXT: fsw fa0, 48(s1)
; LP64D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 40(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 44(s1) ; LP64D-NEXT: fsw fa0, 44(s1)
; LP64D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 40(s1) ; LP64D-NEXT: fsw fa0, 40(s1)
; LP64D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 48(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 36(s1) ; LP64D-NEXT: fsw fa0, 36(s1)
; LP64D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 32(s1) ; LP64D-NEXT: fsw fa0, 32(s1)
; LP64D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 28(s1) ; LP64D-NEXT: fsw fa0, 28(s1)
; LP64D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 60(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 24(s1) ; LP64D-NEXT: fsw fa0, 24(s1)
; LP64D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 64(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 20(s1) ; LP64D-NEXT: fsw fa0, 20(s1)
; LP64D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 68(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 16(s1) ; LP64D-NEXT: fsw fa0, 16(s1)
; LP64D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 72(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64D-NEXT: fsw fa0, %lo(var+12)(s0)
; LP64D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 76(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64D-NEXT: fsw fa0, %lo(var+8)(s0)
; LP64D-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 80(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64D-NEXT: fsw fa0, %lo(var+4)(s0)
; LP64D-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload ; LP64D-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var)(s0) ; LP64D-NEXT: fsw fa0, %lo(var)(s0)
; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 176(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs0, 176(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 168(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 168(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 160(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 160(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 152(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs3, 152(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 144(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs4, 144(sp) # 8-byte Folded Reload
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llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

Show All 14 Lines
; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
; something appropriate. ; something appropriate.
define void @callee() nounwind { define void @callee() nounwind {
; ILP32-LABEL: callee: ; ILP32-LABEL: callee:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var) ; ILP32-NEXT: lui a0, %hi(var)
; ILP32-NEXT: fld ft0, %lo(var)(a0) ; ILP32-NEXT: fld fa0, %lo(var)(a0)
; ILP32-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32-NEXT: fld fa1, %lo(var+8)(a0)
; ILP32-NEXT: addi a1, a0, %lo(var) ; ILP32-NEXT: addi a1, a0, %lo(var)
; ILP32-NEXT: fld ft2, 16(a1) ; ILP32-NEXT: fld fa2, 16(a1)
; ILP32-NEXT: fld ft3, 24(a1) ; ILP32-NEXT: fld fa3, 24(a1)
; ILP32-NEXT: fld ft4, 32(a1) ; ILP32-NEXT: fld fa4, 32(a1)
; ILP32-NEXT: fld ft5, 40(a1) ; ILP32-NEXT: fld fa5, 40(a1)
; ILP32-NEXT: fld ft6, 48(a1) ; ILP32-NEXT: fld fa6, 48(a1)
; ILP32-NEXT: fld ft7, 56(a1) ; ILP32-NEXT: fld fa7, 56(a1)
; ILP32-NEXT: fld fa0, 64(a1) ; ILP32-NEXT: fld ft0, 64(a1)
; ILP32-NEXT: fld fa1, 72(a1) ; ILP32-NEXT: fld ft1, 72(a1)
; ILP32-NEXT: fld fa2, 80(a1) ; ILP32-NEXT: fld ft2, 80(a1)
; ILP32-NEXT: fld fa3, 88(a1) ; ILP32-NEXT: fld ft3, 88(a1)
; ILP32-NEXT: fld fa4, 96(a1) ; ILP32-NEXT: fld ft4, 96(a1)
; ILP32-NEXT: fld fa5, 104(a1) ; ILP32-NEXT: fld ft5, 104(a1)
; ILP32-NEXT: fld fa6, 112(a1) ; ILP32-NEXT: fld ft6, 112(a1)
; ILP32-NEXT: fld fa7, 120(a1) ; ILP32-NEXT: fld ft7, 120(a1)
; ILP32-NEXT: fld ft8, 128(a1) ; ILP32-NEXT: fld ft8, 128(a1)
; ILP32-NEXT: fld ft9, 136(a1) ; ILP32-NEXT: fld ft9, 136(a1)
; ILP32-NEXT: fld ft10, 144(a1) ; ILP32-NEXT: fld ft10, 144(a1)
; ILP32-NEXT: fld ft11, 152(a1) ; ILP32-NEXT: fld ft11, 152(a1)
; ILP32-NEXT: fld fs0, 160(a1) ; ILP32-NEXT: fld fs0, 160(a1)
; ILP32-NEXT: fld fs1, 168(a1) ; ILP32-NEXT: fld fs1, 168(a1)
; ILP32-NEXT: fld fs2, 176(a1) ; ILP32-NEXT: fld fs2, 176(a1)
; ILP32-NEXT: fld fs3, 184(a1) ; ILP32-NEXT: fld fs3, 184(a1)
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; ILP32-NEXT: fsd fs3, 184(a1) ; ILP32-NEXT: fsd fs3, 184(a1)
; ILP32-NEXT: fsd fs2, 176(a1) ; ILP32-NEXT: fsd fs2, 176(a1)
; ILP32-NEXT: fsd fs1, 168(a1) ; ILP32-NEXT: fsd fs1, 168(a1)
; ILP32-NEXT: fsd fs0, 160(a1) ; ILP32-NEXT: fsd fs0, 160(a1)
; ILP32-NEXT: fsd ft11, 152(a1) ; ILP32-NEXT: fsd ft11, 152(a1)
; ILP32-NEXT: fsd ft10, 144(a1) ; ILP32-NEXT: fsd ft10, 144(a1)
; ILP32-NEXT: fsd ft9, 136(a1) ; ILP32-NEXT: fsd ft9, 136(a1)
; ILP32-NEXT: fsd ft8, 128(a1) ; ILP32-NEXT: fsd ft8, 128(a1)
; ILP32-NEXT: fsd fa7, 120(a1) ; ILP32-NEXT: fsd ft7, 120(a1)
; ILP32-NEXT: fsd fa6, 112(a1) ; ILP32-NEXT: fsd ft6, 112(a1)
; ILP32-NEXT: fsd fa5, 104(a1) ; ILP32-NEXT: fsd ft5, 104(a1)
; ILP32-NEXT: fsd fa4, 96(a1) ; ILP32-NEXT: fsd ft4, 96(a1)
; ILP32-NEXT: fsd fa3, 88(a1) ; ILP32-NEXT: fsd ft3, 88(a1)
; ILP32-NEXT: fsd fa2, 80(a1) ; ILP32-NEXT: fsd ft2, 80(a1)
; ILP32-NEXT: fsd fa1, 72(a1) ; ILP32-NEXT: fsd ft1, 72(a1)
; ILP32-NEXT: fsd fa0, 64(a1) ; ILP32-NEXT: fsd ft0, 64(a1)
; ILP32-NEXT: fsd ft7, 56(a1) ; ILP32-NEXT: fsd fa7, 56(a1)
; ILP32-NEXT: fsd ft6, 48(a1) ; ILP32-NEXT: fsd fa6, 48(a1)
; ILP32-NEXT: fsd ft5, 40(a1) ; ILP32-NEXT: fsd fa5, 40(a1)
; ILP32-NEXT: fsd ft4, 32(a1) ; ILP32-NEXT: fsd fa4, 32(a1)
; ILP32-NEXT: fsd ft3, 24(a1) ; ILP32-NEXT: fsd fa3, 24(a1)
; ILP32-NEXT: fsd ft2, 16(a1) ; ILP32-NEXT: fsd fa2, 16(a1)
; ILP32-NEXT: fsd ft1, %lo(var+8)(a0) ; ILP32-NEXT: fsd fa1, %lo(var+8)(a0)
; ILP32-NEXT: fsd ft0, %lo(var)(a0) ; ILP32-NEXT: fsd fa0, %lo(var)(a0)
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: callee: ; LP64-LABEL: callee:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var) ; LP64-NEXT: lui a0, %hi(var)
; LP64-NEXT: fld ft0, %lo(var)(a0) ; LP64-NEXT: fld fa0, %lo(var)(a0)
; LP64-NEXT: fld ft1, %lo(var+8)(a0) ; LP64-NEXT: fld fa1, %lo(var+8)(a0)
; LP64-NEXT: addi a1, a0, %lo(var) ; LP64-NEXT: addi a1, a0, %lo(var)
; LP64-NEXT: fld ft2, 16(a1) ; LP64-NEXT: fld fa2, 16(a1)
; LP64-NEXT: fld ft3, 24(a1) ; LP64-NEXT: fld fa3, 24(a1)
; LP64-NEXT: fld ft4, 32(a1) ; LP64-NEXT: fld fa4, 32(a1)
; LP64-NEXT: fld ft5, 40(a1) ; LP64-NEXT: fld fa5, 40(a1)
; LP64-NEXT: fld ft6, 48(a1) ; LP64-NEXT: fld fa6, 48(a1)
; LP64-NEXT: fld ft7, 56(a1) ; LP64-NEXT: fld fa7, 56(a1)
; LP64-NEXT: fld fa0, 64(a1) ; LP64-NEXT: fld ft0, 64(a1)
; LP64-NEXT: fld fa1, 72(a1) ; LP64-NEXT: fld ft1, 72(a1)
; LP64-NEXT: fld fa2, 80(a1) ; LP64-NEXT: fld ft2, 80(a1)
; LP64-NEXT: fld fa3, 88(a1) ; LP64-NEXT: fld ft3, 88(a1)
; LP64-NEXT: fld fa4, 96(a1) ; LP64-NEXT: fld ft4, 96(a1)
; LP64-NEXT: fld fa5, 104(a1) ; LP64-NEXT: fld ft5, 104(a1)
; LP64-NEXT: fld fa6, 112(a1) ; LP64-NEXT: fld ft6, 112(a1)
; LP64-NEXT: fld fa7, 120(a1) ; LP64-NEXT: fld ft7, 120(a1)
; LP64-NEXT: fld ft8, 128(a1) ; LP64-NEXT: fld ft8, 128(a1)
; LP64-NEXT: fld ft9, 136(a1) ; LP64-NEXT: fld ft9, 136(a1)
; LP64-NEXT: fld ft10, 144(a1) ; LP64-NEXT: fld ft10, 144(a1)
; LP64-NEXT: fld ft11, 152(a1) ; LP64-NEXT: fld ft11, 152(a1)
; LP64-NEXT: fld fs0, 160(a1) ; LP64-NEXT: fld fs0, 160(a1)
; LP64-NEXT: fld fs1, 168(a1) ; LP64-NEXT: fld fs1, 168(a1)
; LP64-NEXT: fld fs2, 176(a1) ; LP64-NEXT: fld fs2, 176(a1)
; LP64-NEXT: fld fs3, 184(a1) ; LP64-NEXT: fld fs3, 184(a1)
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; LP64-NEXT: fsd fs3, 184(a1) ; LP64-NEXT: fsd fs3, 184(a1)
; LP64-NEXT: fsd fs2, 176(a1) ; LP64-NEXT: fsd fs2, 176(a1)
; LP64-NEXT: fsd fs1, 168(a1) ; LP64-NEXT: fsd fs1, 168(a1)
; LP64-NEXT: fsd fs0, 160(a1) ; LP64-NEXT: fsd fs0, 160(a1)
; LP64-NEXT: fsd ft11, 152(a1) ; LP64-NEXT: fsd ft11, 152(a1)
; LP64-NEXT: fsd ft10, 144(a1) ; LP64-NEXT: fsd ft10, 144(a1)
; LP64-NEXT: fsd ft9, 136(a1) ; LP64-NEXT: fsd ft9, 136(a1)
; LP64-NEXT: fsd ft8, 128(a1) ; LP64-NEXT: fsd ft8, 128(a1)
; LP64-NEXT: fsd fa7, 120(a1) ; LP64-NEXT: fsd ft7, 120(a1)
; LP64-NEXT: fsd fa6, 112(a1) ; LP64-NEXT: fsd ft6, 112(a1)
; LP64-NEXT: fsd fa5, 104(a1) ; LP64-NEXT: fsd ft5, 104(a1)
; LP64-NEXT: fsd fa4, 96(a1) ; LP64-NEXT: fsd ft4, 96(a1)
; LP64-NEXT: fsd fa3, 88(a1) ; LP64-NEXT: fsd ft3, 88(a1)
; LP64-NEXT: fsd fa2, 80(a1) ; LP64-NEXT: fsd ft2, 80(a1)
; LP64-NEXT: fsd fa1, 72(a1) ; LP64-NEXT: fsd ft1, 72(a1)
; LP64-NEXT: fsd fa0, 64(a1) ; LP64-NEXT: fsd ft0, 64(a1)
; LP64-NEXT: fsd ft7, 56(a1) ; LP64-NEXT: fsd fa7, 56(a1)
; LP64-NEXT: fsd ft6, 48(a1) ; LP64-NEXT: fsd fa6, 48(a1)
; LP64-NEXT: fsd ft5, 40(a1) ; LP64-NEXT: fsd fa5, 40(a1)
; LP64-NEXT: fsd ft4, 32(a1) ; LP64-NEXT: fsd fa4, 32(a1)
; LP64-NEXT: fsd ft3, 24(a1) ; LP64-NEXT: fsd fa3, 24(a1)
; LP64-NEXT: fsd ft2, 16(a1) ; LP64-NEXT: fsd fa2, 16(a1)
; LP64-NEXT: fsd ft1, %lo(var+8)(a0) ; LP64-NEXT: fsd fa1, %lo(var+8)(a0)
; LP64-NEXT: fsd ft0, %lo(var)(a0) ; LP64-NEXT: fsd fa0, %lo(var)(a0)
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32D-LABEL: callee: ; ILP32D-LABEL: callee:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
; ILP32D-NEXT: addi sp, sp, -96 ; ILP32D-NEXT: addi sp, sp, -96
; ILP32D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var) ; ILP32D-NEXT: lui a0, %hi(var)
; ILP32D-NEXT: fld ft0, %lo(var)(a0) ; ILP32D-NEXT: fld fa0, %lo(var)(a0)
; ILP32D-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32D-NEXT: fld fa1, %lo(var+8)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var) ; ILP32D-NEXT: addi a1, a0, %lo(var)
; ILP32D-NEXT: fld ft2, 16(a1) ; ILP32D-NEXT: fld fa2, 16(a1)
; ILP32D-NEXT: fld ft3, 24(a1) ; ILP32D-NEXT: fld fa3, 24(a1)
; ILP32D-NEXT: fld ft4, 32(a1) ; ILP32D-NEXT: fld fa4, 32(a1)
; ILP32D-NEXT: fld ft5, 40(a1) ; ILP32D-NEXT: fld fa5, 40(a1)
; ILP32D-NEXT: fld ft6, 48(a1) ; ILP32D-NEXT: fld fa6, 48(a1)
; ILP32D-NEXT: fld ft7, 56(a1) ; ILP32D-NEXT: fld fa7, 56(a1)
; ILP32D-NEXT: fld fa0, 64(a1) ; ILP32D-NEXT: fld ft0, 64(a1)
; ILP32D-NEXT: fld fa1, 72(a1) ; ILP32D-NEXT: fld ft1, 72(a1)
; ILP32D-NEXT: fld fa2, 80(a1) ; ILP32D-NEXT: fld ft2, 80(a1)
; ILP32D-NEXT: fld fa3, 88(a1) ; ILP32D-NEXT: fld ft3, 88(a1)
; ILP32D-NEXT: fld fa4, 96(a1) ; ILP32D-NEXT: fld ft4, 96(a1)
; ILP32D-NEXT: fld fa5, 104(a1) ; ILP32D-NEXT: fld ft5, 104(a1)
; ILP32D-NEXT: fld fa6, 112(a1) ; ILP32D-NEXT: fld ft6, 112(a1)
; ILP32D-NEXT: fld fa7, 120(a1) ; ILP32D-NEXT: fld ft7, 120(a1)
; ILP32D-NEXT: fld ft8, 128(a1) ; ILP32D-NEXT: fld ft8, 128(a1)
; ILP32D-NEXT: fld ft9, 136(a1) ; ILP32D-NEXT: fld ft9, 136(a1)
; ILP32D-NEXT: fld ft10, 144(a1) ; ILP32D-NEXT: fld ft10, 144(a1)
; ILP32D-NEXT: fld ft11, 152(a1) ; ILP32D-NEXT: fld ft11, 152(a1)
; ILP32D-NEXT: fld fs0, 160(a1) ; ILP32D-NEXT: fld fs0, 160(a1)
; ILP32D-NEXT: fld fs1, 168(a1) ; ILP32D-NEXT: fld fs1, 168(a1)
; ILP32D-NEXT: fld fs2, 176(a1) ; ILP32D-NEXT: fld fs2, 176(a1)
; ILP32D-NEXT: fld fs3, 184(a1) ; ILP32D-NEXT: fld fs3, 184(a1)
Show All 16 Lines
; ILP32D-NEXT: fsd fs3, 184(a1) ; ILP32D-NEXT: fsd fs3, 184(a1)
; ILP32D-NEXT: fsd fs2, 176(a1) ; ILP32D-NEXT: fsd fs2, 176(a1)
; ILP32D-NEXT: fsd fs1, 168(a1) ; ILP32D-NEXT: fsd fs1, 168(a1)
; ILP32D-NEXT: fsd fs0, 160(a1) ; ILP32D-NEXT: fsd fs0, 160(a1)
; ILP32D-NEXT: fsd ft11, 152(a1) ; ILP32D-NEXT: fsd ft11, 152(a1)
; ILP32D-NEXT: fsd ft10, 144(a1) ; ILP32D-NEXT: fsd ft10, 144(a1)
; ILP32D-NEXT: fsd ft9, 136(a1) ; ILP32D-NEXT: fsd ft9, 136(a1)
; ILP32D-NEXT: fsd ft8, 128(a1) ; ILP32D-NEXT: fsd ft8, 128(a1)
; ILP32D-NEXT: fsd fa7, 120(a1) ; ILP32D-NEXT: fsd ft7, 120(a1)
; ILP32D-NEXT: fsd fa6, 112(a1) ; ILP32D-NEXT: fsd ft6, 112(a1)
; ILP32D-NEXT: fsd fa5, 104(a1) ; ILP32D-NEXT: fsd ft5, 104(a1)
; ILP32D-NEXT: fsd fa4, 96(a1) ; ILP32D-NEXT: fsd ft4, 96(a1)
; ILP32D-NEXT: fsd fa3, 88(a1) ; ILP32D-NEXT: fsd ft3, 88(a1)
; ILP32D-NEXT: fsd fa2, 80(a1) ; ILP32D-NEXT: fsd ft2, 80(a1)
; ILP32D-NEXT: fsd fa1, 72(a1) ; ILP32D-NEXT: fsd ft1, 72(a1)
; ILP32D-NEXT: fsd fa0, 64(a1) ; ILP32D-NEXT: fsd ft0, 64(a1)
; ILP32D-NEXT: fsd ft7, 56(a1) ; ILP32D-NEXT: fsd fa7, 56(a1)
; ILP32D-NEXT: fsd ft6, 48(a1) ; ILP32D-NEXT: fsd fa6, 48(a1)
; ILP32D-NEXT: fsd ft5, 40(a1) ; ILP32D-NEXT: fsd fa5, 40(a1)
; ILP32D-NEXT: fsd ft4, 32(a1) ; ILP32D-NEXT: fsd fa4, 32(a1)
; ILP32D-NEXT: fsd ft3, 24(a1) ; ILP32D-NEXT: fsd fa3, 24(a1)
; ILP32D-NEXT: fsd ft2, 16(a1) ; ILP32D-NEXT: fsd fa2, 16(a1)
; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0) ; ILP32D-NEXT: fsd fa1, %lo(var+8)(a0)
; ILP32D-NEXT: fsd ft0, %lo(var)(a0) ; ILP32D-NEXT: fsd fa0, %lo(var)(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
Show All 15 Lines
; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var) ; LP64D-NEXT: lui a0, %hi(var)
; LP64D-NEXT: fld ft0, %lo(var)(a0) ; LP64D-NEXT: fld fa0, %lo(var)(a0)
; LP64D-NEXT: fld ft1, %lo(var+8)(a0) ; LP64D-NEXT: fld fa1, %lo(var+8)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var) ; LP64D-NEXT: addi a1, a0, %lo(var)
; LP64D-NEXT: fld ft2, 16(a1) ; LP64D-NEXT: fld fa2, 16(a1)
; LP64D-NEXT: fld ft3, 24(a1) ; LP64D-NEXT: fld fa3, 24(a1)
; LP64D-NEXT: fld ft4, 32(a1) ; LP64D-NEXT: fld fa4, 32(a1)
; LP64D-NEXT: fld ft5, 40(a1) ; LP64D-NEXT: fld fa5, 40(a1)
; LP64D-NEXT: fld ft6, 48(a1) ; LP64D-NEXT: fld fa6, 48(a1)
; LP64D-NEXT: fld ft7, 56(a1) ; LP64D-NEXT: fld fa7, 56(a1)
; LP64D-NEXT: fld fa0, 64(a1) ; LP64D-NEXT: fld ft0, 64(a1)
; LP64D-NEXT: fld fa1, 72(a1) ; LP64D-NEXT: fld ft1, 72(a1)
; LP64D-NEXT: fld fa2, 80(a1) ; LP64D-NEXT: fld ft2, 80(a1)
; LP64D-NEXT: fld fa3, 88(a1) ; LP64D-NEXT: fld ft3, 88(a1)
; LP64D-NEXT: fld fa4, 96(a1) ; LP64D-NEXT: fld ft4, 96(a1)
; LP64D-NEXT: fld fa5, 104(a1) ; LP64D-NEXT: fld ft5, 104(a1)
; LP64D-NEXT: fld fa6, 112(a1) ; LP64D-NEXT: fld ft6, 112(a1)
; LP64D-NEXT: fld fa7, 120(a1) ; LP64D-NEXT: fld ft7, 120(a1)
; LP64D-NEXT: fld ft8, 128(a1) ; LP64D-NEXT: fld ft8, 128(a1)
; LP64D-NEXT: fld ft9, 136(a1) ; LP64D-NEXT: fld ft9, 136(a1)
; LP64D-NEXT: fld ft10, 144(a1) ; LP64D-NEXT: fld ft10, 144(a1)
; LP64D-NEXT: fld ft11, 152(a1) ; LP64D-NEXT: fld ft11, 152(a1)
; LP64D-NEXT: fld fs0, 160(a1) ; LP64D-NEXT: fld fs0, 160(a1)
; LP64D-NEXT: fld fs1, 168(a1) ; LP64D-NEXT: fld fs1, 168(a1)
; LP64D-NEXT: fld fs2, 176(a1) ; LP64D-NEXT: fld fs2, 176(a1)
; LP64D-NEXT: fld fs3, 184(a1) ; LP64D-NEXT: fld fs3, 184(a1)
Show All 16 Lines
; LP64D-NEXT: fsd fs3, 184(a1) ; LP64D-NEXT: fsd fs3, 184(a1)
; LP64D-NEXT: fsd fs2, 176(a1) ; LP64D-NEXT: fsd fs2, 176(a1)
; LP64D-NEXT: fsd fs1, 168(a1) ; LP64D-NEXT: fsd fs1, 168(a1)
; LP64D-NEXT: fsd fs0, 160(a1) ; LP64D-NEXT: fsd fs0, 160(a1)
; LP64D-NEXT: fsd ft11, 152(a1) ; LP64D-NEXT: fsd ft11, 152(a1)
; LP64D-NEXT: fsd ft10, 144(a1) ; LP64D-NEXT: fsd ft10, 144(a1)
; LP64D-NEXT: fsd ft9, 136(a1) ; LP64D-NEXT: fsd ft9, 136(a1)
; LP64D-NEXT: fsd ft8, 128(a1) ; LP64D-NEXT: fsd ft8, 128(a1)
; LP64D-NEXT: fsd fa7, 120(a1) ; LP64D-NEXT: fsd ft7, 120(a1)
; LP64D-NEXT: fsd fa6, 112(a1) ; LP64D-NEXT: fsd ft6, 112(a1)
; LP64D-NEXT: fsd fa5, 104(a1) ; LP64D-NEXT: fsd ft5, 104(a1)
; LP64D-NEXT: fsd fa4, 96(a1) ; LP64D-NEXT: fsd ft4, 96(a1)
; LP64D-NEXT: fsd fa3, 88(a1) ; LP64D-NEXT: fsd ft3, 88(a1)
; LP64D-NEXT: fsd fa2, 80(a1) ; LP64D-NEXT: fsd ft2, 80(a1)
; LP64D-NEXT: fsd fa1, 72(a1) ; LP64D-NEXT: fsd ft1, 72(a1)
; LP64D-NEXT: fsd fa0, 64(a1) ; LP64D-NEXT: fsd ft0, 64(a1)
; LP64D-NEXT: fsd ft7, 56(a1) ; LP64D-NEXT: fsd fa7, 56(a1)
; LP64D-NEXT: fsd ft6, 48(a1) ; LP64D-NEXT: fsd fa6, 48(a1)
; LP64D-NEXT: fsd ft5, 40(a1) ; LP64D-NEXT: fsd fa5, 40(a1)
; LP64D-NEXT: fsd ft4, 32(a1) ; LP64D-NEXT: fsd fa4, 32(a1)
; LP64D-NEXT: fsd ft3, 24(a1) ; LP64D-NEXT: fsd fa3, 24(a1)
; LP64D-NEXT: fsd ft2, 16(a1) ; LP64D-NEXT: fsd fa2, 16(a1)
; LP64D-NEXT: fsd ft1, %lo(var+8)(a0) ; LP64D-NEXT: fsd fa1, %lo(var+8)(a0)
; LP64D-NEXT: fsd ft0, %lo(var)(a0) ; LP64D-NEXT: fsd fa0, %lo(var)(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
Show All 18 Lines
define void @caller() nounwind { define void @caller() nounwind {
; ILP32-LABEL: caller: ; ILP32-LABEL: caller:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: addi sp, sp, -272 ; ILP32-NEXT: addi sp, sp, -272
; ILP32-NEXT: sw ra, 268(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var) ; ILP32-NEXT: lui s0, %hi(var)
; ILP32-NEXT: fld ft0, %lo(var)(s0) ; ILP32-NEXT: fld fa0, %lo(var)(s0)
; ILP32-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 248(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32-NEXT: fld fa0, %lo(var+8)(s0)
; ILP32-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 240(sp) # 8-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: addi s1, s0, %lo(var)
; ILP32-NEXT: fld ft0, 16(s1) ; ILP32-NEXT: fld fa0, 16(s1)
; ILP32-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 232(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 24(s1) ; ILP32-NEXT: fld fa0, 24(s1)
; ILP32-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 224(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 32(s1) ; ILP32-NEXT: fld fa0, 32(s1)
; ILP32-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 216(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 40(s1) ; ILP32-NEXT: fld fa0, 40(s1)
; ILP32-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 208(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 48(s1) ; ILP32-NEXT: fld fa0, 48(s1)
; ILP32-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 200(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 56(s1) ; ILP32-NEXT: fld fa0, 56(s1)
; ILP32-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 64(s1) ; ILP32-NEXT: fld fa0, 64(s1)
; ILP32-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 72(s1) ; ILP32-NEXT: fld fa0, 72(s1)
; ILP32-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 80(s1) ; ILP32-NEXT: fld fa0, 80(s1)
; ILP32-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 88(s1) ; ILP32-NEXT: fld fa0, 88(s1)
; ILP32-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 96(s1) ; ILP32-NEXT: fld fa0, 96(s1)
; ILP32-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 104(s1) ; ILP32-NEXT: fld fa0, 104(s1)
; ILP32-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 112(s1) ; ILP32-NEXT: fld fa0, 112(s1)
; ILP32-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 120(s1) ; ILP32-NEXT: fld fa0, 120(s1)
; ILP32-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 128(s1) ; ILP32-NEXT: fld fa0, 128(s1)
; ILP32-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 136(s1) ; ILP32-NEXT: fld fa0, 136(s1)
; ILP32-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 144(s1) ; ILP32-NEXT: fld fa0, 144(s1)
; ILP32-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 152(s1) ; ILP32-NEXT: fld fa0, 152(s1)
; ILP32-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 160(s1) ; ILP32-NEXT: fld fa0, 160(s1)
; ILP32-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 168(s1) ; ILP32-NEXT: fld fa0, 168(s1)
; ILP32-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 176(s1) ; ILP32-NEXT: fld fa0, 176(s1)
; ILP32-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 184(s1) ; ILP32-NEXT: fld fa0, 184(s1)
; ILP32-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 192(s1) ; ILP32-NEXT: fld fa0, 192(s1)
; ILP32-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 200(s1) ; ILP32-NEXT: fld fa0, 200(s1)
; ILP32-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 208(s1) ; ILP32-NEXT: fld fa0, 208(s1)
; ILP32-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 216(s1) ; ILP32-NEXT: fld fa0, 216(s1)
; ILP32-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 224(s1) ; ILP32-NEXT: fld fa0, 224(s1)
; ILP32-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 232(s1) ; ILP32-NEXT: fld fa0, 232(s1)
; ILP32-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 240(s1) ; ILP32-NEXT: fld fa0, 240(s1)
; ILP32-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 248(s1) ; ILP32-NEXT: fld fa0, 248(s1)
; ILP32-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill ; ILP32-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; ILP32-NEXT: call callee@plt ; ILP32-NEXT: call callee@plt
; ILP32-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 0(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 248(s1) ; ILP32-NEXT: fsd fa0, 248(s1)
; ILP32-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 240(s1) ; ILP32-NEXT: fsd fa0, 240(s1)
; ILP32-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 232(s1) ; ILP32-NEXT: fsd fa0, 232(s1)
; ILP32-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 224(s1) ; ILP32-NEXT: fsd fa0, 224(s1)
; ILP32-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 216(s1) ; ILP32-NEXT: fsd fa0, 216(s1)
; ILP32-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 208(s1) ; ILP32-NEXT: fsd fa0, 208(s1)
; ILP32-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 200(s1) ; ILP32-NEXT: fsd fa0, 200(s1)
; ILP32-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 192(s1) ; ILP32-NEXT: fsd fa0, 192(s1)
; ILP32-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 184(s1) ; ILP32-NEXT: fsd fa0, 184(s1)
; ILP32-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 176(s1) ; ILP32-NEXT: fsd fa0, 176(s1)
; ILP32-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 168(s1) ; ILP32-NEXT: fsd fa0, 168(s1)
; ILP32-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 160(s1) ; ILP32-NEXT: fsd fa0, 160(s1)
; ILP32-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 152(s1) ; ILP32-NEXT: fsd fa0, 152(s1)
; ILP32-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 144(s1) ; ILP32-NEXT: fsd fa0, 144(s1)
; ILP32-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 136(s1) ; ILP32-NEXT: fsd fa0, 136(s1)
; ILP32-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 128(s1) ; ILP32-NEXT: fsd fa0, 128(s1)
; ILP32-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 120(s1) ; ILP32-NEXT: fsd fa0, 120(s1)
; ILP32-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 112(s1) ; ILP32-NEXT: fsd fa0, 112(s1)
; ILP32-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 104(s1) ; ILP32-NEXT: fsd fa0, 104(s1)
; ILP32-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 96(s1) ; ILP32-NEXT: fsd fa0, 96(s1)
; ILP32-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 88(s1) ; ILP32-NEXT: fsd fa0, 88(s1)
; ILP32-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 80(s1) ; ILP32-NEXT: fsd fa0, 80(s1)
; ILP32-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 72(s1) ; ILP32-NEXT: fsd fa0, 72(s1)
; ILP32-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 64(s1) ; ILP32-NEXT: fsd fa0, 64(s1)
; ILP32-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 56(s1) ; ILP32-NEXT: fsd fa0, 56(s1)
; ILP32-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 200(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 48(s1) ; ILP32-NEXT: fsd fa0, 48(s1)
; ILP32-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 208(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 40(s1) ; ILP32-NEXT: fsd fa0, 40(s1)
; ILP32-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 216(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 32(s1) ; ILP32-NEXT: fsd fa0, 32(s1)
; ILP32-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 224(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 24(s1) ; ILP32-NEXT: fsd fa0, 24(s1)
; ILP32-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 232(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 16(s1) ; ILP32-NEXT: fsd fa0, 16(s1)
; ILP32-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 240(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32-NEXT: fsd fa0, %lo(var+8)(s0)
; ILP32-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload ; ILP32-NEXT: fld fa0, 248(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, %lo(var)(s0) ; ILP32-NEXT: fsd fa0, %lo(var)(s0)
; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 272 ; ILP32-NEXT: addi sp, sp, 272
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: caller: ; LP64-LABEL: caller:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: addi sp, sp, -288 ; LP64-NEXT: addi sp, sp, -288
; LP64-NEXT: sd ra, 280(sp) # 8-byte Folded Spill ; LP64-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var) ; LP64-NEXT: lui s0, %hi(var)
; LP64-NEXT: fld ft0, %lo(var)(s0) ; LP64-NEXT: fld fa0, %lo(var)(s0)
; LP64-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 256(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, %lo(var+8)(s0) ; LP64-NEXT: fld fa0, %lo(var+8)(s0)
; LP64-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 248(sp) # 8-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: addi s1, s0, %lo(var)
; LP64-NEXT: fld ft0, 16(s1) ; LP64-NEXT: fld fa0, 16(s1)
; LP64-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 240(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 24(s1) ; LP64-NEXT: fld fa0, 24(s1)
; LP64-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 232(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 32(s1) ; LP64-NEXT: fld fa0, 32(s1)
; LP64-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 224(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 40(s1) ; LP64-NEXT: fld fa0, 40(s1)
; LP64-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 216(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 48(s1) ; LP64-NEXT: fld fa0, 48(s1)
; LP64-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 208(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 56(s1) ; LP64-NEXT: fld fa0, 56(s1)
; LP64-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 200(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 64(s1) ; LP64-NEXT: fld fa0, 64(s1)
; LP64-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 72(s1) ; LP64-NEXT: fld fa0, 72(s1)
; LP64-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 80(s1) ; LP64-NEXT: fld fa0, 80(s1)
; LP64-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 88(s1) ; LP64-NEXT: fld fa0, 88(s1)
; LP64-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 96(s1) ; LP64-NEXT: fld fa0, 96(s1)
; LP64-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 104(s1) ; LP64-NEXT: fld fa0, 104(s1)
; LP64-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 112(s1) ; LP64-NEXT: fld fa0, 112(s1)
; LP64-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 120(s1) ; LP64-NEXT: fld fa0, 120(s1)
; LP64-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 128(s1) ; LP64-NEXT: fld fa0, 128(s1)
; LP64-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 136(s1) ; LP64-NEXT: fld fa0, 136(s1)
; LP64-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 144(s1) ; LP64-NEXT: fld fa0, 144(s1)
; LP64-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 152(s1) ; LP64-NEXT: fld fa0, 152(s1)
; LP64-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 160(s1) ; LP64-NEXT: fld fa0, 160(s1)
; LP64-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 168(s1) ; LP64-NEXT: fld fa0, 168(s1)
; LP64-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 176(s1) ; LP64-NEXT: fld fa0, 176(s1)
; LP64-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 184(s1) ; LP64-NEXT: fld fa0, 184(s1)
; LP64-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 192(s1) ; LP64-NEXT: fld fa0, 192(s1)
; LP64-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 200(s1) ; LP64-NEXT: fld fa0, 200(s1)
; LP64-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 208(s1) ; LP64-NEXT: fld fa0, 208(s1)
; LP64-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 216(s1) ; LP64-NEXT: fld fa0, 216(s1)
; LP64-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 224(s1) ; LP64-NEXT: fld fa0, 224(s1)
; LP64-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 232(s1) ; LP64-NEXT: fld fa0, 232(s1)
; LP64-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 240(s1) ; LP64-NEXT: fld fa0, 240(s1)
; LP64-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 248(s1) ; LP64-NEXT: fld fa0, 248(s1)
; LP64-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; LP64-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; LP64-NEXT: call callee@plt ; LP64-NEXT: call callee@plt
; LP64-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 248(s1) ; LP64-NEXT: fsd fa0, 248(s1)
; LP64-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 240(s1) ; LP64-NEXT: fsd fa0, 240(s1)
; LP64-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 232(s1) ; LP64-NEXT: fsd fa0, 232(s1)
; LP64-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 224(s1) ; LP64-NEXT: fsd fa0, 224(s1)
; LP64-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 216(s1) ; LP64-NEXT: fsd fa0, 216(s1)
; LP64-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 208(s1) ; LP64-NEXT: fsd fa0, 208(s1)
; LP64-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 200(s1) ; LP64-NEXT: fsd fa0, 200(s1)
; LP64-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 192(s1) ; LP64-NEXT: fsd fa0, 192(s1)
; LP64-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 184(s1) ; LP64-NEXT: fsd fa0, 184(s1)
; LP64-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 176(s1) ; LP64-NEXT: fsd fa0, 176(s1)
; LP64-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 168(s1) ; LP64-NEXT: fsd fa0, 168(s1)
; LP64-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 160(s1) ; LP64-NEXT: fsd fa0, 160(s1)
; LP64-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 152(s1) ; LP64-NEXT: fsd fa0, 152(s1)
; LP64-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 144(s1) ; LP64-NEXT: fsd fa0, 144(s1)
; LP64-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 136(s1) ; LP64-NEXT: fsd fa0, 136(s1)
; LP64-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 128(s1) ; LP64-NEXT: fsd fa0, 128(s1)
; LP64-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 120(s1) ; LP64-NEXT: fsd fa0, 120(s1)
; LP64-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 112(s1) ; LP64-NEXT: fsd fa0, 112(s1)
; LP64-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 104(s1) ; LP64-NEXT: fsd fa0, 104(s1)
; LP64-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 96(s1) ; LP64-NEXT: fsd fa0, 96(s1)
; LP64-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 88(s1) ; LP64-NEXT: fsd fa0, 88(s1)
; LP64-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 80(s1) ; LP64-NEXT: fsd fa0, 80(s1)
; LP64-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 72(s1) ; LP64-NEXT: fsd fa0, 72(s1)
; LP64-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 64(s1) ; LP64-NEXT: fsd fa0, 64(s1)
; LP64-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 200(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 56(s1) ; LP64-NEXT: fsd fa0, 56(s1)
; LP64-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 208(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 48(s1) ; LP64-NEXT: fsd fa0, 48(s1)
; LP64-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 216(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 40(s1) ; LP64-NEXT: fsd fa0, 40(s1)
; LP64-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 224(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 32(s1) ; LP64-NEXT: fsd fa0, 32(s1)
; LP64-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 232(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 24(s1) ; LP64-NEXT: fsd fa0, 24(s1)
; LP64-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 240(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 16(s1) ; LP64-NEXT: fsd fa0, 16(s1)
; LP64-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 248(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64-NEXT: fsd fa0, %lo(var+8)(s0)
; LP64-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload ; LP64-NEXT: fld fa0, 256(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, %lo(var)(s0) ; LP64-NEXT: fsd fa0, %lo(var)(s0)
; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; LP64-NEXT: addi sp, sp, 288 ; LP64-NEXT: addi sp, sp, 288
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32D-LABEL: caller: ; ILP32D-LABEL: caller:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
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; ILP32D-NEXT: fsd fs5, 208(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs5, 208(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 200(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs6, 200(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 192(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs7, 192(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 184(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs8, 184(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 176(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs9, 176(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var) ; ILP32D-NEXT: lui s0, %hi(var)
; ILP32D-NEXT: fld ft0, %lo(var)(s0) ; ILP32D-NEXT: fld fa0, %lo(var)(s0)
; ILP32D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fld fa0, %lo(var+8)(s0)
; ILP32D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: addi s1, s0, %lo(var)
; ILP32D-NEXT: fld ft0, 16(s1) ; ILP32D-NEXT: fld fa0, 16(s1)
; ILP32D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 24(s1) ; ILP32D-NEXT: fld fa0, 24(s1)
; ILP32D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 32(s1) ; ILP32D-NEXT: fld fa0, 32(s1)
; ILP32D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 40(s1) ; ILP32D-NEXT: fld fa0, 40(s1)
; ILP32D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 48(s1) ; ILP32D-NEXT: fld fa0, 48(s1)
; ILP32D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 56(s1) ; ILP32D-NEXT: fld fa0, 56(s1)
; ILP32D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 64(s1) ; ILP32D-NEXT: fld fa0, 64(s1)
; ILP32D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 72(s1) ; ILP32D-NEXT: fld fa0, 72(s1)
; ILP32D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 80(s1) ; ILP32D-NEXT: fld fa0, 80(s1)
; ILP32D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 88(s1) ; ILP32D-NEXT: fld fa0, 88(s1)
; ILP32D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 96(s1) ; ILP32D-NEXT: fld fa0, 96(s1)
; ILP32D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 104(s1) ; ILP32D-NEXT: fld fa0, 104(s1)
; ILP32D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 112(s1) ; ILP32D-NEXT: fld fa0, 112(s1)
; ILP32D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 120(s1) ; ILP32D-NEXT: fld fa0, 120(s1)
; ILP32D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 128(s1) ; ILP32D-NEXT: fld fa0, 128(s1)
; ILP32D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 136(s1) ; ILP32D-NEXT: fld fa0, 136(s1)
; ILP32D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 144(s1) ; ILP32D-NEXT: fld fa0, 144(s1)
; ILP32D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 152(s1) ; ILP32D-NEXT: fld fa0, 152(s1)
; ILP32D-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld fs8, 160(s1) ; ILP32D-NEXT: fld fs8, 160(s1)
; ILP32D-NEXT: fld fs9, 168(s1) ; ILP32D-NEXT: fld fs9, 168(s1)
; ILP32D-NEXT: fld fs10, 176(s1) ; ILP32D-NEXT: fld fs10, 176(s1)
; ILP32D-NEXT: fld fs11, 184(s1) ; ILP32D-NEXT: fld fs11, 184(s1)
; ILP32D-NEXT: fld fs0, 192(s1) ; ILP32D-NEXT: fld fs0, 192(s1)
; ILP32D-NEXT: fld fs1, 200(s1) ; ILP32D-NEXT: fld fs1, 200(s1)
; ILP32D-NEXT: fld fs2, 208(s1) ; ILP32D-NEXT: fld fs2, 208(s1)
; ILP32D-NEXT: fld fs3, 216(s1) ; ILP32D-NEXT: fld fs3, 216(s1)
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; ILP32D-NEXT: fsd fs3, 216(s1) ; ILP32D-NEXT: fsd fs3, 216(s1)
; ILP32D-NEXT: fsd fs2, 208(s1) ; ILP32D-NEXT: fsd fs2, 208(s1)
; ILP32D-NEXT: fsd fs1, 200(s1) ; ILP32D-NEXT: fsd fs1, 200(s1)
; ILP32D-NEXT: fsd fs0, 192(s1) ; ILP32D-NEXT: fsd fs0, 192(s1)
; ILP32D-NEXT: fsd fs11, 184(s1) ; ILP32D-NEXT: fsd fs11, 184(s1)
; ILP32D-NEXT: fsd fs10, 176(s1) ; ILP32D-NEXT: fsd fs10, 176(s1)
; ILP32D-NEXT: fsd fs9, 168(s1) ; ILP32D-NEXT: fsd fs9, 168(s1)
; ILP32D-NEXT: fsd fs8, 160(s1) ; ILP32D-NEXT: fsd fs8, 160(s1)
; ILP32D-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 0(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 152(s1) ; ILP32D-NEXT: fsd fa0, 152(s1)
; ILP32D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 144(s1) ; ILP32D-NEXT: fsd fa0, 144(s1)
; ILP32D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 136(s1) ; ILP32D-NEXT: fsd fa0, 136(s1)
; ILP32D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 128(s1) ; ILP32D-NEXT: fsd fa0, 128(s1)
; ILP32D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 120(s1) ; ILP32D-NEXT: fsd fa0, 120(s1)
; ILP32D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 112(s1) ; ILP32D-NEXT: fsd fa0, 112(s1)
; ILP32D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 104(s1) ; ILP32D-NEXT: fsd fa0, 104(s1)
; ILP32D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 96(s1) ; ILP32D-NEXT: fsd fa0, 96(s1)
; ILP32D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 88(s1) ; ILP32D-NEXT: fsd fa0, 88(s1)
; ILP32D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 80(s1) ; ILP32D-NEXT: fsd fa0, 80(s1)
; ILP32D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 72(s1) ; ILP32D-NEXT: fsd fa0, 72(s1)
; ILP32D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 64(s1) ; ILP32D-NEXT: fsd fa0, 64(s1)
; ILP32D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 56(s1) ; ILP32D-NEXT: fsd fa0, 56(s1)
; ILP32D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 48(s1) ; ILP32D-NEXT: fsd fa0, 48(s1)
; ILP32D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 40(s1) ; ILP32D-NEXT: fsd fa0, 40(s1)
; ILP32D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 32(s1) ; ILP32D-NEXT: fsd fa0, 32(s1)
; ILP32D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 24(s1) ; ILP32D-NEXT: fsd fa0, 24(s1)
; ILP32D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 16(s1) ; ILP32D-NEXT: fsd fa0, 16(s1)
; ILP32D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fsd fa0, %lo(var+8)(s0)
; ILP32D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, %lo(var)(s0) ; ILP32D-NEXT: fsd fa0, %lo(var)(s0)
; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fld fs0, 248(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs0, 248(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 240(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 240(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 232(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 232(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 224(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs3, 224(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 216(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs4, 216(sp) # 8-byte Folded Reload
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; LP64D-NEXT: fsd fs5, 216(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs5, 216(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 208(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs6, 208(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 200(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs7, 200(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 192(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs8, 192(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 184(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs9, 184(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var) ; LP64D-NEXT: lui s0, %hi(var)
; LP64D-NEXT: fld ft0, %lo(var)(s0) ; LP64D-NEXT: fld fa0, %lo(var)(s0)
; LP64D-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 160(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, %lo(var+8)(s0) ; LP64D-NEXT: fld fa0, %lo(var+8)(s0)
; LP64D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 152(sp) # 8-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: addi s1, s0, %lo(var)
; LP64D-NEXT: fld ft0, 16(s1) ; LP64D-NEXT: fld fa0, 16(s1)
; LP64D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 144(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 24(s1) ; LP64D-NEXT: fld fa0, 24(s1)
; LP64D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 136(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 32(s1) ; LP64D-NEXT: fld fa0, 32(s1)
; LP64D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 128(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 40(s1) ; LP64D-NEXT: fld fa0, 40(s1)
; LP64D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 120(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 48(s1) ; LP64D-NEXT: fld fa0, 48(s1)
; LP64D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 112(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 56(s1) ; LP64D-NEXT: fld fa0, 56(s1)
; LP64D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 104(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 64(s1) ; LP64D-NEXT: fld fa0, 64(s1)
; LP64D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 72(s1) ; LP64D-NEXT: fld fa0, 72(s1)
; LP64D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 80(s1) ; LP64D-NEXT: fld fa0, 80(s1)
; LP64D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 80(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 88(s1) ; LP64D-NEXT: fld fa0, 88(s1)
; LP64D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 72(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 96(s1) ; LP64D-NEXT: fld fa0, 96(s1)
; LP64D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 64(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 104(s1) ; LP64D-NEXT: fld fa0, 104(s1)
; LP64D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 56(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 112(s1) ; LP64D-NEXT: fld fa0, 112(s1)
; LP64D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 120(s1) ; LP64D-NEXT: fld fa0, 120(s1)
; LP64D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 128(s1) ; LP64D-NEXT: fld fa0, 128(s1)
; LP64D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 136(s1) ; LP64D-NEXT: fld fa0, 136(s1)
; LP64D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 144(s1) ; LP64D-NEXT: fld fa0, 144(s1)
; LP64D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 152(s1) ; LP64D-NEXT: fld fa0, 152(s1)
; LP64D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld fs8, 160(s1) ; LP64D-NEXT: fld fs8, 160(s1)
; LP64D-NEXT: fld fs9, 168(s1) ; LP64D-NEXT: fld fs9, 168(s1)
; LP64D-NEXT: fld fs10, 176(s1) ; LP64D-NEXT: fld fs10, 176(s1)
; LP64D-NEXT: fld fs11, 184(s1) ; LP64D-NEXT: fld fs11, 184(s1)
; LP64D-NEXT: fld fs0, 192(s1) ; LP64D-NEXT: fld fs0, 192(s1)
; LP64D-NEXT: fld fs1, 200(s1) ; LP64D-NEXT: fld fs1, 200(s1)
; LP64D-NEXT: fld fs2, 208(s1) ; LP64D-NEXT: fld fs2, 208(s1)
; LP64D-NEXT: fld fs3, 216(s1) ; LP64D-NEXT: fld fs3, 216(s1)
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; LP64D-NEXT: fsd fs3, 216(s1) ; LP64D-NEXT: fsd fs3, 216(s1)
; LP64D-NEXT: fsd fs2, 208(s1) ; LP64D-NEXT: fsd fs2, 208(s1)
; LP64D-NEXT: fsd fs1, 200(s1) ; LP64D-NEXT: fsd fs1, 200(s1)
; LP64D-NEXT: fsd fs0, 192(s1) ; LP64D-NEXT: fsd fs0, 192(s1)
; LP64D-NEXT: fsd fs11, 184(s1) ; LP64D-NEXT: fsd fs11, 184(s1)
; LP64D-NEXT: fsd fs10, 176(s1) ; LP64D-NEXT: fsd fs10, 176(s1)
; LP64D-NEXT: fsd fs9, 168(s1) ; LP64D-NEXT: fsd fs9, 168(s1)
; LP64D-NEXT: fsd fs8, 160(s1) ; LP64D-NEXT: fsd fs8, 160(s1)
; LP64D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 152(s1) ; LP64D-NEXT: fsd fa0, 152(s1)
; LP64D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 144(s1) ; LP64D-NEXT: fsd fa0, 144(s1)
; LP64D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 24(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 136(s1) ; LP64D-NEXT: fsd fa0, 136(s1)
; LP64D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 32(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 128(s1) ; LP64D-NEXT: fsd fa0, 128(s1)
; LP64D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 120(s1) ; LP64D-NEXT: fsd fa0, 120(s1)
; LP64D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 112(s1) ; LP64D-NEXT: fsd fa0, 112(s1)
; LP64D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 104(s1) ; LP64D-NEXT: fsd fa0, 104(s1)
; LP64D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 96(s1) ; LP64D-NEXT: fsd fa0, 96(s1)
; LP64D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 88(s1) ; LP64D-NEXT: fsd fa0, 88(s1)
; LP64D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 80(s1) ; LP64D-NEXT: fsd fa0, 80(s1)
; LP64D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 72(s1) ; LP64D-NEXT: fsd fa0, 72(s1)
; LP64D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 64(s1) ; LP64D-NEXT: fsd fa0, 64(s1)
; LP64D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 104(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 56(s1) ; LP64D-NEXT: fsd fa0, 56(s1)
; LP64D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 112(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 48(s1) ; LP64D-NEXT: fsd fa0, 48(s1)
; LP64D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 120(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 40(s1) ; LP64D-NEXT: fsd fa0, 40(s1)
; LP64D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 128(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 32(s1) ; LP64D-NEXT: fsd fa0, 32(s1)
; LP64D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 136(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 24(s1) ; LP64D-NEXT: fsd fa0, 24(s1)
; LP64D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 144(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 16(s1) ; LP64D-NEXT: fsd fa0, 16(s1)
; LP64D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 152(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64D-NEXT: fsd fa0, %lo(var+8)(s0)
; LP64D-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fa0, 160(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, %lo(var)(s0) ; LP64D-NEXT: fsd fa0, %lo(var)(s0)
; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 256(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs0, 256(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 248(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 248(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 240(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 240(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 232(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs3, 232(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 224(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs4, 224(sp) # 8-byte Folded Reload
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llvm/test/CodeGen/RISCV/calling-conv-half.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: callee_half_in_regs: ; RV32IF-LABEL: callee_half_in_regs:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a0 ; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: mv a0, a1 ; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: call __extendhfsf2@plt ; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x fa0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: add a0, s0, a0 ; RV32IF-NEXT: add a0, s0, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: callee_half_in_regs: ; RV64IF-LABEL: callee_half_in_regs:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a0 ; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: mv a0, a1 ; RV64IF-NEXT: mv a0, a1
; RV64IF-NEXT: call __extendhfsf2@plt ; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: addw a0, s0, a0 ; RV64IF-NEXT: addw a0, s0, a0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32-ILP32F-LABEL: callee_half_in_regs: ; RV32-ILP32F-LABEL: callee_half_in_regs:
; RV32-ILP32F: # %bb.0: ; RV32-ILP32F: # %bb.0:
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: caller_half_in_regs: ; RV64IF-LABEL: caller_half_in_regs:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV64IF-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
; RV64IF-NEXT: fmv.x.w a1, ft0 ; RV64IF-NEXT: fmv.x.w a1, fa0
; RV64IF-NEXT: li a0, 1 ; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: call callee_half_in_regs@plt ; RV64IF-NEXT: call callee_half_in_regs@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32-ILP32F-LABEL: caller_half_in_regs: ; RV32-ILP32F-LABEL: caller_half_in_regs:
; RV32-ILP32F: # %bb.0: ; RV32-ILP32F: # %bb.0:
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: callee_half_on_stack: ; RV32IF-LABEL: callee_half_on_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: lhu a0, 16(sp) ; RV32IF-NEXT: lhu a0, 16(sp)
; RV32IF-NEXT: mv s0, a7 ; RV32IF-NEXT: mv s0, a7
; RV32IF-NEXT: call __extendhfsf2@plt ; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x fa0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: add a0, s0, a0 ; RV32IF-NEXT: add a0, s0, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: callee_half_on_stack: ; RV64IF-LABEL: callee_half_on_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lhu a0, 16(sp) ; RV64IF-NEXT: lhu a0, 16(sp)
; RV64IF-NEXT: mv s0, a7 ; RV64IF-NEXT: mv s0, a7
; RV64IF-NEXT: call __extendhfsf2@plt ; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: addw a0, s0, a0 ; RV64IF-NEXT: addw a0, s0, a0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32-ILP32F-LABEL: callee_half_on_stack: ; RV32-ILP32F-LABEL: callee_half_on_stack:
; RV32-ILP32F: # %bb.0: ; RV32-ILP32F: # %bb.0:
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; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, 1048564 ; RV32IF-NEXT: lui a0, 1048564
; RV32IF-NEXT: addi a0, a0, -1024 ; RV32IF-NEXT: addi a0, a0, -1024
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: callee_half_ret: ; RV64IF-LABEL: callee_half_ret:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI4_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI4_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV64IF-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32-ILP32F-LABEL: callee_half_ret: ; RV32-ILP32F-LABEL: callee_half_ret:
; RV32-ILP32F: # %bb.0: ; RV32-ILP32F: # %bb.0:
; RV32-ILP32F-NEXT: lui a0, %hi(.LCPI4_0) ; RV32-ILP32F-NEXT: lui a0, %hi(.LCPI4_0)
; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI4_0)(a0) ; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV32-ILP32F-NEXT: ret ; RV32-ILP32F-NEXT: ret
; ;
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IF-LABEL: caller_half_ret: ; RV32IF-LABEL: caller_half_ret:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call callee_half_ret@plt ; RV32IF-NEXT: call callee_half_ret@plt
; RV32IF-NEXT: call __extendhfsf2@plt ; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x fa0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: caller_half_ret: ; RV64IF-LABEL: caller_half_ret:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call callee_half_ret@plt ; RV64IF-NEXT: call callee_half_ret@plt
; RV64IF-NEXT: call __extendhfsf2@plt ; RV64IF-NEXT: call __extendhfsf2@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32-ILP32F-LABEL: caller_half_ret: ; RV32-ILP32F-LABEL: caller_half_ret:
; RV32-ILP32F: # %bb.0: ; RV32-ILP32F: # %bb.0:
; RV32-ILP32F-NEXT: addi sp, sp, -16 ; RV32-ILP32F-NEXT: addi sp, sp, -16
; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind { define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_gpr_exhausted_fprs: ; RV32-ILP32D-LABEL: callee_double_in_gpr_exhausted_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw a0, 8(sp) ; RV32-ILP32D-NEXT: sw a0, 8(sp)
; RV32-ILP32D-NEXT: sw a1, 12(sp) ; RV32-ILP32D-NEXT: sw a1, 12(sp)
; RV32-ILP32D-NEXT: fld ft0, 8(sp) ; RV32-ILP32D-NEXT: fld fa0, 8(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a0, a1 ; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%h_fptosi = fptosi double %h to i32 %h_fptosi = fptosi double %h to i32
%i_fptosi = fptosi double %i to i32 %i_fptosi = fptosi double %i to i32
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
Show All 34 Lines
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i32 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind { define i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i32 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: lw a0, 16(sp) ; RV32-ILP32D-NEXT: lw a0, 16(sp)
; RV32-ILP32D-NEXT: sw a7, 8(sp) ; RV32-ILP32D-NEXT: sw a7, 8(sp)
; RV32-ILP32D-NEXT: sw a0, 12(sp) ; RV32-ILP32D-NEXT: sw a0, 12(sp)
; RV32-ILP32D-NEXT: fld ft0, 8(sp) ; RV32-ILP32D-NEXT: fld fa0, 8(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a6, a0 ; RV32-ILP32D-NEXT: add a0, a6, a0
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%m_fptosi = fptosi double %m to i32 %m_fptosi = fptosi double %m to i32
%1 = add i32 %g, %m_fptosi %1 = add i32 %g, %m_fptosi
ret i32 %1 ret i32 %1
} }
Show All 38 Lines; RV32-ILP32D-NEXT: ret
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind { define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
; RV32-ILP32D-LABEL: callee_double_on_stack_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: callee_double_on_stack_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: fld ft0, 0(sp) ; RV32-ILP32D-NEXT: fld fa0, 0(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a6, a0 ; RV32-ILP32D-NEXT: add a0, a6, a0
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%g_trunc = trunc i64 %g to i32 %g_trunc = trunc i64 %g to i32
%m_fptosi = fptosi double %m to i32 %m_fptosi = fptosi double %m to i32
%1 = add i32 %g_trunc, %m_fptosi %1 = add i32 %g_trunc, %m_fptosi
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines %1 = call i32 @callee_float_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0) i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind { define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs: ; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1 ; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%h_fptosi = fptosi float %h to i32 %h_fptosi = fptosi float %h to i32
%i_fptosi = fptosi float %i to i32 %i_fptosi = fptosi float %i to i32
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
Show All 28 Lines %1 = call i32 @callee_float_in_gpr_exhausted_fprs(
float 7.0, float 8.0, float 9.0) float 7.0, float 8.0, float 9.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind { define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind {
; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs: ; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: flw ft0, 0(sp) ; RV32-ILP32FD-NEXT: flw fa0, 0(sp)
; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a6, a0 ; RV32-ILP32FD-NEXT: add a0, a6, a0
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%g_trunc = trunc i64 %g to i32 %g_trunc = trunc i64 %g to i32
%m_fptosi = fptosi float %m to i32 %m_fptosi = fptosi float %m to i32
%1 = add i32 %g_trunc, %m_fptosi %1 = add i32 %g_trunc, %m_fptosi
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

Show All 12 Lines
; RV32IF-NEXT: lw a0, 4(sp) ; RV32IF-NEXT: lw a0, 4(sp)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
ret float %f ret float %f
} }
define float @onstack_f32_fadd(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind { define float @onstack_f32_fadd(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
; RV32IF-LABEL: onstack_f32_fadd: ; RV32IF-LABEL: onstack_f32_fadd:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 4(sp) ; RV32IF-NEXT: flw fa0, 4(sp)
; RV32IF-NEXT: flw ft1, 0(sp) ; RV32IF-NEXT: flw fa1, 0(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s fa0, fa1, fa0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = fadd float %e, %f %1 = fadd float %e, %f
ret float %1 ret float %1
} }
define float @caller_onstack_f32_noop(float %a) nounwind { define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-LABEL: caller_onstack_f32_noop: ; RV32IF-LABEL: caller_onstack_f32_noop:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 18 Lines; RV32IF-NEXT: ret
ret float %1 ret float %1
} }
define float @caller_onstack_f32_fadd(float %a, float %b) nounwind { define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-LABEL: caller_onstack_f32_fadd: ; RV32IF-LABEL: caller_onstack_f32_fadd:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x fa0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x fa1, a0
; RV32IF-NEXT: fadd.s ft2, ft1, ft0 ; RV32IF-NEXT: fadd.s fa2, fa1, fa0
; RV32IF-NEXT: fsub.s ft0, ft0, ft1 ; RV32IF-NEXT: fsub.s fa0, fa0, fa1
; RV32IF-NEXT: fsw ft0, 4(sp) ; RV32IF-NEXT: fsw fa0, 4(sp)
; RV32IF-NEXT: li a0, 1 ; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: li a2, 2 ; RV32IF-NEXT: li a2, 2
; RV32IF-NEXT: li a4, 3 ; RV32IF-NEXT: li a4, 3
; RV32IF-NEXT: li a6, 4 ; RV32IF-NEXT: li a6, 4
; RV32IF-NEXT: fsw ft2, 0(sp) ; RV32IF-NEXT: fsw fa2, 0(sp)
; RV32IF-NEXT: li a1, 0 ; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a5, 0 ; RV32IF-NEXT: li a5, 0
; RV32IF-NEXT: li a7, 0 ; RV32IF-NEXT: li a7, 0
; RV32IF-NEXT: call onstack_f32_noop@plt ; RV32IF-NEXT: call onstack_f32_noop@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = fsub float %b, %a %2 = fsub float %b, %a
%3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2) %3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2)
ret float %3 ret float %3
} }

llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s ; RUN: | FileCheck -check-prefix=RV64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64LP64F %s ; RUN: | FileCheck -check-prefix=RV64LP64F %s
define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) { define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
; RV64-LABEL: callee_v2f32: ; RV64-LABEL: callee_v2f32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.w.x ft0, a2 ; RV64-NEXT: fmv.w.x fa0, a2
; RV64-NEXT: fmv.w.x ft1, a0 ; RV64-NEXT: fmv.w.x fa1, a0
; RV64-NEXT: fmv.w.x ft2, a3 ; RV64-NEXT: fmv.w.x fa2, a3
; RV64-NEXT: fmv.w.x ft3, a1 ; RV64-NEXT: fmv.w.x fa3, a1
; RV64-NEXT: fadd.s ft2, ft3, ft2 ; RV64-NEXT: fadd.s fa2, fa3, fa2
; RV64-NEXT: fadd.s ft0, ft1, ft0 ; RV64-NEXT: fadd.s fa0, fa1, fa0
; RV64-NEXT: fmv.x.w a0, ft0 ; RV64-NEXT: fmv.x.w a0, fa0
; RV64-NEXT: fmv.x.w a1, ft2 ; RV64-NEXT: fmv.x.w a1, fa2
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV64LP64F-LABEL: callee_v2f32: ; RV64LP64F-LABEL: callee_v2f32:
; RV64LP64F: # %bb.0: ; RV64LP64F: # %bb.0:
; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2 ; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2
; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3 ; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3
; RV64LP64F-NEXT: ret ; RV64LP64F-NEXT: ret
%z = fadd <2 x float> %x, %y %z = fadd <2 x float> %x, %y
ret <2 x float> %z ret <2 x float> %z
} }
define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) { define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
; RV64-LABEL: callee_v4f32: ; RV64-LABEL: callee_v4f32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.w.x ft0, a4 ; RV64-NEXT: fmv.w.x fa0, a4
; RV64-NEXT: fmv.w.x ft1, a7 ; RV64-NEXT: fmv.w.x fa1, a7
; RV64-NEXT: fmv.w.x ft2, a3 ; RV64-NEXT: fmv.w.x fa2, a3
; RV64-NEXT: fmv.w.x ft3, a6 ; RV64-NEXT: fmv.w.x fa3, a6
; RV64-NEXT: fmv.w.x ft4, a2 ; RV64-NEXT: fmv.w.x fa4, a2
; RV64-NEXT: fmv.w.x ft5, a5 ; RV64-NEXT: fmv.w.x fa5, a5
; RV64-NEXT: fmv.w.x ft6, a1 ; RV64-NEXT: fmv.w.x fa6, a1
; RV64-NEXT: flw ft7, 0(sp) ; RV64-NEXT: flw fa7, 0(sp)
; RV64-NEXT: fadd.s ft5, ft6, ft5 ; RV64-NEXT: fadd.s fa5, fa6, fa5
; RV64-NEXT: fadd.s ft3, ft4, ft3 ; RV64-NEXT: fadd.s fa3, fa4, fa3
; RV64-NEXT: fadd.s ft1, ft2, ft1 ; RV64-NEXT: fadd.s fa1, fa2, fa1
; RV64-NEXT: fadd.s ft0, ft0, ft7 ; RV64-NEXT: fadd.s fa0, fa0, fa7
; RV64-NEXT: fsw ft0, 12(a0) ; RV64-NEXT: fsw fa0, 12(a0)
; RV64-NEXT: fsw ft1, 8(a0) ; RV64-NEXT: fsw fa1, 8(a0)
; RV64-NEXT: fsw ft3, 4(a0) ; RV64-NEXT: fsw fa3, 4(a0)
; RV64-NEXT: fsw ft5, 0(a0) ; RV64-NEXT: fsw fa5, 0(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV64LP64F-LABEL: callee_v4f32: ; RV64LP64F-LABEL: callee_v4f32:
; RV64LP64F: # %bb.0: ; RV64LP64F: # %bb.0:
; RV64LP64F-NEXT: fadd.s ft0, fa0, fa4 ; RV64LP64F-NEXT: fadd.s fa0, fa0, fa4
; RV64LP64F-NEXT: fadd.s ft1, fa1, fa5 ; RV64LP64F-NEXT: fadd.s fa1, fa1, fa5
; RV64LP64F-NEXT: fadd.s ft2, fa2, fa6 ; RV64LP64F-NEXT: fadd.s fa2, fa2, fa6
; RV64LP64F-NEXT: fadd.s ft3, fa3, fa7 ; RV64LP64F-NEXT: fadd.s fa3, fa3, fa7
; RV64LP64F-NEXT: fsw ft3, 12(a0) ; RV64LP64F-NEXT: fsw fa3, 12(a0)
; RV64LP64F-NEXT: fsw ft2, 8(a0) ; RV64LP64F-NEXT: fsw fa2, 8(a0)
; RV64LP64F-NEXT: fsw ft1, 4(a0) ; RV64LP64F-NEXT: fsw fa1, 4(a0)
; RV64LP64F-NEXT: fsw ft0, 0(a0) ; RV64LP64F-NEXT: fsw fa0, 0(a0)
; RV64LP64F-NEXT: ret ; RV64LP64F-NEXT: ret
%z = fadd <4 x float> %x, %y %z = fadd <4 x float> %x, %y
ret <4 x float> %z ret <4 x float> %z
} }

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
} }
; Check lowering of constantpools ; Check lowering of constantpools
define float @lower_constantpool(float %a) nounwind { define float @lower_constantpool(float %a) nounwind {
; RV32I-SMALL-LABEL: lower_constantpool: ; RV32I-SMALL-LABEL: lower_constantpool:
; RV32I-SMALL: # %bb.0: ; RV32I-SMALL: # %bb.0:
; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0) ; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
; RV32I-SMALL-NEXT: flw ft0, %lo(.LCPI3_0)(a1) ; RV32I-SMALL-NEXT: flw fa0, %lo(.LCPI3_0)(a1)
; RV32I-SMALL-NEXT: fmv.w.x ft1, a0 ; RV32I-SMALL-NEXT: fmv.w.x fa1, a0
; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0 ; RV32I-SMALL-NEXT: fadd.s fa0, fa1, fa0
; RV32I-SMALL-NEXT: fmv.x.w a0, ft0 ; RV32I-SMALL-NEXT: fmv.x.w a0, fa0
; RV32I-SMALL-NEXT: ret ; RV32I-SMALL-NEXT: ret
; ;
; RV32I-MEDIUM-LABEL: lower_constantpool: ; RV32I-MEDIUM-LABEL: lower_constantpool:
; RV32I-MEDIUM: # %bb.0: ; RV32I-MEDIUM: # %bb.0:
; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted ; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0) ; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1) ; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
; RV32I-MEDIUM-NEXT: flw ft0, 0(a1) ; RV32I-MEDIUM-NEXT: flw fa0, 0(a1)
; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0 ; RV32I-MEDIUM-NEXT: fmv.w.x fa1, a0
; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0 ; RV32I-MEDIUM-NEXT: fadd.s fa0, fa1, fa0
; RV32I-MEDIUM-NEXT: fmv.x.w a0, ft0 ; RV32I-MEDIUM-NEXT: fmv.x.w a0, fa0
; RV32I-MEDIUM-NEXT: ret ; RV32I-MEDIUM-NEXT: ret
%1 = fadd float %a, 1.0 %1 = fadd float %a, 1.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/copysign-casts.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV32IF-NEXT: and a2, a2, a3 ; RV32IF-NEXT: and a2, a2, a3
; RV32IF-NEXT: slli a1, a1, 1 ; RV32IF-NEXT: slli a1, a1, 1
; RV32IF-NEXT: srli a1, a1, 1 ; RV32IF-NEXT: srli a1, a1, 1
; RV32IF-NEXT: or a1, a1, a2 ; RV32IF-NEXT: or a1, a1, a2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IFD-LABEL: fold_promote_d_s: ; RV32IFD-LABEL: fold_promote_d_s:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.s ft0, fa1 ; RV32IFD-NEXT: fcvt.d.s fa1, fa1
; RV32IFD-NEXT: fsgnj.d fa0, fa0, ft0 ; RV32IFD-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fold_promote_d_s: ; RV64IFD-LABEL: fold_promote_d_s:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.d.s ft0, fa1 ; RV64IFD-NEXT: fcvt.d.s fa1, fa1
; RV64IFD-NEXT: fsgnj.d fa0, fa0, ft0 ; RV64IFD-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_promote_d_s: ; RV32IFZFH-LABEL: fold_promote_d_s:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fmv.x.w a2, fa0 ; RV32IFZFH-NEXT: fmv.x.w a2, fa0
; RV32IFZFH-NEXT: lui a3, 524288 ; RV32IFZFH-NEXT: lui a3, 524288
; RV32IFZFH-NEXT: and a2, a2, a3 ; RV32IFZFH-NEXT: and a2, a2, a3
; RV32IFZFH-NEXT: slli a1, a1, 1 ; RV32IFZFH-NEXT: slli a1, a1, 1
; RV32IFZFH-NEXT: srli a1, a1, 1 ; RV32IFZFH-NEXT: srli a1, a1, 1
; RV32IFZFH-NEXT: or a1, a1, a2 ; RV32IFZFH-NEXT: or a1, a1, a2
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_promote_d_s: ; RV32IFDZFH-LABEL: fold_promote_d_s:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.d.s ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.d.s fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_promote_d_s: ; RV64IFDZFH-LABEL: fold_promote_d_s:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.d.s ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.d.s fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fpext float %b to double %c = fpext float %b to double
%t = call double @llvm.copysign.f64(double %a, double %c) %t = call double @llvm.copysign.f64(double %a, double %c)
ret double %t ret double %t
} }
define double @fold_promote_d_h(double %a, half %b) nounwind { define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32I-LABEL: fold_promote_d_h: ; RV32I-LABEL: fold_promote_d_h:
Show All 30 Lines
; RV32IFD-LABEL: fold_promote_d_h: ; RV32IFD-LABEL: fold_promote_d_h:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fmv.x.w a0, fa1 ; RV32IFD-NEXT: fmv.x.w a0, fa1
; RV32IFD-NEXT: call __extendhfsf2@plt ; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: fcvt.d.s ft0, fa0 ; RV32IFD-NEXT: fcvt.d.s fa0, fa0
; RV32IFD-NEXT: fsgnj.d fa0, fs0, ft0 ; RV32IFD-NEXT: fsgnj.d fa0, fs0, fa0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fold_promote_d_h: ; RV64IFD-LABEL: fold_promote_d_h:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: fmv.x.w a0, fa1 ; RV64IFD-NEXT: fmv.x.w a0, fa1
; RV64IFD-NEXT: call __extendhfsf2@plt ; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: fcvt.d.s ft0, fa0 ; RV64IFD-NEXT: fcvt.d.s fa0, fa0
; RV64IFD-NEXT: fsgnj.d fa0, fs0, ft0 ; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_promote_d_h: ; RV32IFZFH-LABEL: fold_promote_d_h:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fmv.x.h a2, fa0 ; RV32IFZFH-NEXT: fmv.x.h a2, fa0
; RV32IFZFH-NEXT: lui a3, 8 ; RV32IFZFH-NEXT: lui a3, 8
; RV32IFZFH-NEXT: and a2, a2, a3 ; RV32IFZFH-NEXT: and a2, a2, a3
; RV32IFZFH-NEXT: slli a2, a2, 16 ; RV32IFZFH-NEXT: slli a2, a2, 16
; RV32IFZFH-NEXT: slli a1, a1, 1 ; RV32IFZFH-NEXT: slli a1, a1, 1
; RV32IFZFH-NEXT: srli a1, a1, 1 ; RV32IFZFH-NEXT: srli a1, a1, 1
; RV32IFZFH-NEXT: or a1, a1, a2 ; RV32IFZFH-NEXT: or a1, a1, a2
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_promote_d_h: ; RV32IFDZFH-LABEL: fold_promote_d_h:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.d.h ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.d.h fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_promote_d_h: ; RV64IFDZFH-LABEL: fold_promote_d_h:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.d.h ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.d.h fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fpext half %b to double %c = fpext half %b to double
%t = call double @llvm.copysign.f64(double %a, double %c) %t = call double @llvm.copysign.f64(double %a, double %c)
ret double %t ret double %t
} }
define float @fold_promote_f_h(float %a, half %b) nounwind { define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32I-LABEL: fold_promote_f_h: ; RV32I-LABEL: fold_promote_f_h:
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0 ; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_promote_f_h: ; RV32IFZFH-LABEL: fold_promote_f_h:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fcvt.s.h ft0, fa1 ; RV32IFZFH-NEXT: fcvt.s.h fa1, fa1
; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_promote_f_h: ; RV32IFDZFH-LABEL: fold_promote_f_h:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.s.h ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.s.h fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_promote_f_h: ; RV64IFDZFH-LABEL: fold_promote_f_h:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.s.h ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.s.h fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fpext half %b to float %c = fpext half %b to float
%t = call float @llvm.copysign.f32(float %a, float %c) %t = call float @llvm.copysign.f32(float %a, float %c)
ret float %t ret float %t
} }
define float @fold_demote_s_d(float %a, double %b) nounwind { define float @fold_demote_s_d(float %a, double %b) nounwind {
; RV32I-LABEL: fold_demote_s_d: ; RV32I-LABEL: fold_demote_s_d:
Show All 12 Lines
; RV64I-NEXT: srli a1, a1, 63 ; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IF-LABEL: fold_demote_s_d: ; RV32IF-LABEL: fold_demote_s_d:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x fa1, a1
; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IFD-LABEL: fold_demote_s_d: ; RV32IFD-LABEL: fold_demote_s_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.s.d ft0, fa1 ; RV32IFD-NEXT: fcvt.s.d fa1, fa1
; RV32IFD-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFD-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fold_demote_s_d: ; RV64IFD-LABEL: fold_demote_s_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.s.d ft0, fa1 ; RV64IFD-NEXT: fcvt.s.d fa1, fa1
; RV64IFD-NEXT: fsgnj.s fa0, fa0, ft0 ; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_demote_s_d: ; RV32IFZFH-LABEL: fold_demote_s_d:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fmv.w.x ft0, a1 ; RV32IFZFH-NEXT: fmv.w.x fa1, a1
; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_demote_s_d: ; RV32IFDZFH-LABEL: fold_demote_s_d:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.s.d ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.s.d fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_demote_s_d: ; RV64IFDZFH-LABEL: fold_demote_s_d:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.s.d ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.s.d fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fptrunc double %b to float %c = fptrunc double %b to float
%t = call float @llvm.copysign.f32(float %a, float %c) %t = call float @llvm.copysign.f32(float %a, float %c)
ret float %t ret float %t
} }
define half @fold_demote_h_s(half %a, float %b) nounwind { define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32I-LABEL: fold_demote_h_s: ; RV32I-LABEL: fold_demote_h_s:
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: lui a1, 1048560 ; RV64IFD-NEXT: lui a1, 1048560
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a0 ; RV64IFD-NEXT: fmv.w.x fa0, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_demote_h_s: ; RV32IFZFH-LABEL: fold_demote_h_s:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fcvt.h.s ft0, fa1 ; RV32IFZFH-NEXT: fcvt.h.s fa1, fa1
; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_demote_h_s: ; RV32IFDZFH-LABEL: fold_demote_h_s:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.h.s ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.h.s fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_demote_h_s: ; RV64IFDZFH-LABEL: fold_demote_h_s:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.h.s ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.h.s fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fptrunc float %b to half %c = fptrunc float %b to half
%t = call half @llvm.copysign.f16(half %a, half %c) %t = call half @llvm.copysign.f16(half %a, half %c)
ret half %t ret half %t
} }
define half @fold_demote_h_d(half %a, double %b) nounwind { define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32I-LABEL: fold_demote_h_d: ; RV32I-LABEL: fold_demote_h_d:
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: lui a1, 1048560 ; RV64IFD-NEXT: lui a1, 1048560
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a0 ; RV64IFD-NEXT: fmv.w.x fa0, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_demote_h_d: ; RV32IFZFH-LABEL: fold_demote_h_d:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: srli a0, a1, 16 ; RV32IFZFH-NEXT: srli a0, a1, 16
; RV32IFZFH-NEXT: fmv.h.x ft0, a0 ; RV32IFZFH-NEXT: fmv.h.x fa1, a0
; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
; ;
; RV32IFDZFH-LABEL: fold_demote_h_d: ; RV32IFDZFH-LABEL: fold_demote_h_d:
; RV32IFDZFH: # %bb.0: ; RV32IFDZFH: # %bb.0:
; RV32IFDZFH-NEXT: fcvt.h.d ft0, fa1 ; RV32IFDZFH-NEXT: fcvt.h.d fa1, fa1
; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IFDZFH-NEXT: ret ; RV32IFDZFH-NEXT: ret
; ;
; RV64IFDZFH-LABEL: fold_demote_h_d: ; RV64IFDZFH-LABEL: fold_demote_h_d:
; RV64IFDZFH: # %bb.0: ; RV64IFDZFH: # %bb.0:
; RV64IFDZFH-NEXT: fcvt.h.d ft0, fa1 ; RV64IFDZFH-NEXT: fcvt.h.d fa1, fa1
; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IFDZFH-NEXT: ret ; RV64IFDZFH-NEXT: ret
%c = fptrunc double %b to half %c = fptrunc double %b to half
%t = call half @llvm.copysign.f16(half %a, half %c) %t = call half @llvm.copysign.f16(half %a, half %c)
ret half %t ret half %t
} }

llvm/test/CodeGen/RISCV/double-arith-strict.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1 ret double %1
} }
declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) strictfp declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) strictfp
define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp { define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fmsub_d: ; RV32IFD-LABEL: fmsub_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmsub_d: ; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fmsub_d: ; RV32I-LABEL: fmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fneg double %c_ %negc = fneg double %c_
%1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1 ret double %1
} }
define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp { define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmadd_d: ; RV32IFD-LABEL: fnmadd_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0 ; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d: ; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0 ; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_d: ; RV32I-LABEL: fnmadd_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fneg double %c_ %negc = fneg double %c_
%1 = call double @llvm.experimental.constrained.fma.f64(double %nega, double %b, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call double @llvm.experimental.constrained.fma.f64(double %nega, double %b, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1 ret double %1
} }
define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp { define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmadd_d_2: ; RV32IFD-LABEL: fnmadd_d_2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0 ; RV32IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d_2: ; RV64IFD-LABEL: fnmadd_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0 ; RV64IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_d_2: ; RV32I-LABEL: fnmadd_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fneg double %c_ %negc = fneg double %c_
%1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %negb, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %negb, double %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1 ret double %1
} }
define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp { define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmsub_d: ; RV32IFD-LABEL: fnmsub_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d: ; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2 ; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_d: ; RV32I-LABEL: fnmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%nega = fneg double %a_ %nega = fneg double %a_
%1 = call double @llvm.experimental.constrained.fma.f64(double %nega, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call double @llvm.experimental.constrained.fma.f64(double %nega, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1 ret double %1
} }
define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp { define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32IFD-LABEL: fnmsub_d_2: ; RV32IFD-LABEL: fnmsub_d_2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d_2: ; RV64IFD-LABEL: fnmsub_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2 ; RV64IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_d_2: ; RV32I-LABEL: fnmsub_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-arith.ll

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret double %1 ret double %1
} }
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_d(double %a, double %b) nounwind { define i32 @fneg_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fneg_d: ; RV32IFD-LABEL: fneg_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fadd.d ft0, fa0, fa0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa0
; RV32IFD-NEXT: fneg.d ft1, ft0 ; RV32IFD-NEXT: fneg.d fa1, fa0
; RV32IFD-NEXT: feq.d a0, ft0, ft1 ; RV32IFD-NEXT: feq.d a0, fa0, fa1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fneg_d: ; RV64IFD-LABEL: fneg_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d ft0, fa0, fa0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa0
; RV64IFD-NEXT: fneg.d ft1, ft0 ; RV64IFD-NEXT: fneg.d fa1, fa0
; RV64IFD-NEXT: feq.d a0, ft0, ft1 ; RV64IFD-NEXT: feq.d a0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fneg_d: ; RV32I-LABEL: fneg_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a1
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and. ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define double @fabs_d(double %a, double %b) nounwind { define double @fabs_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fabs_d: ; RV32IFD-LABEL: fabs_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fabs.d ft1, ft0 ; RV32IFD-NEXT: fabs.d fa1, fa0
; RV32IFD-NEXT: fadd.d fa0, ft1, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fabs_d: ; RV64IFD-LABEL: fabs_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fabs.d ft1, ft0 ; RV64IFD-NEXT: fabs.d fa1, fa0
; RV64IFD-NEXT: fadd.d fa0, ft1, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa1, fa0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fabs_d: ; RV32I-LABEL: fabs_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a1
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c) %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1 ret double %1
} }
define double @fmsub_d(double %a, double %b, double %c) nounwind { define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmsub_d: ; RV32IFD-LABEL: fmsub_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmsub_d: ; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fmsub_d: ; RV32I-LABEL: fmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %b, double %negc) %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
ret double %1 ret double %1
} }
define double @fnmadd_d(double %a, double %b, double %c) nounwind { define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d: ; RV32IFD-LABEL: fnmadd_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0 ; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d: ; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa1, ft0 ; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_d: ; RV32I-LABEL: fnmadd_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %negc) %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)
ret double %1 ret double %1
} }
define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_2: ; RV32IFD-LABEL: fnmadd_d_2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0 ; RV32IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d_2: ; RV64IFD-LABEL: fnmadd_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fnmadd.d fa0, ft1, fa0, ft0 ; RV64IFD-NEXT: fnmadd.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_d_2: ; RV32I-LABEL: fnmadd_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %negc) %1 = call double @llvm.fma.f64(double %a, double %negb, double %negc)
ret double %1 ret double %1
} }
define double @fnmsub_d(double %a, double %b, double %c) nounwind { define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d: ; RV32IFD-LABEL: fnmsub_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d: ; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2 ; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_d: ; RV32I-LABEL: fnmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%nega = fsub double -0.0, %a_ %nega = fsub double -0.0, %a_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %c) %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
ret double %1 ret double %1
} }
define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d_2: ; RV32IFD-LABEL: fnmsub_d_2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d_2: ; RV64IFD-LABEL: fnmsub_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fnmsub.d fa0, ft0, fa0, fa2 ; RV64IFD-NEXT: fnmsub.d fa0, fa1, fa0, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_d_2: ; RV32I-LABEL: fnmsub_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract double %a, %b %1 = fmul contract double %a, %b
%2 = fadd contract double %1, %c %2 = fadd contract double %1, %c
ret double %2 ret double %2
} }
define double @fmsub_d_contract(double %a, double %b, double %c) nounwind { define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmsub_d_contract: ; RV32IFD-LABEL: fmsub_d_contract:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV32IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmsub_d_contract: ; RV64IFD-LABEL: fmsub_d_contract:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, ft0 ; RV64IFD-NEXT: fmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fmsub_d_contract: ; RV32I-LABEL: fmsub_d_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract double %a, %b %1 = fmul contract double %a, %b
%2 = fsub contract double %1, %c_ %2 = fsub contract double %1, %c_
ret double %2 ret double %2
} }
define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind { define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_contract: ; RV32IFD-LABEL: fnmadd_d_contract:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fadd.d ft2, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV32IFD-NEXT: fadd.d fa2, fa2, fa3
; RV32IFD-NEXT: fnmadd.d fa0, ft1, ft2, ft0 ; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d_contract: ; RV64IFD-LABEL: fnmadd_d_contract:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fadd.d ft2, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fadd.d ft0, fa2, ft0 ; RV64IFD-NEXT: fadd.d fa2, fa2, fa3
; RV64IFD-NEXT: fnmadd.d fa0, ft1, ft2, ft0 ; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_d_contract: ; RV32I-LABEL: fnmadd_d_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%2 = fneg double %1 %2 = fneg double %1
%3 = fsub contract double %2, %c_ %3 = fsub contract double %2, %c_
ret double %3 ret double %3
} }
define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind { define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d_contract: ; RV32IFD-LABEL: fnmsub_d_contract:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa3, zero
; RV32IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa3
; RV32IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV32IFD-NEXT: fadd.d fa1, fa1, fa3
; RV32IFD-NEXT: fnmsub.d fa0, ft1, ft0, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d_contract: ; RV64IFD-LABEL: fnmsub_d_contract:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, zero ; RV64IFD-NEXT: fmv.d.x fa3, zero
; RV64IFD-NEXT: fadd.d ft1, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa3
; RV64IFD-NEXT: fadd.d ft0, fa1, ft0 ; RV64IFD-NEXT: fadd.d fa1, fa1, fa3
; RV64IFD-NEXT: fnmsub.d fa0, ft1, ft0, fa2 ; RV64IFD-NEXT: fnmsub.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_d_contract: ; RV32I-LABEL: fnmsub_d_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IFD-LABEL: fcopysign_fneg: ; RV32IFD-LABEL: fcopysign_fneg:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld fa1, 8(sp)
; RV32IFD-NEXT: fsgnjn.d ft0, ft1, ft0 ; RV32IFD-NEXT: fsgnjn.d fa0, fa1, fa0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64I-LABEL: fcopysign_fneg: ; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: srli a1, a1, 63 ; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: fcopysign_fneg: ; RV64IFD-LABEL: fcopysign_fneg:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: li a2, -1 ; RV64IFD-NEXT: li a2, -1
; RV64IFD-NEXT: slli a2, a2, 63 ; RV64IFD-NEXT: slli a2, a2, 63
; RV64IFD-NEXT: xor a1, a1, a2 ; RV64IFD-NEXT: xor a1, a1, a2
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x fa0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x fa1, a0
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0 ; RV64IFD-NEXT: fsgnj.d fa0, fa1, fa0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fneg double %b %1 = fneg double %b
%2 = call double @llvm.copysign.f64(double %a, double %1) %2 = call double @llvm.copysign.f64(double %a, double %1)
ret double %2 ret double %2
} }

llvm/test/CodeGen/RISCV/double-calling-conv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; Basic correctness checks for calling convention lowering for RV32D. This can ; Basic correctness checks for calling convention lowering for RV32D. This can
; be somewhat error-prone for soft-float RV32D due to the fact that f64 is legal ; be somewhat error-prone for soft-float RV32D due to the fact that f64 is legal
; but i64 is not, and there is no instruction to move values directly between ; but i64 is not, and there is no instruction to move values directly between
; the GPRs and 64-bit FPRs. ; the GPRs and 64-bit FPRs.
define double @callee_double_inreg(double %a, double %b) nounwind { define double @callee_double_inreg(double %a, double %b) nounwind {
; RV32IFD-LABEL: callee_double_inreg: ; RV32IFD-LABEL: callee_double_inreg:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld fa1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = fadd double %a, %b %1 = fadd double %a, %b
ret double %1 ret double %1
} }
Show All 21 Lines
define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind { define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind {
; RV32IFD-LABEL: callee_double_split_reg_stack: ; RV32IFD-LABEL: callee_double_split_reg_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: sw a7, 8(sp) ; RV32IFD-NEXT: sw a7, 8(sp)
; RV32IFD-NEXT: sw a0, 12(sp) ; RV32IFD-NEXT: sw a0, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: sw a5, 8(sp) ; RV32IFD-NEXT: sw a5, 8(sp)
; RV32IFD-NEXT: sw a6, 12(sp) ; RV32IFD-NEXT: sw a6, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld fa1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = fadd double %d, %e %1 = fadd double %d, %e
ret double %1 ret double %1
} }
Show All 22 Lines; RV32IFD-NEXT: ret
%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72) %1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
ret double %1 ret double %1
} }
define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind { define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind {
; RV32IFD-LABEL: callee_double_stack: ; RV32IFD-LABEL: callee_double_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fld ft0, 24(sp) ; RV32IFD-NEXT: fld fa0, 24(sp)
; RV32IFD-NEXT: fld ft1, 16(sp) ; RV32IFD-NEXT: fld fa1, 16(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = fadd double %e, %f %1 = fadd double %e, %f
ret double %1 ret double %1
} }
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llvm/test/CodeGen/RISCV/double-convert-strict.ll

Show First 20 Lines • Show All 627 Lines • ▼ Show 20 Lines
} }
declare double @llvm.experimental.constrained.uitofp.f64.i16(i16, metadata, metadata) declare double @llvm.experimental.constrained.uitofp.f64.i16(i16, metadata, metadata)
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind { define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_w_demanded_bits: ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: addi a0, a0, 1
; RV32IFD-NEXT: fcvt.d.w ft0, a0 ; RV32IFD-NEXT: fcvt.d.w fa0, a0
; RV32IFD-NEXT: fsd ft0, 0(a1) ; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_w_demanded_bits: ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: fcvt.d.w ft0, a0 ; RV64IFD-NEXT: fcvt.d.w fa0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1) ; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_d_w_demanded_bits: ; RV32I-LABEL: fcvt_d_w_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 33 Lines; RV64I-NEXT: ret
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind { define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_wu_demanded_bits: ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: addi a0, a0, 1
; RV32IFD-NEXT: fcvt.d.wu ft0, a0 ; RV32IFD-NEXT: fcvt.d.wu fa0, a0
; RV32IFD-NEXT: fsd ft0, 0(a1) ; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits: ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: fcvt.d.wu ft0, a0 ; RV64IFD-NEXT: fcvt.d.wu fa0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1) ; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_d_wu_demanded_bits: ; RV32I-LABEL: fcvt_d_wu_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 35 Lines

llvm/test/CodeGen/RISCV/double-convert.ll

Show First 20 Lines • Show All 609 Lines • ▼ Show 20 Lines
define i64 @fcvt_l_d_sat(double %a) nounwind { define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d_sat: ; RV32IFD-LABEL: fcvt_l_d_sat:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI12_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB12_2 ; RV32IFD-NEXT: bnez s0, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB12_2: # %start ; RV32IFD-NEXT: .LBB12_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI12_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB12_9 ; RV32IFD-NEXT: beqz a3, .LBB12_9
; RV32IFD-NEXT: # %bb.3: # %start ; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB12_10 ; RV32IFD-NEXT: beqz a2, .LBB12_10
; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: .LBB12_4: # %start
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB12_11 ; RV32IFD-NEXT: beqz s0, .LBB12_11
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines
define i64 @fcvt_lu_d_sat(double %a) nounwind { define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d_sat: ; RV32IFD-LABEL: fcvt_lu_d_sat:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB14_2 ; RV32IFD-NEXT: bnez s0, .LBB14_2
; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB14_2: # %start ; RV32IFD-NEXT: .LBB14_2: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB14_7 ; RV32IFD-NEXT: beqz a4, .LBB14_7
; RV32IFD-NEXT: # %bb.3: # %start ; RV32IFD-NEXT: # %bb.3: # %start
; RV32IFD-NEXT: beqz s0, .LBB14_8 ; RV32IFD-NEXT: beqz s0, .LBB14_8
; RV32IFD-NEXT: .LBB14_4: # %start ; RV32IFD-NEXT: .LBB14_4: # %start
; RV32IFD-NEXT: bnez a4, .LBB14_6 ; RV32IFD-NEXT: bnez a4, .LBB14_6
; RV32IFD-NEXT: .LBB14_5: # %start ; RV32IFD-NEXT: .LBB14_5: # %start
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Linesstart:
ret i64 %0 ret i64 %0
} }
declare i64 @llvm.fptoui.sat.i64.f64(double) declare i64 @llvm.fptoui.sat.i64.f64(double)
define i64 @fmv_x_d(double %a, double %b) nounwind { define i64 @fmv_x_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fmv_x_d: ; RV32IFD-LABEL: fmv_x_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd fa0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmv_x_d: ; RV64IFD-LABEL: fmv_x_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fmv_x_d: ; RV32I-LABEL: fmv_x_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; Ensure fmv.w.x is generated even for a soft double calling convention ; Ensure fmv.w.x is generated even for a soft double calling convention
; RV32IFD-LABEL: fmv_d_x: ; RV32IFD-LABEL: fmv_d_x:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld fa0, 0(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld fa1, 8(sp)
; RV32IFD-NEXT: fadd.d fa0, ft1, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa1, fa0
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmv_d_x: ; RV64IFD-LABEL: fmv_d_x:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x fa0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x fa1, a1
; RV64IFD-NEXT: fadd.d fa0, ft0, ft1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fmv_d_x: ; RV32I-LABEL: fmv_d_x:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret double %1 ret double %1
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind { define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_w_demanded_bits: ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: addi a0, a0, 1
; RV32IFD-NEXT: fcvt.d.w ft0, a0 ; RV32IFD-NEXT: fcvt.d.w fa0, a0
; RV32IFD-NEXT: fsd ft0, 0(a1) ; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_w_demanded_bits: ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: fcvt.d.w ft0, a0 ; RV64IFD-NEXT: fcvt.d.w fa0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1) ; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_d_w_demanded_bits: ; RV32I-LABEL: fcvt_d_w_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 33 Lines; RV64I-NEXT: ret
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind { define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_wu_demanded_bits: ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1 ; RV32IFD-NEXT: addi a0, a0, 1
; RV32IFD-NEXT: fcvt.d.wu ft0, a0 ; RV32IFD-NEXT: fcvt.d.wu fa0, a0
; RV32IFD-NEXT: fsd ft0, 0(a1) ; RV32IFD-NEXT: fsd fa0, 0(a1)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits: ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1 ; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: fcvt.d.wu ft0, a0 ; RV64IFD-NEXT: fcvt.d.wu fa0, a0
; RV64IFD-NEXT: fsd ft0, 0(a1) ; RV64IFD-NEXT: fsd fa0, 0(a1)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_d_wu_demanded_bits: ; RV32I-LABEL: fcvt_d_wu_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i16: ; RV32IFD-LABEL: fcvt_w_s_sat_i16:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB26_2 ; RV32IFD-NEXT: beqz a0, .LBB26_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI26_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0) ; RV32IFD-NEXT: fld fa2, %lo(.LCPI26_1)(a0)
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV32IFD-NEXT: fmin.d fa0, fa0, fa2
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB26_2: # %start ; RV32IFD-NEXT: .LBB26_2: # %start
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i16: ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB26_2 ; RV64IFD-NEXT: beqz a0, .LBB26_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0) ; RV64IFD-NEXT: fld fa1, %lo(.LCPI26_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0) ; RV64IFD-NEXT: fld fa2, %lo(.LCPI26_1)(a0)
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV64IFD-NEXT: fmin.d fa0, fa0, fa2
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB26_2: # %start ; RV64IFD-NEXT: .LBB26_2: # %start
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui double %a to i16 %1 = fptoui double %a to i16
ret i16 %1 ret i16 %1
} }
define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_s_sat_i16: ; RV32IFD-LABEL: fcvt_wu_s_sat_i16:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI28_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI28_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI28_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI28_0)(a0)
; RV32IFD-NEXT: fcvt.d.w ft1, zero ; RV32IFD-NEXT: fcvt.d.w fa2, zero
; RV32IFD-NEXT: fmax.d ft1, fa0, ft1 ; RV32IFD-NEXT: fmax.d fa0, fa0, fa2
; RV32IFD-NEXT: fmin.d ft0, ft1, ft0 ; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_wu_s_sat_i16: ; RV64IFD-LABEL: fcvt_wu_s_sat_i16:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI28_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI28_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI28_0)(a0) ; RV64IFD-NEXT: fld fa1, %lo(.LCPI28_0)(a0)
; RV64IFD-NEXT: fmv.d.x ft1, zero ; RV64IFD-NEXT: fmv.d.x fa2, zero
; RV64IFD-NEXT: fmax.d ft1, fa0, ft1 ; RV64IFD-NEXT: fmax.d fa0, fa0, fa2
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0 ; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i16: ; RV32I-LABEL: fcvt_wu_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i8: ; RV32IFD-LABEL: fcvt_w_s_sat_i8:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB30_2 ; RV32IFD-NEXT: beqz a0, .LBB30_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI30_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0) ; RV32IFD-NEXT: fld fa2, %lo(.LCPI30_1)(a0)
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV32IFD-NEXT: fmin.d fa0, fa0, fa2
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB30_2: # %start ; RV32IFD-NEXT: .LBB30_2: # %start
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i8: ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB30_2 ; RV64IFD-NEXT: beqz a0, .LBB30_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; RV64IFD-NEXT: fld fa1, %lo(.LCPI30_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0) ; RV64IFD-NEXT: fld fa2, %lo(.LCPI30_1)(a0)
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV64IFD-NEXT: fmin.d fa0, fa0, fa2
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB30_2: # %start ; RV64IFD-NEXT: .LBB30_2: # %start
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
} }
define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
; ;
; ;
; RV32IFD-LABEL: fcvt_wu_s_sat_i8: ; RV32IFD-LABEL: fcvt_wu_s_sat_i8:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: lui a0, %hi(.LCPI32_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI32_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI32_0)(a0)
; RV32IFD-NEXT: fcvt.d.w ft1, zero ; RV32IFD-NEXT: fcvt.d.w fa2, zero
; RV32IFD-NEXT: fmax.d ft1, fa0, ft1 ; RV32IFD-NEXT: fmax.d fa0, fa0, fa2
; RV32IFD-NEXT: fmin.d ft0, ft1, ft0 ; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_wu_s_sat_i8: ; RV64IFD-LABEL: fcvt_wu_s_sat_i8:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI32_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI32_0)(a0) ; RV64IFD-NEXT: fld fa1, %lo(.LCPI32_0)(a0)
; RV64IFD-NEXT: fmv.d.x ft1, zero ; RV64IFD-NEXT: fmv.d.x fa2, zero
; RV64IFD-NEXT: fmax.d ft1, fa0, ft1 ; RV64IFD-NEXT: fmax.d fa0, fa0, fa2
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0 ; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i8: ; RV32I-LABEL: fcvt_wu_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-imm.ll

Show All 17 Lines
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
ret double 3.1415926535897931159979634685441851615905761718750 ret double 3.1415926535897931159979634685441851615905761718750
} }
define double @double_imm_op(double %a) nounwind { define double @double_imm_op(double %a) nounwind {
; RV32IFD-LABEL: double_imm_op: ; RV32IFD-LABEL: double_imm_op:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: fadd.d fa0, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: double_imm_op: ; RV64IFD-LABEL: double_imm_op:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0) ; RV64IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV64IFD-NEXT: fadd.d fa0, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fadd double %a, 1.0 %1 = fadd double %a, 1.0
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s ; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s ; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
define dso_local double @fld(double *%a) nounwind { define dso_local double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld: ; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fld ft0, 0(a0) ; RV32IFD-NEXT: fld fa0, 0(a0)
; RV32IFD-NEXT: fld ft1, 24(a0) ; RV32IFD-NEXT: fld fa1, 24(a0)
; RV32IFD-NEXT: fadd.d fa0, ft0, ft1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld: ; RV64IFD-LABEL: fld:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fld ft0, 0(a0) ; RV64IFD-NEXT: fld fa0, 0(a0)
; RV64IFD-NEXT: fld ft1, 24(a0) ; RV64IFD-NEXT: fld fa1, 24(a0)
; RV64IFD-NEXT: fadd.d fa0, ft0, ft1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = load double, double* %a %1 = load double, double* %a
%2 = getelementptr double, double* %a, i32 3 %2 = getelementptr double, double* %a, i32 3
%3 = load double, double* %2 %3 = load double, double* %2
; Use both loaded values in an FP op to ensure an fld is used, even for the ; Use both loaded values in an FP op to ensure an fld is used, even for the
; soft float ABI ; soft float ABI
%4 = fadd double %1, %3 %4 = fadd double %1, %3
ret double %4 ret double %4
} }
define dso_local void @fsd(double *%a, double %b, double %c) nounwind { define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fsd: ; RV32IFD-LABEL: fsd:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fsd ft0, 0(a0) ; RV32IFD-NEXT: fsd fa0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 64(a0) ; RV32IFD-NEXT: fsd fa0, 64(a0)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fsd: ; RV64IFD-LABEL: fsd:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fsd ft0, 0(a0) ; RV64IFD-NEXT: fsd fa0, 0(a0)
; RV64IFD-NEXT: fsd ft0, 64(a0) ; RV64IFD-NEXT: fsd fa0, 64(a0)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even ; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
%1 = fadd double %b, %c %1 = fadd double %b, %c
store double %1, double* %a store double %1, double* %a
%2 = getelementptr double, double* %a, i32 8 %2 = getelementptr double, double* %a, i32 8
store double %1, double* %2 store double %1, double* %2
ret void ret void
} }
; Check load and store to a global ; Check load and store to a global
@G = dso_local global double 0.0 @G = dso_local global double 0.0
define dso_local double @fld_fsd_global(double %a, double %b) nounwind { define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; RV32IFD-LABEL: fld_fsd_global: ; RV32IFD-LABEL: fld_fsd_global:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fadd.d fa0, fa0, fa1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: lui a0, %hi(G) ; RV32IFD-NEXT: lui a0, %hi(G)
; RV32IFD-NEXT: fld ft0, %lo(G)(a0) ; RV32IFD-NEXT: fld fa1, %lo(G)(a0)
; RV32IFD-NEXT: fsd fa0, %lo(G)(a0) ; RV32IFD-NEXT: fsd fa0, %lo(G)(a0)
; RV32IFD-NEXT: addi a0, a0, %lo(G) ; RV32IFD-NEXT: addi a0, a0, %lo(G)
; RV32IFD-NEXT: fld ft0, 72(a0) ; RV32IFD-NEXT: fld fa1, 72(a0)
; RV32IFD-NEXT: fsd fa0, 72(a0) ; RV32IFD-NEXT: fsd fa0, 72(a0)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_fsd_global: ; RV64IFD-LABEL: fld_fsd_global:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fadd.d fa0, fa0, fa1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: lui a0, %hi(G) ; RV64IFD-NEXT: lui a0, %hi(G)
; RV64IFD-NEXT: fld ft0, %lo(G)(a0) ; RV64IFD-NEXT: fld fa1, %lo(G)(a0)
; RV64IFD-NEXT: fsd fa0, %lo(G)(a0) ; RV64IFD-NEXT: fsd fa0, %lo(G)(a0)
; RV64IFD-NEXT: addi a0, a0, %lo(G) ; RV64IFD-NEXT: addi a0, a0, %lo(G)
; RV64IFD-NEXT: fld ft0, 72(a0) ; RV64IFD-NEXT: fld fa1, 72(a0)
; RV64IFD-NEXT: fsd fa0, 72(a0) ; RV64IFD-NEXT: fsd fa0, 72(a0)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even ; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
%1 = fadd double %a, %b %1 = fadd double %a, %b
%2 = load volatile double, double* @G %2 = load volatile double, double* @G
store double %1, double* @G store double %1, double* @G
%3 = getelementptr double, double* @G, i32 9 %3 = getelementptr double, double* @G, i32 9
%4 = load volatile double, double* %3 %4 = load volatile double, double* %3
store double %1, double* %3 store double %1, double* %3
ret double %1 ret double %1
} }
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define dso_local double @fld_fsd_constant(double %a) nounwind { define dso_local double @fld_fsd_constant(double %a) nounwind {
; RV32IFD-LABEL: fld_fsd_constant: ; RV32IFD-LABEL: fld_fsd_constant:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lui a0, 912092 ; RV32IFD-NEXT: lui a0, 912092
; RV32IFD-NEXT: fld ft0, -273(a0) ; RV32IFD-NEXT: fld fa1, -273(a0)
; RV32IFD-NEXT: fadd.d fa0, fa0, ft0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fsd fa0, -273(a0) ; RV32IFD-NEXT: fsd fa0, -273(a0)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_fsd_constant: ; RV64IFD-LABEL: fld_fsd_constant:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, 228023 ; RV64IFD-NEXT: lui a0, 228023
; RV64IFD-NEXT: slli a0, a0, 2 ; RV64IFD-NEXT: slli a0, a0, 2
; RV64IFD-NEXT: fld ft0, -273(a0) ; RV64IFD-NEXT: fld fa1, -273(a0)
; RV64IFD-NEXT: fadd.d fa0, fa0, ft0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fsd fa0, -273(a0) ; RV64IFD-NEXT: fsd fa0, -273(a0)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = inttoptr i32 3735928559 to double* %1 = inttoptr i32 3735928559 to double*
%2 = load volatile double, double* %1 %2 = load volatile double, double* %1
%3 = fadd double %a, %2 %3 = fadd double %a, %2
store double %3, double* %1 store double %3, double* %1
ret double %3 ret double %3
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define dso_local double @fld_stack(double %a) nounwind { define dso_local double @fld_stack(double %a) nounwind {
; RV32IFD-LABEL: fld_stack: ; RV32IFD-LABEL: fld_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: addi a0, sp, 8 ; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead@plt ; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld fa0, 8(sp)
; RV32IFD-NEXT: fadd.d fa0, ft0, fs0 ; RV32IFD-NEXT: fadd.d fa0, fa0, fs0
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_stack: ; RV64IFD-LABEL: fld_stack:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32 ; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: addi a0, sp, 8 ; RV64IFD-NEXT: addi a0, sp, 8
; RV64IFD-NEXT: call notdead@plt ; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: fld ft0, 8(sp) ; RV64IFD-NEXT: fld fa0, 8(sp)
; RV64IFD-NEXT: fadd.d fa0, ft0, fs0 ; RV64IFD-NEXT: fadd.d fa0, fa0, fs0
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32 ; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = alloca double, align 8 %1 = alloca double, align 8
%2 = bitcast double* %1 to i8* %2 = bitcast double* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load double, double* %1 %3 = load double, double* %1
%4 = fadd double %3, %a ; force load in to FPR64 %4 = fadd double %3, %a ; force load in to FPR64
ret double %4 ret double %4
} }
define dso_local void @fsd_stack(double %a, double %b) nounwind { define dso_local void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-LABEL: fsd_stack: ; RV32IFD-LABEL: fsd_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: fsd fa0, 0(sp)
; RV32IFD-NEXT: mv a0, sp ; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call notdead@plt ; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fsd_stack: ; RV64IFD-LABEL: fsd_stack:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fadd.d ft0, fa0, fa1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: fsd ft0, 0(sp) ; RV64IFD-NEXT: fsd fa0, 0(sp)
; RV64IFD-NEXT: mv a0, sp ; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead@plt ; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fadd double %a, %b ; force store from FPR64 %1 = fadd double %a, %b ; force store from FPR64
%2 = alloca double, align 8 %2 = alloca double, align 8
store double %1, double* %2 store double %1, double* %2
%3 = bitcast double* %2 to i8* %3 = bitcast double* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
} }
; Test selection of store<ST4[%a], trunc to f32>, .. ; Test selection of store<ST4[%a], trunc to f32>, ..
define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone { define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
; RV32IFD-LABEL: fsd_trunc: ; RV32IFD-LABEL: fsd_trunc:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.s.d ft0, fa0 ; RV32IFD-NEXT: fcvt.s.d fa0, fa0
; RV32IFD-NEXT: fsw ft0, 0(a0) ; RV32IFD-NEXT: fsw fa0, 0(a0)
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fsd_trunc: ; RV64IFD-LABEL: fsd_trunc:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.s.d ft0, fa0 ; RV64IFD-NEXT: fcvt.s.d fa0, fa0
; RV64IFD-NEXT: fsw ft0, 0(a0) ; RV64IFD-NEXT: fsw fa0, 0(a0)
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fptrunc double %b to float %1 = fptrunc double %b to float
store float %1, float* %a, align 4 store float %1, float* %a, align 4
ret void ret void
} }

llvm/test/CodeGen/RISCV/double-previous-failure.ll

Show All 16 Lines
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: li a0, 0
; RV32IFD-NEXT: call test@plt ; RV32IFD-NEXT: call test@plt
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld fa0, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: fld fa2, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: flt.d a0, fa0, fa1
; RV32IFD-NEXT: not a0, a0 ; RV32IFD-NEXT: not a0, a0
; RV32IFD-NEXT: flt.d a1, ft2, ft0 ; RV32IFD-NEXT: flt.d a1, fa2, fa0
; RV32IFD-NEXT: xori a1, a1, 1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: and a0, a0, a1 ; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB1_2 ; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: .LBB1_2: # %if.end ; RV32IFD-NEXT: .LBB1_2: # %if.end
; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: li a0, 0
; RV32IFD-NEXT: call exit@plt ; RV32IFD-NEXT: call exit@plt
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llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

Show All 30 Lines
; RV32IFD-LABEL: test_floor_si64: ; RV32IFD-LABEL: test_floor_si64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor@plt ; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB1_2 ; RV32IFD-NEXT: bnez s0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB1_2: ; RV32IFD-NEXT: .LBB1_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB1_9 ; RV32IFD-NEXT: beqz a3, .LBB1_9
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB1_10 ; RV32IFD-NEXT: beqz a2, .LBB1_10
; RV32IFD-NEXT: .LBB1_4: ; RV32IFD-NEXT: .LBB1_4:
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB1_11 ; RV32IFD-NEXT: beqz s0, .LBB1_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_floor_ui64: ; RV32IFD-LABEL: test_floor_ui64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor@plt ; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB3_2 ; RV32IFD-NEXT: bnez s0, .LBB3_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB3_2: ; RV32IFD-NEXT: .LBB3_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI3_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB3_7 ; RV32IFD-NEXT: beqz a4, .LBB3_7
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: beqz s0, .LBB3_8 ; RV32IFD-NEXT: beqz s0, .LBB3_8
; RV32IFD-NEXT: .LBB3_4: ; RV32IFD-NEXT: .LBB3_4:
; RV32IFD-NEXT: bnez a4, .LBB3_6 ; RV32IFD-NEXT: bnez a4, .LBB3_6
; RV32IFD-NEXT: .LBB3_5: ; RV32IFD-NEXT: .LBB3_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_ceil_si64: ; RV32IFD-LABEL: test_ceil_si64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt ; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI5_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB5_2 ; RV32IFD-NEXT: bnez s0, .LBB5_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: .LBB5_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI5_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB5_9 ; RV32IFD-NEXT: beqz a3, .LBB5_9
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB5_10 ; RV32IFD-NEXT: beqz a2, .LBB5_10
; RV32IFD-NEXT: .LBB5_4: ; RV32IFD-NEXT: .LBB5_4:
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB5_11 ; RV32IFD-NEXT: beqz s0, .LBB5_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_ceil_ui64: ; RV32IFD-LABEL: test_ceil_ui64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt ; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB7_2 ; RV32IFD-NEXT: bnez s0, .LBB7_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB7_2: ; RV32IFD-NEXT: .LBB7_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI7_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI7_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB7_7 ; RV32IFD-NEXT: beqz a4, .LBB7_7
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: beqz s0, .LBB7_8 ; RV32IFD-NEXT: beqz s0, .LBB7_8
; RV32IFD-NEXT: .LBB7_4: ; RV32IFD-NEXT: .LBB7_4:
; RV32IFD-NEXT: bnez a4, .LBB7_6 ; RV32IFD-NEXT: bnez a4, .LBB7_6
; RV32IFD-NEXT: .LBB7_5: ; RV32IFD-NEXT: .LBB7_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_trunc_si64: ; RV32IFD-LABEL: test_trunc_si64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt ; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI9_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB9_2 ; RV32IFD-NEXT: bnez s0, .LBB9_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB9_2: ; RV32IFD-NEXT: .LBB9_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI9_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB9_9 ; RV32IFD-NEXT: beqz a3, .LBB9_9
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB9_10 ; RV32IFD-NEXT: beqz a2, .LBB9_10
; RV32IFD-NEXT: .LBB9_4: ; RV32IFD-NEXT: .LBB9_4:
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB9_11 ; RV32IFD-NEXT: beqz s0, .LBB9_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_trunc_ui64: ; RV32IFD-LABEL: test_trunc_ui64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt ; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB11_2 ; RV32IFD-NEXT: bnez s0, .LBB11_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB11_2: ; RV32IFD-NEXT: .LBB11_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB11_7 ; RV32IFD-NEXT: beqz a4, .LBB11_7
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: beqz s0, .LBB11_8 ; RV32IFD-NEXT: beqz s0, .LBB11_8
; RV32IFD-NEXT: .LBB11_4: ; RV32IFD-NEXT: .LBB11_4:
; RV32IFD-NEXT: bnez a4, .LBB11_6 ; RV32IFD-NEXT: bnez a4, .LBB11_6
; RV32IFD-NEXT: .LBB11_5: ; RV32IFD-NEXT: .LBB11_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_round_si64: ; RV32IFD-LABEL: test_round_si64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call round@plt ; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI13_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB13_2 ; RV32IFD-NEXT: bnez s0, .LBB13_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB13_2: ; RV32IFD-NEXT: .LBB13_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI13_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB13_9 ; RV32IFD-NEXT: beqz a3, .LBB13_9
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB13_10 ; RV32IFD-NEXT: beqz a2, .LBB13_10
; RV32IFD-NEXT: .LBB13_4: ; RV32IFD-NEXT: .LBB13_4:
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB13_11 ; RV32IFD-NEXT: beqz s0, .LBB13_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_round_ui64: ; RV32IFD-LABEL: test_round_ui64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call round@plt ; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB15_2 ; RV32IFD-NEXT: bnez s0, .LBB15_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB15_2: ; RV32IFD-NEXT: .LBB15_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI15_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI15_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB15_7 ; RV32IFD-NEXT: beqz a4, .LBB15_7
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: beqz s0, .LBB15_8 ; RV32IFD-NEXT: beqz s0, .LBB15_8
; RV32IFD-NEXT: .LBB15_4: ; RV32IFD-NEXT: .LBB15_4:
; RV32IFD-NEXT: bnez a4, .LBB15_6 ; RV32IFD-NEXT: bnez a4, .LBB15_6
; RV32IFD-NEXT: .LBB15_5: ; RV32IFD-NEXT: .LBB15_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_roundeven_si64: ; RV32IFD-LABEL: test_roundeven_si64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt ; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_0)(a0) ; RV32IFD-NEXT: fld fa1, %lo(.LCPI17_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa1, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: bnez s0, .LBB17_2 ; RV32IFD-NEXT: bnez s0, .LBB17_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a2, 0 ; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: .LBB17_2: ; RV32IFD-NEXT: .LBB17_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI17_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_1)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI17_1)(a0)
; RV32IFD-NEXT: flt.d a3, ft0, fs0 ; RV32IFD-NEXT: flt.d a3, fa0, fs0
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a3, .LBB17_9 ; RV32IFD-NEXT: beqz a3, .LBB17_9
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: feq.d a2, fs0, fs0 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: beqz a2, .LBB17_10 ; RV32IFD-NEXT: beqz a2, .LBB17_10
; RV32IFD-NEXT: .LBB17_4: ; RV32IFD-NEXT: .LBB17_4:
; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: beqz s0, .LBB17_11 ; RV32IFD-NEXT: beqz s0, .LBB17_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IFD-LABEL: test_roundeven_ui64: ; RV32IFD-LABEL: test_roundeven_ui64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt ; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w fa0, zero
; RV32IFD-NEXT: fle.d s0, ft0, fa0 ; RV32IFD-NEXT: fle.d s0, fa0, fs0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: mv a3, a0 ; RV32IFD-NEXT: mv a3, a0
; RV32IFD-NEXT: bnez s0, .LBB19_2 ; RV32IFD-NEXT: bnez s0, .LBB19_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a3, 0 ; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: .LBB19_2: ; RV32IFD-NEXT: .LBB19_2:
; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI19_0)(a0) ; RV32IFD-NEXT: fld fa0, %lo(.LCPI19_0)(a0)
; RV32IFD-NEXT: flt.d a4, ft0, fs0 ; RV32IFD-NEXT: flt.d a4, fa0, fs0
; RV32IFD-NEXT: li a2, -1 ; RV32IFD-NEXT: li a2, -1
; RV32IFD-NEXT: li a0, -1 ; RV32IFD-NEXT: li a0, -1
; RV32IFD-NEXT: beqz a4, .LBB19_7 ; RV32IFD-NEXT: beqz a4, .LBB19_7
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: beqz s0, .LBB19_8 ; RV32IFD-NEXT: beqz s0, .LBB19_8
; RV32IFD-NEXT: .LBB19_4: ; RV32IFD-NEXT: .LBB19_4:
; RV32IFD-NEXT: bnez a4, .LBB19_6 ; RV32IFD-NEXT: bnez a4, .LBB19_6
; RV32IFD-NEXT: .LBB19_5: ; RV32IFD-NEXT: .LBB19_5:
Show All 38 Lines

llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @func(double %d, i32 %n) nounwind { define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func: ; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld fa0, 16(sp)
; RV32IFD-NEXT: beqz a2, .LBB0_2 ; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1 ; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: fsd fa0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func@plt ; RV32IFD-NEXT: call func@plt
; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld fa0, 16(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; RV32IFD-NEXT: .LBB0_2: # %return ; RV32IFD-NEXT: .LBB0_2: # %return
; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: fsd fa0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: func: ; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry ; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sext.w a2, a1 ; RV64IFD-NEXT: sext.w a2, a1
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x fa0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2 ; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addiw a1, a1, -1 ; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fsd fa0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func@plt ; RV64IFD-NEXT: call func@plt
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x fa0, a0
; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
; RV64IFD-NEXT: .LBB0_2: # %return ; RV64IFD-NEXT: .LBB0_2: # %return
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
entry: entry:
%cmp = icmp eq i32 %n, 0 %cmp = icmp eq i32 %n, 0
br i1 %cmp, label %return, label %if.else br i1 %cmp, label %return, label %if.else
if.else: if.else:
%sub = add i32 %n, -1 %sub = add i32 %n, -1
%call = tail call double @func(double %d, i32 %sub) %call = tail call double @func(double %d, i32 %sub)
%add = fadd double %call, %d %add = fadd double %call, %d
ret double %add ret double %add
return: return:
ret double %d ret double %d
} }

llvm/test/CodeGen/RISCV/float-arith-strict.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp { define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fmsub_s: ; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmsub_s: ; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fmsub_s: ; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 38 Lines; RV64I-NEXT: ret
%negc = fneg float %c_ %negc = fneg float %c_
%1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp { define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmadd_s: ; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 ; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s: ; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 ; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s: ; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fneg float %c_ %negc = fneg float %c_
%1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp { define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmadd_s_2: ; RV32IF-LABEL: fnmadd_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 ; RV32IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s_2: ; RV64IF-LABEL: fnmadd_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 ; RV64IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_2: ; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fneg float %c_ %negc = fneg float %c_
%1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp { define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmsub_s: ; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 ; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s: ; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 ; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s: ; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 36 Lines; RV64I-NEXT: ret
%nega = fneg float %a_ %nega = fneg float %a_
%1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp { define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fnmsub_s_2: ; RV32IF-LABEL: fnmsub_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 ; RV32IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s_2: ; RV64IF-LABEL: fnmsub_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 ; RV64IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s_2: ; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-arith.ll

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret float %1 ret float %1
} }
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_s(float %a, float %b) nounwind { define i32 @fneg_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fneg_s: ; RV32IF-LABEL: fneg_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa0
; RV32IF-NEXT: fneg.s ft1, ft0 ; RV32IF-NEXT: fneg.s fa1, fa0
; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fneg_s: ; RV64IF-LABEL: fneg_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa0
; RV64IF-NEXT: fneg.s ft1, ft0 ; RV64IF-NEXT: fneg.s fa1, fa0
; RV64IF-NEXT: feq.s a0, ft0, ft1 ; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fneg_s: ; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
Show All 25 Lines; RV64I-NEXT: ret
ret i32 %4 ret i32 %4
} }
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define float @fsgnjn_s(float %a, float %b) nounwind { define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fsgnjn_s: ; RV32IF-LABEL: fsgnjn_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa1, fa0, fa1
; RV32IF-NEXT: fsgnjn.s fa0, fa0, ft0 ; RV32IF-NEXT: fsgnjn.s fa0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fsgnjn_s: ; RV64IF-LABEL: fsgnjn_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa1, fa0, fa1
; RV64IF-NEXT: fsgnjn.s fa0, fa0, ft0 ; RV64IF-NEXT: fsgnjn.s fa0, fa0, fa1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fsgnjn_s: ; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
Show All 34 Lines
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and. ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define float @fabs_s(float %a, float %b) nounwind { define float @fabs_s(float %a, float %b) nounwind {
; RV32IF-LABEL: fabs_s: ; RV32IF-LABEL: fabs_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fabs.s ft1, ft0 ; RV32IF-NEXT: fabs.s fa1, fa0
; RV32IF-NEXT: fadd.s fa0, ft1, ft0 ; RV32IF-NEXT: fadd.s fa0, fa1, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fabs_s: ; RV64IF-LABEL: fabs_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fabs.s ft1, ft0 ; RV64IF-NEXT: fabs.s fa1, fa0
; RV64IF-NEXT: fadd.s fa0, ft1, ft0 ; RV64IF-NEXT: fadd.s fa0, fa1, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fabs_s: ; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c) %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
define float @fmsub_s(float %a, float %b, float %c) nounwind { define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s: ; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmsub_s: ; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fmsub_s: ; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 38 Lines; RV64I-NEXT: ret
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc) %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmadd_s(float %a, float %b, float %c) nounwind { define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s: ; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 ; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s: ; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0 ; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s: ; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %negc) %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_2: ; RV32IF-LABEL: fnmadd_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 ; RV32IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s_2: ; RV64IF-LABEL: fnmadd_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0 ; RV64IF-NEXT: fnmadd.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_2: ; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %negc) %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
ret float %1 ret float %1
} }
define float @fnmsub_s(float %a, float %b, float %c) nounwind { define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s: ; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 ; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s: ; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 ; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s: ; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 36 Lines; RV64I-NEXT: ret
%nega = fsub float -0.0, %a_ %nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c) %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
ret float %1 ret float %1
} }
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_2: ; RV32IF-LABEL: fnmsub_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 ; RV32IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s_2: ; RV64IF-LABEL: fnmsub_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2 ; RV64IF-NEXT: fnmsub.s fa0, fa1, fa0, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s_2: ; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract float %a, %b %1 = fmul contract float %a, %b
%2 = fadd contract float %1, %c %2 = fadd contract float %1, %c
ret float %2 ret float %2
} }
define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s_contract: ; RV32IF-LABEL: fmsub_s_contract:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmsub_s_contract: ; RV64IF-LABEL: fmsub_s_contract:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0 ; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fmsub_s_contract: ; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract float %a, %b %1 = fmul contract float %a, %b
%2 = fsub contract float %1, %c_ %2 = fsub contract float %1, %c_
ret float %2 ret float %2
} }
define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_contract: ; RV32IF-LABEL: fnmadd_s_contract:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fadd.s ft2, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fadd.s ft0, fa2, ft0 ; RV32IF-NEXT: fadd.s fa2, fa2, fa3
; RV32IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 ; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s_contract: ; RV64IF-LABEL: fnmadd_s_contract:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fadd.s ft2, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s fa2, fa2, fa3
; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 ; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_contract: ; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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%2 = fneg float %1 %2 = fneg float %1
%3 = fsub contract float %2, %c_ %3 = fsub contract float %2, %c_
ret float %3 ret float %3
} }
define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_contract: ; RV32IF-LABEL: fnmsub_s_contract:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa3, zero
; RV32IF-NEXT: fadd.s ft1, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa3
; RV32IF-NEXT: fadd.s ft0, fa1, ft0 ; RV32IF-NEXT: fadd.s fa1, fa1, fa3
; RV32IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 ; RV32IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s_contract: ; RV64IF-LABEL: fnmsub_s_contract:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x fa3, zero
; RV64IF-NEXT: fadd.s ft1, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa3
; RV64IF-NEXT: fadd.s ft0, fa1, ft0 ; RV64IF-NEXT: fadd.s fa1, fa1, fa3
; RV64IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2 ; RV64IF-NEXT: fnmsub.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s_contract: ; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

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; floating-point register, if the machine has them, and the result of ; floating-point register, if the machine has them, and the result of
; the bitwise operation is then needed in a floating-point register. ; the bitwise operation is then needed in a floating-point register.
; This should mean the optimisations will fire even if you're using the ; This should mean the optimisations will fire even if you're using the
; soft-float ABI on a machine with hardware floating-point support. ; soft-float ABI on a machine with hardware floating-point support.
define float @bitcast_and(float %a1, float %a2) nounwind { define float @bitcast_and(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_and: ; RV32F-LABEL: bitcast_and:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1 ; RV32F-NEXT: fmv.w.x fa0, a1
; RV32F-NEXT: fmv.w.x ft1, a0 ; RV32F-NEXT: fmv.w.x fa1, a0
; RV32F-NEXT: fadd.s ft0, ft1, ft0 ; RV32F-NEXT: fadd.s fa0, fa1, fa0
; RV32F-NEXT: fabs.s ft0, ft0 ; RV32F-NEXT: fabs.s fa0, fa0
; RV32F-NEXT: fadd.s ft0, ft1, ft0 ; RV32F-NEXT: fadd.s fa0, fa1, fa0
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_and: ; RV32FD-LABEL: bitcast_and:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1 ; RV32FD-NEXT: fmv.w.x fa0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0 ; RV32FD-NEXT: fmv.w.x fa1, a0
; RV32FD-NEXT: fadd.s ft0, ft1, ft0 ; RV32FD-NEXT: fadd.s fa0, fa1, fa0
; RV32FD-NEXT: fabs.s ft0, ft0 ; RV32FD-NEXT: fabs.s fa0, fa0
; RV32FD-NEXT: fadd.s ft0, ft1, ft0 ; RV32FD-NEXT: fadd.s fa0, fa1, fa0
; RV32FD-NEXT: fmv.x.w a0, ft0 ; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_and: ; RV64F-LABEL: bitcast_and:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1 ; RV64F-NEXT: fmv.w.x fa0, a1
; RV64F-NEXT: fmv.w.x ft1, a0 ; RV64F-NEXT: fmv.w.x fa1, a0
; RV64F-NEXT: fadd.s ft0, ft1, ft0 ; RV64F-NEXT: fadd.s fa0, fa1, fa0
; RV64F-NEXT: fabs.s ft0, ft0 ; RV64F-NEXT: fabs.s fa0, fa0
; RV64F-NEXT: fadd.s ft0, ft1, ft0 ; RV64F-NEXT: fadd.s fa0, fa1, fa0
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_and: ; RV64FD-LABEL: bitcast_and:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1 ; RV64FD-NEXT: fmv.w.x fa0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0 ; RV64FD-NEXT: fmv.w.x fa1, a0
; RV64FD-NEXT: fadd.s ft0, ft1, ft0 ; RV64FD-NEXT: fadd.s fa0, fa1, fa0
; RV64FD-NEXT: fabs.s ft0, ft0 ; RV64FD-NEXT: fabs.s fa0, fa0
; RV64FD-NEXT: fadd.s ft0, ft1, ft0 ; RV64FD-NEXT: fadd.s fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.w a0, ft0 ; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fadd float %a1, %a2 %a3 = fadd float %a1, %a2
%bc1 = bitcast float %a3 to i32 %bc1 = bitcast float %a3 to i32
%and = and i32 %bc1, 2147483647 %and = and i32 %bc1, 2147483647
%bc2 = bitcast i32 %and to float %bc2 = bitcast i32 %and to float
%a4 = fadd float %a1, %bc2 %a4 = fadd float %a1, %bc2
ret float %a4 ret float %a4
} }
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; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_and: ; RV32FD-LABEL: bitcast_double_and:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp) ; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp) ; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp) ; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp) ; RV32FD-NEXT: fld fa1, 8(sp)
; RV32FD-NEXT: fadd.d ft0, ft1, ft0 ; RV32FD-NEXT: fadd.d fa0, fa1, fa0
; RV32FD-NEXT: fabs.d ft0, ft0 ; RV32FD-NEXT: fabs.d fa0, fa0
; RV32FD-NEXT: fadd.d ft0, ft1, ft0 ; RV32FD-NEXT: fadd.d fa0, fa1, fa0
; RV32FD-NEXT: fsd ft0, 8(sp) ; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_and: ; RV64F-LABEL: bitcast_double_and:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __adddf3@plt ; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: slli a0, a0, 1 ; RV64F-NEXT: slli a0, a0, 1
; RV64F-NEXT: srli a1, a0, 1 ; RV64F-NEXT: srli a1, a0, 1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __adddf3@plt ; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_and: ; RV64FD-LABEL: bitcast_double_and:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x fa0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x fa1, a0
; RV64FD-NEXT: fadd.d ft0, ft1, ft0 ; RV64FD-NEXT: fadd.d fa0, fa1, fa0
; RV64FD-NEXT: fabs.d ft0, ft0 ; RV64FD-NEXT: fabs.d fa0, fa0
; RV64FD-NEXT: fadd.d ft0, ft1, ft0 ; RV64FD-NEXT: fadd.d fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.d a0, ft0 ; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fadd double %a1, %a2 %a3 = fadd double %a1, %a2
%bc1 = bitcast double %a3 to i64 %bc1 = bitcast double %a3 to i64
%and = and i64 %bc1, 9223372036854775807 %and = and i64 %bc1, 9223372036854775807
%bc2 = bitcast i64 %and to double %bc2 = bitcast i64 %and to double
%a4 = fadd double %a1, %bc2 %a4 = fadd double %a1, %bc2
ret double %a4 ret double %a4
} }
define float @bitcast_xor(float %a1, float %a2) nounwind { define float @bitcast_xor(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_xor: ; RV32F-LABEL: bitcast_xor:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1 ; RV32F-NEXT: fmv.w.x fa0, a1
; RV32F-NEXT: fmv.w.x ft1, a0 ; RV32F-NEXT: fmv.w.x fa1, a0
; RV32F-NEXT: fmul.s ft0, ft1, ft0 ; RV32F-NEXT: fmul.s fa0, fa1, fa0
; RV32F-NEXT: fneg.s ft0, ft0 ; RV32F-NEXT: fneg.s fa0, fa0
; RV32F-NEXT: fmul.s ft0, ft1, ft0 ; RV32F-NEXT: fmul.s fa0, fa1, fa0
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_xor: ; RV32FD-LABEL: bitcast_xor:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1 ; RV32FD-NEXT: fmv.w.x fa0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0 ; RV32FD-NEXT: fmv.w.x fa1, a0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0 ; RV32FD-NEXT: fmul.s fa0, fa1, fa0
; RV32FD-NEXT: fneg.s ft0, ft0 ; RV32FD-NEXT: fneg.s fa0, fa0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0 ; RV32FD-NEXT: fmul.s fa0, fa1, fa0
; RV32FD-NEXT: fmv.x.w a0, ft0 ; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_xor: ; RV64F-LABEL: bitcast_xor:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1 ; RV64F-NEXT: fmv.w.x fa0, a1
; RV64F-NEXT: fmv.w.x ft1, a0 ; RV64F-NEXT: fmv.w.x fa1, a0
; RV64F-NEXT: fmul.s ft0, ft1, ft0 ; RV64F-NEXT: fmul.s fa0, fa1, fa0
; RV64F-NEXT: fneg.s ft0, ft0 ; RV64F-NEXT: fneg.s fa0, fa0
; RV64F-NEXT: fmul.s ft0, ft1, ft0 ; RV64F-NEXT: fmul.s fa0, fa1, fa0
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_xor: ; RV64FD-LABEL: bitcast_xor:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1 ; RV64FD-NEXT: fmv.w.x fa0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0 ; RV64FD-NEXT: fmv.w.x fa1, a0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0 ; RV64FD-NEXT: fmul.s fa0, fa1, fa0
; RV64FD-NEXT: fneg.s ft0, ft0 ; RV64FD-NEXT: fneg.s fa0, fa0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0 ; RV64FD-NEXT: fmul.s fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.w a0, ft0 ; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2 %a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32 %bc1 = bitcast float %a3 to i32
%and = xor i32 %bc1, 2147483648 %and = xor i32 %bc1, 2147483648
%bc2 = bitcast i32 %and to float %bc2 = bitcast i32 %and to float
%a4 = fmul float %a1, %bc2 %a4 = fmul float %a1, %bc2
ret float %a4 ret float %a4
} }
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; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_xor: ; RV32FD-LABEL: bitcast_double_xor:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp) ; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp) ; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp) ; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp) ; RV32FD-NEXT: fld fa1, 8(sp)
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d fa0, fa1, fa0
; RV32FD-NEXT: fneg.d ft0, ft0 ; RV32FD-NEXT: fneg.d fa0, fa0
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d fa0, fa1, fa0
; RV32FD-NEXT: fsd ft0, 8(sp) ; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_xor: ; RV64F-LABEL: bitcast_double_xor:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3@plt ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: li a1, -1 ; RV64F-NEXT: li a1, -1
; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: xor a1, a0, a1 ; RV64F-NEXT: xor a1, a0, a1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3@plt ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_xor: ; RV64FD-LABEL: bitcast_double_xor:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x fa0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x fa1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d fa0, fa1, fa0
; RV64FD-NEXT: fneg.d ft0, ft0 ; RV64FD-NEXT: fneg.d fa0, fa0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.d a0, ft0 ; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2 %a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64 %bc1 = bitcast double %a3 to i64
%and = xor i64 %bc1, 9223372036854775808 %and = xor i64 %bc1, 9223372036854775808
%bc2 = bitcast i64 %and to double %bc2 = bitcast i64 %and to double
%a4 = fmul double %a1, %bc2 %a4 = fmul double %a1, %bc2
ret double %a4 ret double %a4
} }
define float @bitcast_or(float %a1, float %a2) nounwind { define float @bitcast_or(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_or: ; RV32F-LABEL: bitcast_or:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1 ; RV32F-NEXT: fmv.w.x fa0, a1
; RV32F-NEXT: fmv.w.x ft1, a0 ; RV32F-NEXT: fmv.w.x fa1, a0
; RV32F-NEXT: fmul.s ft0, ft1, ft0 ; RV32F-NEXT: fmul.s fa0, fa1, fa0
; RV32F-NEXT: fabs.s ft0, ft0 ; RV32F-NEXT: fabs.s fa0, fa0
; RV32F-NEXT: fneg.s ft0, ft0 ; RV32F-NEXT: fneg.s fa0, fa0
; RV32F-NEXT: fmul.s ft0, ft1, ft0 ; RV32F-NEXT: fmul.s fa0, fa1, fa0
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_or: ; RV32FD-LABEL: bitcast_or:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1 ; RV32FD-NEXT: fmv.w.x fa0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0 ; RV32FD-NEXT: fmv.w.x fa1, a0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0 ; RV32FD-NEXT: fmul.s fa0, fa1, fa0
; RV32FD-NEXT: fabs.s ft0, ft0 ; RV32FD-NEXT: fabs.s fa0, fa0
; RV32FD-NEXT: fneg.s ft0, ft0 ; RV32FD-NEXT: fneg.s fa0, fa0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0 ; RV32FD-NEXT: fmul.s fa0, fa1, fa0
; RV32FD-NEXT: fmv.x.w a0, ft0 ; RV32FD-NEXT: fmv.x.w a0, fa0
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_or: ; RV64F-LABEL: bitcast_or:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1 ; RV64F-NEXT: fmv.w.x fa0, a1
; RV64F-NEXT: fmv.w.x ft1, a0 ; RV64F-NEXT: fmv.w.x fa1, a0
; RV64F-NEXT: fmul.s ft0, ft1, ft0 ; RV64F-NEXT: fmul.s fa0, fa1, fa0
; RV64F-NEXT: fabs.s ft0, ft0 ; RV64F-NEXT: fabs.s fa0, fa0
; RV64F-NEXT: fneg.s ft0, ft0 ; RV64F-NEXT: fneg.s fa0, fa0
; RV64F-NEXT: fmul.s ft0, ft1, ft0 ; RV64F-NEXT: fmul.s fa0, fa1, fa0
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_or: ; RV64FD-LABEL: bitcast_or:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1 ; RV64FD-NEXT: fmv.w.x fa0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0 ; RV64FD-NEXT: fmv.w.x fa1, a0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0 ; RV64FD-NEXT: fmul.s fa0, fa1, fa0
; RV64FD-NEXT: fabs.s ft0, ft0 ; RV64FD-NEXT: fabs.s fa0, fa0
; RV64FD-NEXT: fneg.s ft0, ft0 ; RV64FD-NEXT: fneg.s fa0, fa0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0 ; RV64FD-NEXT: fmul.s fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.w a0, ft0 ; RV64FD-NEXT: fmv.x.w a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2 %a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32 %bc1 = bitcast float %a3 to i32
%and = or i32 %bc1, 2147483648 %and = or i32 %bc1, 2147483648
%bc2 = bitcast i32 %and to float %bc2 = bitcast i32 %and to float
%a4 = fmul float %a1, %bc2 %a4 = fmul float %a1, %bc2
ret float %a4 ret float %a4
} }
Show All 20 Lines
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_or: ; RV32FD-LABEL: bitcast_double_or:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp) ; RV32FD-NEXT: fld fa0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp) ; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp) ; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp) ; RV32FD-NEXT: fld fa1, 8(sp)
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d fa0, fa1, fa0
; RV32FD-NEXT: fabs.d ft0, ft0 ; RV32FD-NEXT: fabs.d fa0, fa0
; RV32FD-NEXT: fneg.d ft0, ft0 ; RV32FD-NEXT: fneg.d fa0, fa0
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d fa0, fa1, fa0
; RV32FD-NEXT: fsd ft0, 8(sp) ; RV32FD-NEXT: fsd fa0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_or: ; RV64F-LABEL: bitcast_double_or:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3@plt ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: li a1, -1 ; RV64F-NEXT: li a1, -1
; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: or a1, a0, a1 ; RV64F-NEXT: or a1, a0, a1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3@plt ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_or: ; RV64FD-LABEL: bitcast_double_or:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x fa0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x fa1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d fa0, fa1, fa0
; RV64FD-NEXT: fabs.d ft0, ft0 ; RV64FD-NEXT: fabs.d fa0, fa0
; RV64FD-NEXT: fneg.d ft0, ft0 ; RV64FD-NEXT: fneg.d fa0, fa0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d fa0, fa1, fa0
; RV64FD-NEXT: fmv.x.d a0, ft0 ; RV64FD-NEXT: fmv.x.d a0, fa0
; RV64FD-NEXT: ret ; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2 %a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64 %bc1 = bitcast double %a3 to i64
%and = or i64 %bc1, 9223372036854775808 %and = or i64 %bc1, 9223372036854775808
%bc2 = bitcast i64 %and to double %bc2 = bitcast i64 %and to double
%a4 = fmul double %a1, %bc2 %a4 = fmul double %a1, %bc2
ret double %a4 ret double %a4
} }

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IF-LABEL: fcopysign_fneg: ; RV32IF-LABEL: fcopysign_fneg:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: xor a1, a1, a2 ; RV32IF-NEXT: xor a1, a1, a2
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x fa0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x fa1, a0
; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0 ; RV32IF-NEXT: fsgnj.s fa0, fa1, fa0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64I-LABEL: fcopysign_fneg: ; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33 ; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IF-LABEL: fcopysign_fneg: ; RV64IF-LABEL: fcopysign_fneg:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x fa0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x fa1, a0
; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0 ; RV64IF-NEXT: fsgnjn.s fa0, fa1, fa0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fneg float %b %1 = fneg float %b
%2 = call float @llvm.copysign.f32(float %a, float %1) %2 = call float @llvm.copysign.f32(float %a, float %1)
ret float %2 ret float %2
} }

llvm/test/CodeGen/RISCV/float-convert-strict.ll

Show First 20 Lines • Show All 559 Lines • ▼ Show 20 Lines
} }
declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metadata) declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metadata)
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind { define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_w_demanded_bits: ; RV32IF-LABEL: fcvt_s_w_demanded_bits:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: addi a0, a0, 1
; RV32IF-NEXT: fcvt.s.w ft0, a0 ; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: fsw ft0, 0(a1) ; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_w_demanded_bits: ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_s_w_demanded_bits: ; RV32I-LABEL: fcvt_s_w_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 32 Lines; RV64I-NEXT: ret
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind { define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_wu_demanded_bits: ; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: addi a0, a0, 1
; RV32IF-NEXT: fcvt.s.wu ft0, a0 ; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: fsw ft0, 0(a1) ; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_wu_demanded_bits: ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_s_wu_demanded_bits: ; RV32I-LABEL: fcvt_s_wu_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 34 Lines

llvm/test/CodeGen/RISCV/float-convert.ll

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Linesstart:
%0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a) %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %0 ret i32 %0
} }
declare i32 @llvm.fptoui.sat.i32.f32(float) declare i32 @llvm.fptoui.sat.i32.f32(float)
define i32 @fmv_x_w(float %a, float %b) nounwind { define i32 @fmv_x_w(float %a, float %b) nounwind {
; RV32IF-LABEL: fmv_x_w: ; RV32IF-LABEL: fmv_x_w:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmv_x_w: ; RV64IF-LABEL: fmv_x_w:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fmv_x_w: ; RV32I-LABEL: fmv_x_w:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%a = load i32, i32* %p %a = load i32, i32* %p
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define float @fmv_w_x(i32 %a, i32 %b) nounwind { define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV32IF-LABEL: fmv_w_x: ; RV32IF-LABEL: fmv_w_x:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x fa0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x fa1, a1
; RV32IF-NEXT: fadd.s fa0, ft0, ft1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmv_w_x: ; RV64IF-LABEL: fmv_w_x:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x fa1, a1
; RV64IF-NEXT: fadd.s fa0, ft0, ft1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fmv_w_x: ; RV32I-LABEL: fmv_w_x:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define i64 @fcvt_l_s_sat(float %a) nounwind { define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_l_s_sat: ; RV32IF-LABEL: fcvt_l_s_sat:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI12_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI12_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB12_2 ; RV32IF-NEXT: bnez s0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %start ; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB12_2: # %start ; RV32IF-NEXT: .LBB12_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI12_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI12_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI12_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI12_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB12_9 ; RV32IF-NEXT: beqz a3, .LBB12_9
; RV32IF-NEXT: # %bb.3: # %start ; RV32IF-NEXT: # %bb.3: # %start
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB12_10 ; RV32IF-NEXT: beqz a2, .LBB12_10
; RV32IF-NEXT: .LBB12_4: # %start ; RV32IF-NEXT: .LBB12_4: # %start
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB12_11 ; RV32IF-NEXT: beqz s0, .LBB12_11
▲ Show 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
define i64 @fcvt_lu_s_sat(float %a) nounwind { define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_lu_s_sat: ; RV32IF-LABEL: fcvt_lu_s_sat:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB14_2 ; RV32IF-NEXT: bnez s0, .LBB14_2
; RV32IF-NEXT: # %bb.1: # %start ; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB14_2: # %start ; RV32IF-NEXT: .LBB14_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI14_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI14_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI14_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI14_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB14_7 ; RV32IF-NEXT: beqz a4, .LBB14_7
; RV32IF-NEXT: # %bb.3: # %start ; RV32IF-NEXT: # %bb.3: # %start
; RV32IF-NEXT: beqz s0, .LBB14_8 ; RV32IF-NEXT: beqz s0, .LBB14_8
; RV32IF-NEXT: .LBB14_4: # %start ; RV32IF-NEXT: .LBB14_4: # %start
; RV32IF-NEXT: bnez a4, .LBB14_6 ; RV32IF-NEXT: bnez a4, .LBB14_6
; RV32IF-NEXT: .LBB14_5: # %start ; RV32IF-NEXT: .LBB14_5: # %start
▲ Show 20 Lines • Show All 322 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret float %1 ret float %1
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind { define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_w_demanded_bits: ; RV32IF-LABEL: fcvt_s_w_demanded_bits:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: addi a0, a0, 1
; RV32IF-NEXT: fcvt.s.w ft0, a0 ; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: fsw ft0, 0(a1) ; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_w_demanded_bits: ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_s_w_demanded_bits: ; RV32I-LABEL: fcvt_s_w_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 32 Lines; RV64I-NEXT: ret
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind { define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_wu_demanded_bits: ; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1 ; RV32IF-NEXT: addi a0, a0, 1
; RV32IF-NEXT: fcvt.s.wu ft0, a0 ; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: fsw ft0, 0(a1) ; RV32IF-NEXT: fsw fa0, 0(a1)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_wu_demanded_bits: ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1 ; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fsw ft0, 0(a1) ; RV64IF-NEXT: fsw fa0, 0(a1)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_s_wu_demanded_bits: ; RV32I-LABEL: fcvt_s_wu_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind { define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat_i16: ; RV32IF-LABEL: fcvt_w_s_sat_i16:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0 ; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB24_2 ; RV32IF-NEXT: beqz a0, .LBB24_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI24_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI24_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI24_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI24_1)
; RV32IF-NEXT: flw ft1, %lo(.LCPI24_1)(a0) ; RV32IF-NEXT: flw fa2, %lo(.LCPI24_1)(a0)
; RV32IF-NEXT: fmax.s ft0, fa0, ft0 ; RV32IF-NEXT: fmax.s fa0, fa0, fa1
; RV32IF-NEXT: fmin.s ft0, ft0, ft1 ; RV32IF-NEXT: fmin.s fa0, fa0, fa2
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB24_2: # %start ; RV32IF-NEXT: .LBB24_2: # %start
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_w_s_sat_i16: ; RV64IF-LABEL: fcvt_w_s_sat_i16:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0 ; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB24_2 ; RV64IF-NEXT: beqz a0, .LBB24_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI24_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0) ; RV64IF-NEXT: flw fa1, %lo(.LCPI24_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI24_1) ; RV64IF-NEXT: lui a0, %hi(.LCPI24_1)
; RV64IF-NEXT: flw ft1, %lo(.LCPI24_1)(a0) ; RV64IF-NEXT: flw fa2, %lo(.LCPI24_1)(a0)
; RV64IF-NEXT: fmax.s ft0, fa0, ft0 ; RV64IF-NEXT: fmax.s fa0, fa0, fa1
; RV64IF-NEXT: fmin.s ft0, ft0, ft1 ; RV64IF-NEXT: fmin.s fa0, fa0, fa2
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: .LBB24_2: # %start ; RV64IF-NEXT: .LBB24_2: # %start
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui float %a to i16 %1 = fptoui float %a to i16
ret i16 %1 ret i16 %1
} }
define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_sat_i16: ; RV32IF-LABEL: fcvt_wu_s_sat_i16:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI26_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI26_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI26_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI26_0)(a0)
; RV32IF-NEXT: fmv.w.x ft1, zero ; RV32IF-NEXT: fmv.w.x fa2, zero
; RV32IF-NEXT: fmax.s ft1, fa0, ft1 ; RV32IF-NEXT: fmax.s fa0, fa0, fa2
; RV32IF-NEXT: fmin.s ft0, ft1, ft0 ; RV32IF-NEXT: fmin.s fa0, fa0, fa1
; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_wu_s_sat_i16: ; RV64IF-LABEL: fcvt_wu_s_sat_i16:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, %hi(.LCPI26_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI26_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI26_0)(a0) ; RV64IF-NEXT: flw fa1, %lo(.LCPI26_0)(a0)
; RV64IF-NEXT: fmv.w.x ft1, zero ; RV64IF-NEXT: fmv.w.x fa2, zero
; RV64IF-NEXT: fmax.s ft1, fa0, ft1 ; RV64IF-NEXT: fmax.s fa0, fa0, fa2
; RV64IF-NEXT: fmin.s ft0, ft1, ft0 ; RV64IF-NEXT: fmin.s fa0, fa0, fa1
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i16: ; RV32I-LABEL: fcvt_wu_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind { define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat_i8: ; RV32IF-LABEL: fcvt_w_s_sat_i8:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0 ; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB28_2 ; RV32IF-NEXT: beqz a0, .LBB28_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI28_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI28_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI28_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI28_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI28_1)
; RV32IF-NEXT: flw ft1, %lo(.LCPI28_1)(a0) ; RV32IF-NEXT: flw fa2, %lo(.LCPI28_1)(a0)
; RV32IF-NEXT: fmax.s ft0, fa0, ft0 ; RV32IF-NEXT: fmax.s fa0, fa0, fa1
; RV32IF-NEXT: fmin.s ft0, ft0, ft1 ; RV32IF-NEXT: fmin.s fa0, fa0, fa2
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB28_2: # %start ; RV32IF-NEXT: .LBB28_2: # %start
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_w_s_sat_i8: ; RV64IF-LABEL: fcvt_w_s_sat_i8:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0 ; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB28_2 ; RV64IF-NEXT: beqz a0, .LBB28_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI28_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI28_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0) ; RV64IF-NEXT: flw fa1, %lo(.LCPI28_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI28_1) ; RV64IF-NEXT: lui a0, %hi(.LCPI28_1)
; RV64IF-NEXT: flw ft1, %lo(.LCPI28_1)(a0) ; RV64IF-NEXT: flw fa2, %lo(.LCPI28_1)(a0)
; RV64IF-NEXT: fmax.s ft0, fa0, ft0 ; RV64IF-NEXT: fmax.s fa0, fa0, fa1
; RV64IF-NEXT: fmin.s ft0, ft0, ft1 ; RV64IF-NEXT: fmin.s fa0, fa0, fa2
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: .LBB28_2: # %start ; RV64IF-NEXT: .LBB28_2: # %start
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui float %a to i8 %1 = fptoui float %a to i8
ret i8 %1 ret i8 %1
} }
define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_sat_i8: ; RV32IF-LABEL: fcvt_wu_s_sat_i8:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI30_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI30_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI30_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI30_0)(a0)
; RV32IF-NEXT: fmv.w.x ft1, zero ; RV32IF-NEXT: fmv.w.x fa2, zero
; RV32IF-NEXT: fmax.s ft1, fa0, ft1 ; RV32IF-NEXT: fmax.s fa0, fa0, fa2
; RV32IF-NEXT: fmin.s ft0, ft1, ft0 ; RV32IF-NEXT: fmin.s fa0, fa0, fa1
; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_wu_s_sat_i8: ; RV64IF-LABEL: fcvt_wu_s_sat_i8:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, %hi(.LCPI30_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI30_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI30_0)(a0) ; RV64IF-NEXT: flw fa1, %lo(.LCPI30_0)(a0)
; RV64IF-NEXT: fmv.w.x ft1, zero ; RV64IF-NEXT: fmv.w.x fa2, zero
; RV64IF-NEXT: fmax.s ft1, fa0, ft1 ; RV64IF-NEXT: fmax.s fa0, fa0, fa2
; RV64IF-NEXT: fmin.s ft0, ft1, ft0 ; RV64IF-NEXT: fmin.s fa0, fa0, fa1
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i8: ; RV32I-LABEL: fcvt_wu_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-imm.ll

Show All 18 Lines
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
ret float 3.14159274101257324218750 ret float 3.14159274101257324218750
} }
define float @float_imm_op(float %a) nounwind { define float @float_imm_op(float %a) nounwind {
; RV32IF-LABEL: float_imm_op: ; RV32IF-LABEL: float_imm_op:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IF-NEXT: fadd.s fa0, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: float_imm_op: ; RV64IF-LABEL: float_imm_op:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV64IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV64IF-NEXT: fadd.s fa0, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, 1.0 %1 = fadd float %a, 1.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s ; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
define dso_local float @flw(float *%a) nounwind { define dso_local float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw: ; RV32IF-LABEL: flw:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 0(a0) ; RV32IF-NEXT: flw fa0, 0(a0)
; RV32IF-NEXT: flw ft1, 12(a0) ; RV32IF-NEXT: flw fa1, 12(a0)
; RV32IF-NEXT: fadd.s fa0, ft0, ft1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw: ; RV64IF-LABEL: flw:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: flw ft0, 0(a0) ; RV64IF-NEXT: flw fa0, 0(a0)
; RV64IF-NEXT: flw ft1, 12(a0) ; RV64IF-NEXT: flw fa1, 12(a0)
; RV64IF-NEXT: fadd.s fa0, ft0, ft1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = load float, float* %a %1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3 %2 = getelementptr float, float* %a, i32 3
%3 = load float, float* %2 %3 = load float, float* %2
; Use both loaded values in an FP op to ensure an flw is used, even for the ; Use both loaded values in an FP op to ensure an flw is used, even for the
; soft float ABI ; soft float ABI
%4 = fadd float %1, %3 %4 = fadd float %1, %3
ret float %4 ret float %4
} }
define dso_local void @fsw(float *%a, float %b, float %c) nounwind { define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
; Use %b and %c in an FP op to ensure floating point registers are used, even ; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
; RV32IF-LABEL: fsw: ; RV32IF-LABEL: fsw:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fsw ft0, 0(a0) ; RV32IF-NEXT: fsw fa0, 0(a0)
; RV32IF-NEXT: fsw ft0, 32(a0) ; RV32IF-NEXT: fsw fa0, 32(a0)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fsw: ; RV64IF-LABEL: fsw:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fsw ft0, 0(a0) ; RV64IF-NEXT: fsw fa0, 0(a0)
; RV64IF-NEXT: fsw ft0, 32(a0) ; RV64IF-NEXT: fsw fa0, 32(a0)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %b, %c %1 = fadd float %b, %c
store float %1, float* %a store float %1, float* %a
%2 = getelementptr float, float* %a, i32 8 %2 = getelementptr float, float* %a, i32 8
store float %1, float* %2 store float %1, float* %2
ret void ret void
} }
; Check load and store to a global ; Check load and store to a global
@G = dso_local global float 0.0 @G = dso_local global float 0.0
define dso_local float @flw_fsw_global(float %a, float %b) nounwind { define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
; Use %a and %b in an FP op to ensure floating point registers are used, even ; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI ; for the soft float ABI
; RV32IF-LABEL: flw_fsw_global: ; RV32IF-LABEL: flw_fsw_global:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s fa0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: lui a0, %hi(G) ; RV32IF-NEXT: lui a0, %hi(G)
; RV32IF-NEXT: flw ft0, %lo(G)(a0) ; RV32IF-NEXT: flw fa1, %lo(G)(a0)
; RV32IF-NEXT: fsw fa0, %lo(G)(a0) ; RV32IF-NEXT: fsw fa0, %lo(G)(a0)
; RV32IF-NEXT: addi a0, a0, %lo(G) ; RV32IF-NEXT: addi a0, a0, %lo(G)
; RV32IF-NEXT: flw ft0, 36(a0) ; RV32IF-NEXT: flw fa1, 36(a0)
; RV32IF-NEXT: fsw fa0, 36(a0) ; RV32IF-NEXT: fsw fa0, 36(a0)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_fsw_global: ; RV64IF-LABEL: flw_fsw_global:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s fa0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: lui a0, %hi(G) ; RV64IF-NEXT: lui a0, %hi(G)
; RV64IF-NEXT: flw ft0, %lo(G)(a0) ; RV64IF-NEXT: flw fa1, %lo(G)(a0)
; RV64IF-NEXT: fsw fa0, %lo(G)(a0) ; RV64IF-NEXT: fsw fa0, %lo(G)(a0)
; RV64IF-NEXT: addi a0, a0, %lo(G) ; RV64IF-NEXT: addi a0, a0, %lo(G)
; RV64IF-NEXT: flw ft0, 36(a0) ; RV64IF-NEXT: flw fa1, 36(a0)
; RV64IF-NEXT: fsw fa0, 36(a0) ; RV64IF-NEXT: fsw fa0, 36(a0)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = load volatile float, float* @G %2 = load volatile float, float* @G
store float %1, float* @G store float %1, float* @G
%3 = getelementptr float, float* @G, i32 9 %3 = getelementptr float, float* @G, i32 9
%4 = load volatile float, float* %3 %4 = load volatile float, float* %3
store float %1, float* %3 store float %1, float* %3
ret float %1 ret float %1
} }
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define dso_local float @flw_fsw_constant(float %a) nounwind { define dso_local float @flw_fsw_constant(float %a) nounwind {
; RV32IF-LABEL: flw_fsw_constant: ; RV32IF-LABEL: flw_fsw_constant:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, 912092 ; RV32IF-NEXT: lui a0, 912092
; RV32IF-NEXT: flw ft0, -273(a0) ; RV32IF-NEXT: flw fa1, -273(a0)
; RV32IF-NEXT: fadd.s fa0, fa0, ft0 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fsw fa0, -273(a0) ; RV32IF-NEXT: fsw fa0, -273(a0)
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_fsw_constant: ; RV64IF-LABEL: flw_fsw_constant:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, 228023 ; RV64IF-NEXT: lui a0, 228023
; RV64IF-NEXT: slli a0, a0, 2 ; RV64IF-NEXT: slli a0, a0, 2
; RV64IF-NEXT: flw ft0, -273(a0) ; RV64IF-NEXT: flw fa1, -273(a0)
; RV64IF-NEXT: fadd.s fa0, fa0, ft0 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fsw fa0, -273(a0) ; RV64IF-NEXT: fsw fa0, -273(a0)
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = inttoptr i32 3735928559 to float* %1 = inttoptr i32 3735928559 to float*
%2 = load volatile float, float* %1 %2 = load volatile float, float* %1
%3 = fadd float %a, %2 %3 = fadd float %a, %2
store float %3, float* %1 store float %3, float* %1
ret float %3 ret float %3
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define dso_local float @flw_stack(float %a) nounwind { define dso_local float @flw_stack(float %a) nounwind {
; RV32IF-LABEL: flw_stack: ; RV32IF-LABEL: flw_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: addi a0, sp, 4 ; RV32IF-NEXT: addi a0, sp, 4
; RV32IF-NEXT: call notdead@plt ; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: flw ft0, 4(sp) ; RV32IF-NEXT: flw fa0, 4(sp)
; RV32IF-NEXT: fadd.s fa0, ft0, fs0 ; RV32IF-NEXT: fadd.s fa0, fa0, fs0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_stack: ; RV64IF-LABEL: flw_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: mv a0, sp ; RV64IF-NEXT: mv a0, sp
; RV64IF-NEXT: call notdead@plt ; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: flw ft0, 0(sp) ; RV64IF-NEXT: flw fa0, 0(sp)
; RV64IF-NEXT: fadd.s fa0, ft0, fs0 ; RV64IF-NEXT: fadd.s fa0, fa0, fs0
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = alloca float, align 4 %1 = alloca float, align 4
%2 = bitcast float* %1 to i8* %2 = bitcast float* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load float, float* %1 %3 = load float, float* %1
%4 = fadd float %3, %a ; force load in to FPR32 %4 = fadd float %3, %a ; force load in to FPR32
ret float %4 ret float %4
} }
define dso_local void @fsw_stack(float %a, float %b) nounwind { define dso_local void @fsw_stack(float %a, float %b) nounwind {
; RV32IF-LABEL: fsw_stack: ; RV32IF-LABEL: fsw_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fadd.s ft0, fa0, fa1 ; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: fsw ft0, 8(sp) ; RV32IF-NEXT: fsw fa0, 8(sp)
; RV32IF-NEXT: addi a0, sp, 8 ; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead@plt ; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fsw_stack: ; RV64IF-LABEL: fsw_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fadd.s ft0, fa0, fa1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fsw ft0, 4(sp) ; RV64IF-NEXT: fsw fa0, 4(sp)
; RV64IF-NEXT: addi a0, sp, 4 ; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead@plt ; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b ; force store from FPR32 %1 = fadd float %a, %b ; force store from FPR32
%2 = alloca float, align 4 %2 = alloca float, align 4
store float %1, float* %2 store float %1, float* %2
%3 = bitcast float* %2 to i8* %3 = bitcast float* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
} }

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

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; RV32IF-LABEL: test_floor_si64: ; RV32IF-LABEL: test_floor_si64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call floorf@plt ; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB1_2 ; RV32IF-NEXT: bnez s0, .LBB1_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB1_2: ; RV32IF-NEXT: .LBB1_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI1_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI1_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB1_9 ; RV32IF-NEXT: beqz a3, .LBB1_9
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB1_10 ; RV32IF-NEXT: beqz a2, .LBB1_10
; RV32IF-NEXT: .LBB1_4: ; RV32IF-NEXT: .LBB1_4:
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB1_11 ; RV32IF-NEXT: beqz s0, .LBB1_11
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; RV32IF-LABEL: test_floor_ui64: ; RV32IF-LABEL: test_floor_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call floorf@plt ; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB3_2 ; RV32IF-NEXT: bnez s0, .LBB3_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB3_2: ; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB3_7 ; RV32IF-NEXT: beqz a4, .LBB3_7
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: beqz s0, .LBB3_8 ; RV32IF-NEXT: beqz s0, .LBB3_8
; RV32IF-NEXT: .LBB3_4: ; RV32IF-NEXT: .LBB3_4:
; RV32IF-NEXT: bnez a4, .LBB3_6 ; RV32IF-NEXT: bnez a4, .LBB3_6
; RV32IF-NEXT: .LBB3_5: ; RV32IF-NEXT: .LBB3_5:
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; RV32IF-LABEL: test_ceil_si64: ; RV32IF-LABEL: test_ceil_si64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call ceilf@plt ; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI5_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI5_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB5_2 ; RV32IF-NEXT: bnez s0, .LBB5_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB5_2: ; RV32IF-NEXT: .LBB5_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI5_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI5_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI5_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI5_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB5_9 ; RV32IF-NEXT: beqz a3, .LBB5_9
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB5_10 ; RV32IF-NEXT: beqz a2, .LBB5_10
; RV32IF-NEXT: .LBB5_4: ; RV32IF-NEXT: .LBB5_4:
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB5_11 ; RV32IF-NEXT: beqz s0, .LBB5_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_ceil_ui64: ; RV32IF-LABEL: test_ceil_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call ceilf@plt ; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB7_2 ; RV32IF-NEXT: bnez s0, .LBB7_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB7_2: ; RV32IF-NEXT: .LBB7_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB7_7 ; RV32IF-NEXT: beqz a4, .LBB7_7
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: beqz s0, .LBB7_8 ; RV32IF-NEXT: beqz s0, .LBB7_8
; RV32IF-NEXT: .LBB7_4: ; RV32IF-NEXT: .LBB7_4:
; RV32IF-NEXT: bnez a4, .LBB7_6 ; RV32IF-NEXT: bnez a4, .LBB7_6
; RV32IF-NEXT: .LBB7_5: ; RV32IF-NEXT: .LBB7_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_trunc_si64: ; RV32IF-LABEL: test_trunc_si64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call truncf@plt ; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI9_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI9_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB9_2 ; RV32IF-NEXT: bnez s0, .LBB9_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB9_2: ; RV32IF-NEXT: .LBB9_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI9_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI9_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI9_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI9_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB9_9 ; RV32IF-NEXT: beqz a3, .LBB9_9
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB9_10 ; RV32IF-NEXT: beqz a2, .LBB9_10
; RV32IF-NEXT: .LBB9_4: ; RV32IF-NEXT: .LBB9_4:
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB9_11 ; RV32IF-NEXT: beqz s0, .LBB9_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_trunc_ui64: ; RV32IF-LABEL: test_trunc_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call truncf@plt ; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB11_2 ; RV32IF-NEXT: bnez s0, .LBB11_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB11_2: ; RV32IF-NEXT: .LBB11_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI11_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI11_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB11_7 ; RV32IF-NEXT: beqz a4, .LBB11_7
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: beqz s0, .LBB11_8 ; RV32IF-NEXT: beqz s0, .LBB11_8
; RV32IF-NEXT: .LBB11_4: ; RV32IF-NEXT: .LBB11_4:
; RV32IF-NEXT: bnez a4, .LBB11_6 ; RV32IF-NEXT: bnez a4, .LBB11_6
; RV32IF-NEXT: .LBB11_5: ; RV32IF-NEXT: .LBB11_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_round_si64: ; RV32IF-LABEL: test_round_si64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundf@plt ; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI13_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI13_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI13_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB13_2 ; RV32IF-NEXT: bnez s0, .LBB13_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB13_2: ; RV32IF-NEXT: .LBB13_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI13_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI13_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI13_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI13_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB13_9 ; RV32IF-NEXT: beqz a3, .LBB13_9
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB13_10 ; RV32IF-NEXT: beqz a2, .LBB13_10
; RV32IF-NEXT: .LBB13_4: ; RV32IF-NEXT: .LBB13_4:
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB13_11 ; RV32IF-NEXT: beqz s0, .LBB13_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_round_ui64: ; RV32IF-LABEL: test_round_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundf@plt ; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB15_2 ; RV32IF-NEXT: bnez s0, .LBB15_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB15_2: ; RV32IF-NEXT: .LBB15_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI15_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI15_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB15_7 ; RV32IF-NEXT: beqz a4, .LBB15_7
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: beqz s0, .LBB15_8 ; RV32IF-NEXT: beqz s0, .LBB15_8
; RV32IF-NEXT: .LBB15_4: ; RV32IF-NEXT: .LBB15_4:
; RV32IF-NEXT: bnez a4, .LBB15_6 ; RV32IF-NEXT: bnez a4, .LBB15_6
; RV32IF-NEXT: .LBB15_5: ; RV32IF-NEXT: .LBB15_5:
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_roundeven_si64: ; RV32IF-LABEL: test_roundeven_si64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundevenf@plt ; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI17_0)(a0) ; RV32IF-NEXT: flw fa1, %lo(.LCPI17_0)(a0)
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa1, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: mv a2, a0 ; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB17_2 ; RV32IF-NEXT: bnez s0, .LBB17_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a2, 0 ; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB17_2: ; RV32IF-NEXT: .LBB17_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI17_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI17_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI17_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI17_1)(a0)
; RV32IF-NEXT: flt.s a3, ft0, fs0 ; RV32IF-NEXT: flt.s a3, fa0, fs0
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB17_9 ; RV32IF-NEXT: beqz a3, .LBB17_9
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: feq.s a2, fs0, fs0 ; RV32IF-NEXT: feq.s a2, fs0, fs0
; RV32IF-NEXT: beqz a2, .LBB17_10 ; RV32IF-NEXT: beqz a2, .LBB17_10
; RV32IF-NEXT: .LBB17_4: ; RV32IF-NEXT: .LBB17_4:
; RV32IF-NEXT: lui a4, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: beqz s0, .LBB17_11 ; RV32IF-NEXT: beqz s0, .LBB17_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: test_roundeven_ui64: ; RV32IF-LABEL: test_roundeven_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundevenf@plt ; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x fa0, zero
; RV32IF-NEXT: fle.s s0, ft0, fa0 ; RV32IF-NEXT: fle.s s0, fa0, fs0
; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: mv a3, a0 ; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB19_2 ; RV32IF-NEXT: bnez s0, .LBB19_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a3, 0 ; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB19_2: ; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI19_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI19_0)(a0)
; RV32IF-NEXT: flt.s a4, ft0, fs0 ; RV32IF-NEXT: flt.s a4, fa0, fs0
; RV32IF-NEXT: li a2, -1 ; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1 ; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB19_7 ; RV32IF-NEXT: beqz a4, .LBB19_7
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: beqz s0, .LBB19_8 ; RV32IF-NEXT: beqz s0, .LBB19_8
; RV32IF-NEXT: .LBB19_4: ; RV32IF-NEXT: .LBB19_4:
; RV32IF-NEXT: bnez a4, .LBB19_6 ; RV32IF-NEXT: bnez a4, .LBB19_6
; RV32IF-NEXT: .LBB19_5: ; RV32IF-NEXT: .LBB19_5:
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llvm/test/CodeGen/RISCV/fp-imm.ll

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; RV64D-NEXT: fmv.w.x fa0, zero ; RV64D-NEXT: fmv.w.x fa0, zero
; RV64D-NEXT: ret ; RV64D-NEXT: ret
ret float 0.0 ret float 0.0
} }
define float @f32_negative_zero(float *%pf) nounwind { define float @f32_negative_zero(float *%pf) nounwind {
; RV32F-LABEL: f32_negative_zero: ; RV32F-LABEL: f32_negative_zero:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, zero ; RV32F-NEXT: fmv.w.x fa0, zero
; RV32F-NEXT: fneg.s fa0, ft0 ; RV32F-NEXT: fneg.s fa0, fa0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32D-LABEL: f32_negative_zero: ; RV32D-LABEL: f32_negative_zero:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: fmv.w.x ft0, zero ; RV32D-NEXT: fmv.w.x fa0, zero
; RV32D-NEXT: fneg.s fa0, ft0 ; RV32D-NEXT: fneg.s fa0, fa0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64F-LABEL: f32_negative_zero: ; RV64F-LABEL: f32_negative_zero:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, zero ; RV64F-NEXT: fmv.w.x fa0, zero
; RV64F-NEXT: fneg.s fa0, ft0 ; RV64F-NEXT: fneg.s fa0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64D-LABEL: f32_negative_zero: ; RV64D-LABEL: f32_negative_zero:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: fmv.w.x ft0, zero ; RV64D-NEXT: fmv.w.x fa0, zero
; RV64D-NEXT: fneg.s fa0, ft0 ; RV64D-NEXT: fneg.s fa0, fa0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
ret float -0.0 ret float -0.0
} }
define double @f64_positive_zero(double *%pd) nounwind { define double @f64_positive_zero(double *%pd) nounwind {
; RV32F-LABEL: f64_positive_zero: ; RV32F-LABEL: f64_positive_zero:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: li a0, 0 ; RV32F-NEXT: li a0, 0
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; RV32F-LABEL: f64_negative_zero: ; RV32F-LABEL: f64_negative_zero:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, 524288 ; RV32F-NEXT: lui a1, 524288
; RV32F-NEXT: li a0, 0 ; RV32F-NEXT: li a0, 0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32D-LABEL: f64_negative_zero: ; RV32D-LABEL: f64_negative_zero:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: fcvt.d.w ft0, zero ; RV32D-NEXT: fcvt.d.w fa0, zero
; RV32D-NEXT: fneg.d fa0, ft0 ; RV32D-NEXT: fneg.d fa0, fa0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64F-LABEL: f64_negative_zero: ; RV64F-LABEL: f64_negative_zero:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: li a0, -1 ; RV64F-NEXT: li a0, -1
; RV64F-NEXT: slli a0, a0, 63 ; RV64F-NEXT: slli a0, a0, 63
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64D-LABEL: f64_negative_zero: ; RV64D-LABEL: f64_negative_zero:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: fmv.d.x ft0, zero ; RV64D-NEXT: fmv.d.x fa0, zero
; RV64D-NEXT: fneg.d fa0, ft0 ; RV64D-NEXT: fneg.d fa0, fa0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
ret double -0.0 ret double -0.0
} }

llvm/test/CodeGen/RISCV/half-arith-strict.ll

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines; RV64IZFH-NEXT: ret
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }
declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp { define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fmsub_h: ; RV32IZFH-LABEL: fmsub_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fmsub_h: ; RV64IZFH-LABEL: fmsub_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor %c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fneg half %c_ %negc = fneg half %c_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }
define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp { define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h: ; RV32IZFH-LABEL: fnmadd_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0 ; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmadd_h: ; RV64IZFH-LABEL: fnmadd_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0 ; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%a_ = fadd half 0.0, %a %a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c %c_ = fadd half 0.0, %c
%nega = fneg half %a_ %nega = fneg half %a_
%negc = fneg half %c_ %negc = fneg half %c_
%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }
define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp { define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h_2: ; RV32IZFH-LABEL: fnmadd_h_2:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 ; RV32IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmadd_h_2: ; RV64IZFH-LABEL: fnmadd_h_2:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 ; RV64IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%b_ = fadd half 0.0, %b %b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c %c_ = fadd half 0.0, %c
%negb = fneg half %b_ %negb = fneg half %b_
%negc = fneg half %c_ %negc = fneg half %c_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }
define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp { define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h: ; RV32IZFH-LABEL: fnmsub_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmsub_h: ; RV64IZFH-LABEL: fnmsub_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2 ; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%a_ = fadd half 0.0, %a %a_ = fadd half 0.0, %a
%nega = fneg half %a_ %nega = fneg half %a_
%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }
define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp { define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h_2: ; RV32IZFH-LABEL: fnmsub_h_2:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmsub_h_2: ; RV64IZFH-LABEL: fnmsub_h_2:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 ; RV64IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%b_ = fadd half 0.0, %b %b_ = fadd half 0.0, %b
%negb = fneg half %b_ %negb = fneg half %b_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1 ret half %1
} }

llvm/test/CodeGen/RISCV/half-arith.ll

Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret half %1 ret half %1
} }
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_s(half %a, half %b) nounwind { define i32 @fneg_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fneg_s: ; RV32IZFH-LABEL: fneg_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa0
; RV32IZFH-NEXT: fneg.h ft1, ft0 ; RV32IZFH-NEXT: fneg.h fa1, fa0
; RV32IZFH-NEXT: feq.h a0, ft0, ft1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fneg_s: ; RV64IZFH-LABEL: fneg_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa0
; RV64IZFH-NEXT: fneg.h ft1, ft0 ; RV64IZFH-NEXT: fneg.h fa1, fa0
; RV64IZFH-NEXT: feq.h a0, ft0, ft1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fneg_s: ; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i32 %4 ret i32 %4
} }
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor. ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define half @fsgnjn_s(half %a, half %b) nounwind { define half @fsgnjn_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fsgnjn_s: ; RV32IZFH-LABEL: fsgnjn_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h fa1, fa0, fa1
; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, ft0 ; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fsgnjn_s: ; RV64IZFH-LABEL: fsgnjn_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa1, fa0, fa1
; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, ft0 ; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fsgnjn_s: ; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
declare half @llvm.fabs.f16(half) declare half @llvm.fabs.f16(half)
; This function performs extra work to ensure that ; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and. ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define half @fabs_s(half %a, half %b) nounwind { define half @fabs_s(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fabs_s: ; RV32IZFH-LABEL: fabs_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: fabs.h ft1, ft0 ; RV32IZFH-NEXT: fabs.h fa1, fa0
; RV32IZFH-NEXT: fadd.h fa0, ft1, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa1, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fabs_s: ; RV64IZFH-LABEL: fabs_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fabs.h ft1, ft0 ; RV64IZFH-NEXT: fabs.h fa1, fa0
; RV64IZFH-NEXT: fadd.h fa0, ft1, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa1, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fabs_s: ; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c) %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
ret half %1 ret half %1
} }
define half @fmsub_s(half %a, half %b, half %c) nounwind { define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fmsub_s: ; RV32IZFH-LABEL: fmsub_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fmsub_s: ; RV64IZFH-LABEL: fmsub_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fmsub_s: ; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub half -0.0, %c_ %negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %b, half %negc) %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
ret half %1 ret half %1
} }
define half @fnmadd_s(half %a, half %b, half %c) nounwind { define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s: ; RV32IZFH-LABEL: fnmadd_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0 ; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmadd_s: ; RV64IZFH-LABEL: fnmadd_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0 ; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s: ; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub half -0.0, %c_ %negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %nega, half %b, half %negc) %1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
ret half %1 ret half %1
} }
define half @fnmadd_s_2(half %a, half %b, half %c) nounwind { define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s_2: ; RV32IZFH-LABEL: fnmadd_s_2:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 ; RV32IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmadd_s_2: ; RV64IZFH-LABEL: fnmadd_s_2:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 ; RV64IZFH-NEXT: fnmadd.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_2: ; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%negc = fsub half -0.0, %c_ %negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %negb, half %negc) %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
ret half %1 ret half %1
} }
define half @fnmsub_s(half %a, half %b, half %c) nounwind { define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s: ; RV32IZFH-LABEL: fnmsub_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmsub_s: ; RV64IZFH-LABEL: fnmsub_s:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2 ; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s: ; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%nega = fsub half -0.0, %a_ %nega = fsub half -0.0, %a_
%1 = call half @llvm.fma.f16(half %nega, half %b, half %c) %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
ret half %1 ret half %1
} }
define half @fnmsub_s_2(half %a, half %b, half %c) nounwind { define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s_2: ; RV32IZFH-LABEL: fnmsub_s_2:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmsub_s_2: ; RV64IZFH-LABEL: fnmsub_s_2:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 ; RV64IZFH-NEXT: fnmsub.h fa0, fa1, fa0, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s_2: ; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract half %a, %b %1 = fmul contract half %a, %b
%2 = fadd contract half %1, %c %2 = fadd contract half %1, %c
ret half %2 ret half %2
} }
define half @fmsub_s_contract(half %a, half %b, half %c) nounwind { define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fmsub_s_contract: ; RV32IZFH-LABEL: fmsub_s_contract:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fmsub_s_contract: ; RV64IZFH-LABEL: fmsub_s_contract:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0 ; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fmsub_s_contract: ; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fmul contract half %a, %b %1 = fmul contract half %a, %b
%2 = fsub contract half %1, %c_ %2 = fsub contract half %1, %c_
ret half %2 ret half %2
} }
define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind { define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s_contract: ; RV32IZFH-LABEL: fnmadd_s_contract:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fadd.h ft2, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV32IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0 ; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmadd_s_contract: ; RV64IZFH-LABEL: fnmadd_s_contract:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fadd.h ft2, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 ; RV64IZFH-NEXT: fadd.h fa2, fa2, fa3
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0 ; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_contract: ; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%2 = fneg half %1 %2 = fneg half %1
%3 = fsub contract half %2, %c_ %3 = fsub contract half %2, %c_
ret half %3 ret half %3
} }
define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind { define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s_contract: ; RV32IZFH-LABEL: fnmsub_s_contract:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa3, zero
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV32IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV32IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fnmsub_s_contract: ; RV64IZFH-LABEL: fnmsub_s_contract:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa3, zero
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa3
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0 ; RV64IZFH-NEXT: fadd.h fa1, fa1, fa3
; RV64IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2 ; RV64IZFH-NEXT: fnmsub.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fnmsub_s_contract: ; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 17 ; RV32I-NEXT: slli a0, a0, 17
; RV32I-NEXT: srli a0, a0, 17 ; RV32I-NEXT: srli a0, a0, 17
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IZFH-LABEL: fcopysign_fneg: ; RV32IZFH-LABEL: fcopysign_fneg:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, a1 ; RV32IZFH-NEXT: fmv.h.x fa0, a1
; RV32IZFH-NEXT: fmv.h.x ft1, a0 ; RV32IZFH-NEXT: fmv.h.x fa1, a0
; RV32IZFH-NEXT: fsgnjn.h ft0, ft1, ft0 ; RV32IZFH-NEXT: fsgnjn.h fa0, fa1, fa0
; RV32IZFH-NEXT: fmv.x.h a0, ft0 ; RV32IZFH-NEXT: fmv.x.h a0, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64I-LABEL: fcopysign_fneg: ; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: lui a2, 1048568 ; RV64I-NEXT: lui a2, 1048568
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 49 ; RV64I-NEXT: slli a0, a0, 49
; RV64I-NEXT: srli a0, a0, 49 ; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZFH-LABEL: fcopysign_fneg: ; RV64IZFH-LABEL: fcopysign_fneg:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, a1 ; RV64IZFH-NEXT: fmv.h.x fa0, a1
; RV64IZFH-NEXT: fmv.h.x ft1, a0 ; RV64IZFH-NEXT: fmv.h.x fa1, a0
; RV64IZFH-NEXT: fsgnjn.h ft0, ft1, ft0 ; RV64IZFH-NEXT: fsgnjn.h fa0, fa1, fa0
; RV64IZFH-NEXT: fmv.x.h a0, ft0 ; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fneg half %b %1 = fneg half %b
%2 = call half @llvm.copysign.f16(half %a, half %1) %2 = call half @llvm.copysign.f16(half %a, half %1)
ret half %2 ret half %2
} }

llvm/test/CodeGen/RISCV/half-convert-strict.ll

Show First 20 Lines • Show All 636 Lines • ▼ Show 20 Lines
} }
declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata) declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata)
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) { define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV32IZFH-LABEL: fcvt_h_w_demanded_bits: ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: addi a0, a0, 1
; RV32IZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: fsh ft0, 0(a1) ; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_w_demanded_bits: ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: addiw a0, a0, 1
; RV64IZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: fsh ft0, 0(a1) ; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits: ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: addi a0, a0, 1
; RV32IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
; RV32IDZFH-NEXT: fsh ft0, 0(a1) ; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits: ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1) ; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%3 = add i32 %0, 1 %3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
store half %4, half* %1, align 2 store half %4, half* %1, align 2
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) { define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: addi a0, a0, 1
; RV32IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: fsh ft0, 0(a1) ; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: addiw a0, a0, 1
; RV64IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: fsh ft0, 0(a1) ; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: addi a0, a0, 1
; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IDZFH-NEXT: fsh ft0, 0(a1) ; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1) ; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%3 = add i32 %0, 1 %3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
store half %4, half* %1, align 2 store half %4, half* %1, align 2
ret i32 %3 ret i32 %3
} }

llvm/test/CodeGen/RISCV/half-convert.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi half %a to i16 %1 = fptosi half %a to i16
ret i16 %1 ret i16 %1
} }
define i16 @fcvt_si_h_sat(half %a) nounwind { define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_si_h_sat: ; RV32IZFH-LABEL: fcvt_si_h_sat:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB1_2 ; RV32IZFH-NEXT: beqz a0, .LBB1_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0) ; RV32IZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB1_2: # %start ; RV32IZFH-NEXT: .LBB1_2: # %start
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_si_h_sat: ; RV64IZFH-LABEL: fcvt_si_h_sat:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB1_2 ; RV64IZFH-NEXT: beqz a0, .LBB1_2
; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_1) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_1)
; RV64IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0) ; RV64IZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB1_2: # %start ; RV64IZFH-NEXT: .LBB1_2: # %start
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_si_h_sat: ; RV32IDZFH-LABEL: fcvt_si_h_sat:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB1_2 ; RV32IDZFH-NEXT: beqz a0, .LBB1_2
; RV32IDZFH-NEXT: # %bb.1: ; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0) ; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB1_2: # %start ; RV32IDZFH-NEXT: .LBB1_2: # %start
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_si_h_sat: ; RV64IDZFH-LABEL: fcvt_si_h_sat:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB1_2 ; RV64IDZFH-NEXT: beqz a0, .LBB1_2
; RV64IDZFH-NEXT: # %bb.1: ; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_1) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0) ; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI1_1)(a0)
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB1_2: # %start ; RV64IDZFH-NEXT: .LBB1_2: # %start
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_si_h_sat: ; RV32I-LABEL: fcvt_si_h_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui half %a to i16 %1 = fptoui half %a to i16
ret i16 %1 ret i16 %1
} }
define i16 @fcvt_ui_h_sat(half %a) nounwind { define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_ui_h_sat: ; RV32IZFH-LABEL: fcvt_ui_h_sat:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: fmv.w.x ft2, zero ; RV32IZFH-NEXT: fmv.w.x fa2, zero
; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_ui_h_sat: ; RV64IZFH-LABEL: fcvt_ui_h_sat:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV64IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
; RV64IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: fmv.w.x ft2, zero ; RV64IZFH-NEXT: fmv.w.x fa2, zero
; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_ui_h_sat: ; RV32IDZFH-LABEL: fcvt_ui_h_sat:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: fmv.w.x ft2, zero ; RV32IDZFH-NEXT: fmv.w.x fa2, zero
; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_ui_h_sat: ; RV64IDZFH-LABEL: fcvt_ui_h_sat:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI3_0)(a0)
; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: fmv.w.x ft2, zero ; RV64IDZFH-NEXT: fmv.w.x fa2, zero
; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_ui_h_sat: ; RV32I-LABEL: fcvt_ui_h_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 575 Lines • ▼ Show 20 Lines
define i64 @fcvt_l_h_sat(half %a) nounwind { define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_l_h_sat: ; RV32IZFH-LABEL: fcvt_l_h_sat:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI10_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB10_2 ; RV32IZFH-NEXT: bnez s0, .LBB10_2
; RV32IZFH-NEXT: # %bb.1: # %start ; RV32IZFH-NEXT: # %bb.1: # %start
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB10_2: # %start ; RV32IZFH-NEXT: .LBB10_2: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI10_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB10_9 ; RV32IZFH-NEXT: beqz a3, .LBB10_9
; RV32IZFH-NEXT: # %bb.3: # %start ; RV32IZFH-NEXT: # %bb.3: # %start
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB10_10 ; RV32IZFH-NEXT: beqz a2, .LBB10_10
; RV32IZFH-NEXT: .LBB10_4: # %start ; RV32IZFH-NEXT: .LBB10_4: # %start
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB10_11 ; RV32IZFH-NEXT: beqz s0, .LBB10_11
Show All 36 Lines
; ;
; RV32IDZFH-LABEL: fcvt_l_h_sat: ; RV32IDZFH-LABEL: fcvt_l_h_sat:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI10_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IDZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IDZFH-NEXT: fle.s s0, fa1, fs0
; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call __fixsfdi@plt ; RV32IDZFH-NEXT: call __fixsfdi@plt
; RV32IDZFH-NEXT: mv a2, a0 ; RV32IDZFH-NEXT: mv a2, a0
; RV32IDZFH-NEXT: bnez s0, .LBB10_2 ; RV32IDZFH-NEXT: bnez s0, .LBB10_2
; RV32IDZFH-NEXT: # %bb.1: # %start ; RV32IDZFH-NEXT: # %bb.1: # %start
; RV32IDZFH-NEXT: li a2, 0 ; RV32IDZFH-NEXT: li a2, 0
; RV32IDZFH-NEXT: .LBB10_2: # %start ; RV32IDZFH-NEXT: .LBB10_2: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_1) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_1)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0) ; RV32IDZFH-NEXT: flw fa0, %lo(.LCPI10_1)(a0)
; RV32IDZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IDZFH-NEXT: flt.s a3, fa0, fs0
; RV32IDZFH-NEXT: li a0, -1 ; RV32IDZFH-NEXT: li a0, -1
; RV32IDZFH-NEXT: beqz a3, .LBB10_9 ; RV32IDZFH-NEXT: beqz a3, .LBB10_9
; RV32IDZFH-NEXT: # %bb.3: # %start ; RV32IDZFH-NEXT: # %bb.3: # %start
; RV32IDZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IDZFH-NEXT: feq.s a2, fs0, fs0
; RV32IDZFH-NEXT: beqz a2, .LBB10_10 ; RV32IDZFH-NEXT: beqz a2, .LBB10_10
; RV32IDZFH-NEXT: .LBB10_4: # %start ; RV32IDZFH-NEXT: .LBB10_4: # %start
; RV32IDZFH-NEXT: lui a4, 524288 ; RV32IDZFH-NEXT: lui a4, 524288
; RV32IDZFH-NEXT: beqz s0, .LBB10_11 ; RV32IDZFH-NEXT: beqz s0, .LBB10_11
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
define i64 @fcvt_lu_h_sat(half %a) nounwind { define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_lu_h_sat: ; RV32IZFH-LABEL: fcvt_lu_h_sat:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB12_2 ; RV32IZFH-NEXT: bnez s0, .LBB12_2
; RV32IZFH-NEXT: # %bb.1: # %start ; RV32IZFH-NEXT: # %bb.1: # %start
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB12_2: # %start ; RV32IZFH-NEXT: .LBB12_2: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI12_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB12_7 ; RV32IZFH-NEXT: beqz a4, .LBB12_7
; RV32IZFH-NEXT: # %bb.3: # %start ; RV32IZFH-NEXT: # %bb.3: # %start
; RV32IZFH-NEXT: beqz s0, .LBB12_8 ; RV32IZFH-NEXT: beqz s0, .LBB12_8
; RV32IZFH-NEXT: .LBB12_4: # %start ; RV32IZFH-NEXT: .LBB12_4: # %start
; RV32IZFH-NEXT: bnez a4, .LBB12_6 ; RV32IZFH-NEXT: bnez a4, .LBB12_6
; RV32IZFH-NEXT: .LBB12_5: # %start ; RV32IZFH-NEXT: .LBB12_5: # %start
Show All 24 Lines
; ;
; RV32IDZFH-LABEL: fcvt_lu_h_sat: ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IDZFH-NEXT: fmv.w.x ft0, zero ; RV32IDZFH-NEXT: fmv.w.x fa0, zero
; RV32IDZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IDZFH-NEXT: fle.s s0, fa0, fs0
; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call __fixunssfdi@plt ; RV32IDZFH-NEXT: call __fixunssfdi@plt
; RV32IDZFH-NEXT: mv a3, a0 ; RV32IDZFH-NEXT: mv a3, a0
; RV32IDZFH-NEXT: bnez s0, .LBB12_2 ; RV32IDZFH-NEXT: bnez s0, .LBB12_2
; RV32IDZFH-NEXT: # %bb.1: # %start ; RV32IDZFH-NEXT: # %bb.1: # %start
; RV32IDZFH-NEXT: li a3, 0 ; RV32IDZFH-NEXT: li a3, 0
; RV32IDZFH-NEXT: .LBB12_2: # %start ; RV32IDZFH-NEXT: .LBB12_2: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0) ; RV32IDZFH-NEXT: flw fa0, %lo(.LCPI12_0)(a0)
; RV32IDZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IDZFH-NEXT: flt.s a4, fa0, fs0
; RV32IDZFH-NEXT: li a2, -1 ; RV32IDZFH-NEXT: li a2, -1
; RV32IDZFH-NEXT: li a0, -1 ; RV32IDZFH-NEXT: li a0, -1
; RV32IDZFH-NEXT: beqz a4, .LBB12_7 ; RV32IDZFH-NEXT: beqz a4, .LBB12_7
; RV32IDZFH-NEXT: # %bb.3: # %start ; RV32IDZFH-NEXT: # %bb.3: # %start
; RV32IDZFH-NEXT: beqz s0, .LBB12_8 ; RV32IDZFH-NEXT: beqz s0, .LBB12_8
; RV32IDZFH-NEXT: .LBB12_4: # %start ; RV32IDZFH-NEXT: .LBB12_4: # %start
; RV32IDZFH-NEXT: bnez a4, .LBB12_6 ; RV32IDZFH-NEXT: bnez a4, .LBB12_6
; RV32IDZFH-NEXT: .LBB12_5: # %start ; RV32IDZFH-NEXT: .LBB12_5: # %start
▲ Show 20 Lines • Show All 886 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i16 %1 ret i16 %1
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) nounwind { define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) nounwind {
; RV32IZFH-LABEL: fcvt_h_w_demanded_bits: ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: addi a0, a0, 1
; RV32IZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: fsh ft0, 0(a1) ; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_w_demanded_bits: ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: addiw a0, a0, 1
; RV64IZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: fsh ft0, 0(a1) ; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits: ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: addi a0, a0, 1
; RV32IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
; RV32IDZFH-NEXT: fsh ft0, 0(a1) ; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits: ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.w ft0, a0 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1) ; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_h_w_demanded_bits: ; RV32I-LABEL: fcvt_h_w_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
Show All 34 Lines; RV64I-NEXT: ret
ret i32 %3 ret i32 %3
} }
; Make sure we select W version of addi on RV64. ; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) nounwind { define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) nounwind {
; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1 ; RV32IZFH-NEXT: addi a0, a0, 1
; RV32IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: fsh ft0, 0(a1) ; RV32IZFH-NEXT: fsh fa0, 0(a1)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addiw a0, a0, 1 ; RV64IZFH-NEXT: addiw a0, a0, 1
; RV64IZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: fsh ft0, 0(a1) ; RV64IZFH-NEXT: fsh fa0, 0(a1)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi a0, a0, 1 ; RV32IDZFH-NEXT: addi a0, a0, 1
; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IDZFH-NEXT: fsh ft0, 0(a1) ; RV32IDZFH-NEXT: fsh fa0, 0(a1)
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits: ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addiw a0, a0, 1 ; RV64IDZFH-NEXT: addiw a0, a0, 1
; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: fsh ft0, 0(a1) ; RV64IDZFH-NEXT: fsh fa0, 0(a1)
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_h_wu_demanded_bits: ; RV32I-LABEL: fcvt_h_wu_demanded_bits:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi half %a to i16 %1 = fptosi half %a to i16
ret i16 %1 ret i16 %1
} }
define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind { define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_s_sat_i16: ; RV32IZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB32_2 ; RV32IZFH-NEXT: beqz a0, .LBB32_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_1)
; RV32IZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0) ; RV32IZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB32_2: # %start ; RV32IZFH-NEXT: .LBB32_2: # %start
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_w_s_sat_i16: ; RV64IZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB32_2 ; RV64IZFH-NEXT: beqz a0, .LBB32_2
; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_1) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_1)
; RV64IZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0) ; RV64IZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB32_2: # %start ; RV64IZFH-NEXT: .LBB32_2: # %start
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i16: ; RV32IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB32_2 ; RV32IDZFH-NEXT: beqz a0, .LBB32_2
; RV32IDZFH-NEXT: # %bb.1: ; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_1) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0) ; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB32_2: # %start ; RV32IDZFH-NEXT: .LBB32_2: # %start
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i16: ; RV64IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB32_2 ; RV64IDZFH-NEXT: beqz a0, .LBB32_2
; RV64IDZFH-NEXT: # %bb.1: ; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI32_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_1) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI32_1)(a0) ; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI32_1)(a0)
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB32_2: # %start ; RV64IDZFH-NEXT: .LBB32_2: # %start
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui half %a to i16 %1 = fptoui half %a to i16
ret i16 %1 ret i16 %1
} }
define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_wu_s_sat_i16: ; RV32IZFH-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI34_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI34_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: fmv.w.x ft2, zero ; RV32IZFH-NEXT: fmv.w.x fa2, zero
; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_wu_s_sat_i16: ; RV64IZFH-LABEL: fcvt_wu_s_sat_i16:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI34_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI34_0)
; RV64IZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
; RV64IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: fmv.w.x ft2, zero ; RV64IZFH-NEXT: fmv.w.x fa2, zero
; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_wu_s_sat_i16: ; RV32IDZFH-LABEL: fcvt_wu_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI34_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI34_0)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: fmv.w.x ft2, zero ; RV32IDZFH-NEXT: fmv.w.x fa2, zero
; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_wu_s_sat_i16: ; RV64IDZFH-LABEL: fcvt_wu_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI34_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI34_0)
; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI34_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI34_0)(a0)
; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: fmv.w.x ft2, zero ; RV64IDZFH-NEXT: fmv.w.x fa2, zero
; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i16: ; RV32I-LABEL: fcvt_wu_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi half %a to i8 %1 = fptosi half %a to i8
ret i8 %1 ret i8 %1
} }
define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind { define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_s_sat_i8: ; RV32IZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IZFH-NEXT: feq.s a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB36_2 ; RV32IZFH-NEXT: beqz a0, .LBB36_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_1)
; RV32IZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0) ; RV32IZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IZFH-NEXT: .LBB36_2: # %start ; RV32IZFH-NEXT: .LBB36_2: # %start
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_w_s_sat_i8: ; RV64IZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IZFH-NEXT: feq.s a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB36_2 ; RV64IZFH-NEXT: beqz a0, .LBB36_2
; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_1) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_1)
; RV64IZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0) ; RV64IZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IZFH-NEXT: .LBB36_2: # %start ; RV64IZFH-NEXT: .LBB36_2: # %start
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i8: ; RV32IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV32IDZFH-NEXT: feq.s a0, fa0, fa0
; RV32IDZFH-NEXT: beqz a0, .LBB36_2 ; RV32IDZFH-NEXT: beqz a0, .LBB36_2
; RV32IDZFH-NEXT: # %bb.1: ; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_1) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0) ; RV32IDZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IDZFH-NEXT: .LBB36_2: # %start ; RV32IDZFH-NEXT: .LBB36_2: # %start
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i8: ; RV64IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0 ; RV64IDZFH-NEXT: feq.s a0, fa0, fa0
; RV64IDZFH-NEXT: beqz a0, .LBB36_2 ; RV64IDZFH-NEXT: beqz a0, .LBB36_2
; RV64IDZFH-NEXT: # %bb.1: ; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI36_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_1) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI36_1)(a0) ; RV64IDZFH-NEXT: flw fa2, %lo(.LCPI36_1)(a0)
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IDZFH-NEXT: .LBB36_2: # %start ; RV64IDZFH-NEXT: .LBB36_2: # %start
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = fptoui half %a to i8 %1 = fptoui half %a to i8
ret i8 %1 ret i8 %1
} }
define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_wu_s_sat_i8: ; RV32IZFH-LABEL: fcvt_wu_s_sat_i8:
; RV32IZFH: # %bb.0: # %start ; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: lui a0, %hi(.LCPI38_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI38_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: fmv.w.x ft2, zero ; RV32IZFH-NEXT: fmv.w.x fa2, zero
; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_wu_s_sat_i8: ; RV64IZFH-LABEL: fcvt_wu_s_sat_i8:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: lui a0, %hi(.LCPI38_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI38_0)
; RV64IZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0) ; RV64IZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
; RV64IZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: fmv.w.x ft2, zero ; RV64IZFH-NEXT: fmv.w.x fa2, zero
; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_wu_s_sat_i8: ; RV32IDZFH-LABEL: fcvt_wu_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI38_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI38_0)
; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0) ; RV32IDZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: fmv.w.x ft2, zero ; RV32IDZFH-NEXT: fmv.w.x fa2, zero
; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV32IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV32IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz ; RV32IDZFH-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_wu_s_sat_i8: ; RV64IDZFH-LABEL: fcvt_wu_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI38_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI38_0)
; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI38_0)(a0) ; RV64IDZFH-NEXT: flw fa1, %lo(.LCPI38_0)(a0)
; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IDZFH-NEXT: fmv.w.x ft2, zero ; RV64IDZFH-NEXT: fmv.w.x fa2, zero
; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2 ; RV64IDZFH-NEXT: fmax.s fa0, fa0, fa2
; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0 ; RV64IDZFH-NEXT: fmin.s fa0, fa0, fa1
; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IDZFH-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_s_sat_i8: ; RV32I-LABEL: fcvt_wu_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-fcmp.ll

Show All 40 Lines
; ;
; RV64IZFH-LABEL: fcmp_oeq: ; RV64IZFH-LABEL: fcmp_oeq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_oeq: ; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: feq.h a0, ft1, ft0 ; RV32I-NEXT: feq.h a0, fa1, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_oeq: ; RV64I-LABEL: fcmp_oeq:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: feq.h a0, ft1, ft0 ; RV64I-NEXT: feq.h a0, fa1, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp oeq half %a, %b %1 = fcmp oeq half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ogt(half %a, half %b) nounwind { define i32 @fcmp_ogt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ogt: ; RV32IZFH-LABEL: fcmp_ogt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ogt: ; RV64IZFH-LABEL: fcmp_ogt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ogt: ; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ogt: ; RV64I-LABEL: fcmp_ogt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ogt half %a, %b %1 = fcmp ogt half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_oge(half %a, half %b) nounwind { define i32 @fcmp_oge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_oge: ; RV32IZFH-LABEL: fcmp_oge:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_oge: ; RV64IZFH-LABEL: fcmp_oge:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_oge: ; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: fle.h a0, ft1, ft0 ; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_oge: ; RV64I-LABEL: fcmp_oge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: fle.h a0, ft1, ft0 ; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp oge half %a, %b %1 = fcmp oge half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_olt(half %a, half %b) nounwind { define i32 @fcmp_olt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_olt: ; RV32IZFH-LABEL: fcmp_olt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_olt: ; RV64IZFH-LABEL: fcmp_olt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_olt: ; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_olt: ; RV64I-LABEL: fcmp_olt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp olt half %a, %b %1 = fcmp olt half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ole(half %a, half %b) nounwind { define i32 @fcmp_ole(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ole: ; RV32IZFH-LABEL: fcmp_ole:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ole: ; RV64IZFH-LABEL: fcmp_ole:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ole: ; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: fle.h a0, ft1, ft0 ; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ole: ; RV64I-LABEL: fcmp_ole:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: fle.h a0, ft1, ft0 ; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ole half %a, %b %1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_one(half %a, half %b) nounwind { define i32 @fcmp_one(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_one: ; RV32IZFH-LABEL: fcmp_one:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: flt.h a1, fa1, fa0 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: or a0, a1, a0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_one: ; RV64IZFH-LABEL: fcmp_one:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: flt.h a1, fa1, fa0 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_one: ; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: flt.h a1, ft0, ft1 ; RV32I-NEXT: flt.h a1, fa0, fa1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_one: ; RV64I-LABEL: fcmp_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: flt.h a1, ft0, ft1 ; RV64I-NEXT: flt.h a1, fa0, fa1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp one half %a, %b %1 = fcmp one half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(half %a, half %b) nounwind { define i32 @fcmp_ord(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ord: ; RV32IZFH-LABEL: fcmp_ord:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ord: ; RV64IZFH-LABEL: fcmp_ord:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ord: ; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: feq.h a0, ft1, ft1 ; RV32I-NEXT: feq.h a0, fa1, fa1
; RV32I-NEXT: feq.h a1, ft0, ft0 ; RV32I-NEXT: feq.h a1, fa0, fa0
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ord: ; RV64I-LABEL: fcmp_ord:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: feq.h a0, ft1, ft1 ; RV64I-NEXT: feq.h a0, fa1, fa1
; RV64I-NEXT: feq.h a1, ft0, ft0 ; RV64I-NEXT: feq.h a1, fa0, fa0
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ord half %a, %b %1 = fcmp ord half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ueq(half %a, half %b) nounwind { define i32 @fcmp_ueq(half %a, half %b) nounwind {
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: flt.h a1, fa1, fa0 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ueq: ; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: flt.h a1, ft0, ft1 ; RV32I-NEXT: flt.h a1, fa0, fa1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ueq: ; RV64I-LABEL: fcmp_ueq:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: flt.h a1, ft0, ft1 ; RV64I-NEXT: flt.h a1, fa0, fa1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ueq half %a, %b %1 = fcmp ueq half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(half %a, half %b) nounwind { define i32 @fcmp_ugt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ugt: ; RV32IZFH-LABEL: fcmp_ugt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ugt: ; RV64IZFH-LABEL: fcmp_ugt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ugt: ; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: fle.h a0, ft1, ft0 ; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ugt: ; RV64I-LABEL: fcmp_ugt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: fle.h a0, ft1, ft0 ; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ugt half %a, %b %1 = fcmp ugt half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_uge(half %a, half %b) nounwind { define i32 @fcmp_uge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_uge: ; RV32IZFH-LABEL: fcmp_uge:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_uge: ; RV64IZFH-LABEL: fcmp_uge:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_uge: ; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_uge: ; RV64I-LABEL: fcmp_uge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp uge half %a, %b %1 = fcmp uge half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ult(half %a, half %b) nounwind { define i32 @fcmp_ult(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ult: ; RV32IZFH-LABEL: fcmp_ult:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ult: ; RV64IZFH-LABEL: fcmp_ult:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ult: ; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: fle.h a0, ft1, ft0 ; RV32I-NEXT: fle.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ult: ; RV64I-LABEL: fcmp_ult:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: fle.h a0, ft1, ft0 ; RV64I-NEXT: fle.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ult half %a, %b %1 = fcmp ult half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ule(half %a, half %b) nounwind { define i32 @fcmp_ule(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ule: ; RV32IZFH-LABEL: fcmp_ule:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ule: ; RV64IZFH-LABEL: fcmp_ule:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_ule: ; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: flt.h a0, ft1, ft0 ; RV32I-NEXT: flt.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_ule: ; RV64I-LABEL: fcmp_ule:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: flt.h a0, ft1, ft0 ; RV64I-NEXT: flt.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ule half %a, %b %1 = fcmp ule half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_une(half %a, half %b) nounwind { define i32 @fcmp_une(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_une: ; RV32IZFH-LABEL: fcmp_une:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_une: ; RV64IZFH-LABEL: fcmp_une:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_une: ; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1 ; RV32I-NEXT: fmv.h.x fa0, a1
; RV32I-NEXT: fmv.h.x ft1, a0 ; RV32I-NEXT: fmv.h.x fa1, a0
; RV32I-NEXT: feq.h a0, ft1, ft0 ; RV32I-NEXT: feq.h a0, fa1, fa0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_une: ; RV64I-LABEL: fcmp_une:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1 ; RV64I-NEXT: fmv.h.x fa0, a1
; RV64I-NEXT: fmv.h.x ft1, a0 ; RV64I-NEXT: fmv.h.x fa1, a0
; RV64I-NEXT: feq.h a0, ft1, ft0 ; RV64I-NEXT: feq.h a0, fa1, fa0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp une half %a, %b %1 = fcmp une half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_uno(half %a, half %b) nounwind { define i32 @fcmp_uno(half %a, half %b) nounwind {
Show All 10 Lines
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32I-LABEL: fcmp_uno: ; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0 ; RV32I-NEXT: fmv.h.x fa0, a0
; RV32I-NEXT: fmv.h.x ft1, a1 ; RV32I-NEXT: fmv.h.x fa1, a1
; RV32I-NEXT: feq.h a0, ft1, ft1 ; RV32I-NEXT: feq.h a0, fa1, fa1
; RV32I-NEXT: feq.h a1, ft0, ft0 ; RV32I-NEXT: feq.h a1, fa0, fa0
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcmp_uno: ; RV64I-LABEL: fcmp_uno:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0 ; RV64I-NEXT: fmv.h.x fa0, a0
; RV64I-NEXT: fmv.h.x ft1, a1 ; RV64I-NEXT: fmv.h.x fa1, a1
; RV64I-NEXT: feq.h a0, ft1, ft1 ; RV64I-NEXT: feq.h a0, fa1, fa1
; RV64I-NEXT: feq.h a1, ft0, ft0 ; RV64I-NEXT: feq.h a1, fa0, fa0
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp uno half %a, %b %1 = fcmp uno half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
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llvm/test/CodeGen/RISCV/half-imm.ll

Show All 18 Lines
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
ret half 3.0 ret half 3.0
} }
define half @half_imm_op(half %a) nounwind { define half @half_imm_op(half %a) nounwind {
; RV32IZFH-LABEL: half_imm_op: ; RV32IZFH-LABEL: half_imm_op:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; RV32IZFH-NEXT: flh fa1, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: half_imm_op: ; RV64IZFH-LABEL: half_imm_op:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; RV64IZFH-NEXT: flh fa1, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, 1.0 %1 = fadd half %a, 1.0
ret half %1 ret half %1
} }

llvm/test/CodeGen/RISCV/half-intrinsics.ll

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call sinf@plt ; RV32IZFH-NEXT: call sinf@plt
; RV32IZFH-NEXT: fcvt.h.s fs1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fs1, fa0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call cosf@plt ; RV32IZFH-NEXT: call cosf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fadd.h fa0, fs1, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fs1, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: sincos_f16: ; RV64IZFH-LABEL: sincos_f16:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill ; RV64IZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fs0, fa0
; RV64IZFH-NEXT: fmv.s fa0, fs0 ; RV64IZFH-NEXT: fmv.s fa0, fs0
; RV64IZFH-NEXT: call sinf@plt ; RV64IZFH-NEXT: call sinf@plt
; RV64IZFH-NEXT: fcvt.h.s fs1, fa0 ; RV64IZFH-NEXT: fcvt.h.s fs1, fa0
; RV64IZFH-NEXT: fmv.s fa0, fs0 ; RV64IZFH-NEXT: fmv.s fa0, fs0
; RV64IZFH-NEXT: call cosf@plt ; RV64IZFH-NEXT: call cosf@plt
; RV64IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: fadd.h fa0, fs1, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fs1, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload ; RV64IZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: sincos_f16: ; RV32IDZFH-LABEL: sincos_f16:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -32 ; RV32IDZFH-NEXT: addi sp, sp, -32
; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call sinf@plt ; RV32IDZFH-NEXT: call sinf@plt
; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0 ; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0
; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call cosf@plt ; RV32IDZFH-NEXT: call cosf@plt
; RV32IDZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IDZFH-NEXT: fadd.h fa0, fs1, ft0 ; RV32IDZFH-NEXT: fadd.h fa0, fs1, fa0
; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload ; RV32IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload ; RV32IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 32 ; RV32IDZFH-NEXT: addi sp, sp, 32
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: sincos_f16: ; RV64IDZFH-LABEL: sincos_f16:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: addi sp, sp, -32 ; RV64IDZFH-NEXT: addi sp, sp, -32
; RV64IDZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64IDZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill ; RV64IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV64IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fs0, fa0
; RV64IDZFH-NEXT: fmv.s fa0, fs0 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
; RV64IDZFH-NEXT: call sinf@plt ; RV64IDZFH-NEXT: call sinf@plt
; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0 ; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0
; RV64IDZFH-NEXT: fmv.s fa0, fs0 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
; RV64IDZFH-NEXT: call cosf@plt ; RV64IDZFH-NEXT: call cosf@plt
; RV64IDZFH-NEXT: fcvt.h.s ft0, fa0 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IDZFH-NEXT: fadd.h fa0, fs1, ft0 ; RV64IDZFH-NEXT: fadd.h fa0, fs1, fa0
; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload ; RV64IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload ; RV64IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV64IDZFH-NEXT: addi sp, sp, 32 ; RV64IDZFH-NEXT: addi sp, sp, 32
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: sincos_f16: ; RV32I-LABEL: sincos_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
▲ Show 20 Lines • Show All 1,539 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
define half @flh(half *%a) nounwind { define half @flh(half *%a) nounwind {
; RV32IZFH-LABEL: flh: ; RV32IZFH-LABEL: flh:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flh ft0, 0(a0) ; RV32IZFH-NEXT: flh fa0, 0(a0)
; RV32IZFH-NEXT: flh ft1, 6(a0) ; RV32IZFH-NEXT: flh fa1, 6(a0)
; RV32IZFH-NEXT: fadd.h fa0, ft0, ft1 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: flh: ; RV64IZFH-LABEL: flh:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flh ft0, 0(a0) ; RV64IZFH-NEXT: flh fa0, 0(a0)
; RV64IZFH-NEXT: flh ft1, 6(a0) ; RV64IZFH-NEXT: flh fa1, 6(a0)
; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = load half, half* %a %1 = load half, half* %a
%2 = getelementptr half, half* %a, i32 3 %2 = getelementptr half, half* %a, i32 3
%3 = load half, half* %2 %3 = load half, half* %2
; Use both loaded values in an FP op to ensure an flh is used, even for the ; Use both loaded values in an FP op to ensure an flh is used, even for the
; soft half ABI ; soft half ABI
%4 = fadd half %1, %3 %4 = fadd half %1, %3
ret half %4 ret half %4
} }
define dso_local void @fsh(half *%a, half %b, half %c) nounwind { define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
; Use %b and %c in an FP op to ensure half precision floating point registers ; Use %b and %c in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI ; are used, even for the soft half ABI
; RV32IZFH-LABEL: fsh: ; RV32IZFH-LABEL: fsh:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: fsh ft0, 0(a0) ; RV32IZFH-NEXT: fsh fa0, 0(a0)
; RV32IZFH-NEXT: fsh ft0, 16(a0) ; RV32IZFH-NEXT: fsh fa0, 16(a0)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fsh: ; RV64IZFH-LABEL: fsh:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fsh ft0, 0(a0) ; RV64IZFH-NEXT: fsh fa0, 0(a0)
; RV64IZFH-NEXT: fsh ft0, 16(a0) ; RV64IZFH-NEXT: fsh fa0, 16(a0)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %b, %c %1 = fadd half %b, %c
store half %1, half* %a store half %1, half* %a
%2 = getelementptr half, half* %a, i32 8 %2 = getelementptr half, half* %a, i32 8
store half %1, half* %2 store half %1, half* %2
ret void ret void
} }
; Check load and store to a global ; Check load and store to a global
@G = dso_local global half 0.0 @G = dso_local global half 0.0
define half @flh_fsh_global(half %a, half %b) nounwind { define half @flh_fsh_global(half %a, half %b) nounwind {
; Use %a and %b in an FP op to ensure half precision floating point registers ; Use %a and %b in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI ; are used, even for the soft half ABI
; RV32IZFH-LABEL: flh_fsh_global: ; RV32IZFH-LABEL: flh_fsh_global:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: lui a0, %hi(G) ; RV32IZFH-NEXT: lui a0, %hi(G)
; RV32IZFH-NEXT: flh ft0, %lo(G)(a0) ; RV32IZFH-NEXT: flh fa1, %lo(G)(a0)
; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0) ; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV32IZFH-NEXT: addi a0, a0, %lo(G) ; RV32IZFH-NEXT: addi a0, a0, %lo(G)
; RV32IZFH-NEXT: flh ft0, 18(a0) ; RV32IZFH-NEXT: flh fa1, 18(a0)
; RV32IZFH-NEXT: fsh fa0, 18(a0) ; RV32IZFH-NEXT: fsh fa0, 18(a0)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: flh_fsh_global: ; RV64IZFH-LABEL: flh_fsh_global:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: lui a0, %hi(G) ; RV64IZFH-NEXT: lui a0, %hi(G)
; RV64IZFH-NEXT: flh ft0, %lo(G)(a0) ; RV64IZFH-NEXT: flh fa1, %lo(G)(a0)
; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0) ; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV64IZFH-NEXT: addi a0, a0, %lo(G) ; RV64IZFH-NEXT: addi a0, a0, %lo(G)
; RV64IZFH-NEXT: flh ft0, 18(a0) ; RV64IZFH-NEXT: flh fa1, 18(a0)
; RV64IZFH-NEXT: fsh fa0, 18(a0) ; RV64IZFH-NEXT: fsh fa0, 18(a0)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = load volatile half, half* @G %2 = load volatile half, half* @G
store half %1, half* @G store half %1, half* @G
%3 = getelementptr half, half* @G, i32 9 %3 = getelementptr half, half* @G, i32 9
%4 = load volatile half, half* %3 %4 = load volatile half, half* %3
store half %1, half* %3 store half %1, half* %3
ret half %1 ret half %1
} }
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define half @flh_fsh_constant(half %a) nounwind { define half @flh_fsh_constant(half %a) nounwind {
; RV32IZFH-LABEL: flh_fsh_constant: ; RV32IZFH-LABEL: flh_fsh_constant:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, 912092 ; RV32IZFH-NEXT: lui a0, 912092
; RV32IZFH-NEXT: flh ft0, -273(a0) ; RV32IZFH-NEXT: flh fa1, -273(a0)
; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: fsh fa0, -273(a0) ; RV32IZFH-NEXT: fsh fa0, -273(a0)
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: flh_fsh_constant: ; RV64IZFH-LABEL: flh_fsh_constant:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, 228023 ; RV64IZFH-NEXT: lui a0, 228023
; RV64IZFH-NEXT: slli a0, a0, 2 ; RV64IZFH-NEXT: slli a0, a0, 2
; RV64IZFH-NEXT: flh ft0, -273(a0) ; RV64IZFH-NEXT: flh fa1, -273(a0)
; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fsh fa0, -273(a0) ; RV64IZFH-NEXT: fsh fa0, -273(a0)
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = inttoptr i32 3735928559 to half* %1 = inttoptr i32 3735928559 to half*
%2 = load volatile half, half* %1 %2 = load volatile half, half* %1
%3 = fadd half %a, %2 %3 = fadd half %a, %2
store half %3, half* %1 store half %3, half* %1
ret half %3 ret half %3
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define half @flh_stack(half %a) nounwind { define half @flh_stack(half %a) nounwind {
; RV32IZFH-LABEL: flh_stack: ; RV32IZFH-LABEL: flh_stack:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fmv.h fs0, fa0 ; RV32IZFH-NEXT: fmv.h fs0, fa0
; RV32IZFH-NEXT: addi a0, sp, 4 ; RV32IZFH-NEXT: addi a0, sp, 4
; RV32IZFH-NEXT: call notdead@plt ; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: flh ft0, 4(sp) ; RV32IZFH-NEXT: flh fa0, 4(sp)
; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fs0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: flh_stack: ; RV64IZFH-LABEL: flh_stack:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fmv.h fs0, fa0 ; RV64IZFH-NEXT: fmv.h fs0, fa0
; RV64IZFH-NEXT: mv a0, sp ; RV64IZFH-NEXT: mv a0, sp
; RV64IZFH-NEXT: call notdead@plt ; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: flh ft0, 0(sp) ; RV64IZFH-NEXT: flh fa0, 0(sp)
; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fs0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = alloca half, align 4 %1 = alloca half, align 4
%2 = bitcast half* %1 to i8* %2 = bitcast half* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load half, half* %1 %3 = load half, half* %1
%4 = fadd half %3, %a ; force load in to FPR16 %4 = fadd half %3, %a ; force load in to FPR16
ret half %4 ret half %4
} }
define dso_local void @fsh_stack(half %a, half %b) nounwind { define dso_local void @fsh_stack(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fsh_stack: ; RV32IZFH-LABEL: fsh_stack:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: fsh ft0, 8(sp) ; RV32IZFH-NEXT: fsh fa0, 8(sp)
; RV32IZFH-NEXT: addi a0, sp, 8 ; RV32IZFH-NEXT: addi a0, sp, 8
; RV32IZFH-NEXT: call notdead@plt ; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fsh_stack: ; RV64IZFH-LABEL: fsh_stack:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fsh ft0, 4(sp) ; RV64IZFH-NEXT: fsh fa0, 4(sp)
; RV64IZFH-NEXT: addi a0, sp, 4 ; RV64IZFH-NEXT: addi a0, sp, 4
; RV64IZFH-NEXT: call notdead@plt ; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b ; force store from FPR16 %1 = fadd half %a, %b ; force store from FPR16
%2 = alloca half, align 4 %2 = alloca half, align 4
store half %1, half* %2 store half %1, half* %2
%3 = bitcast half* %2 to i8* %3 = bitcast half* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
} }

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

Show All 31 Lines
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt ; RV32IZFH-NEXT: call floorf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: fcvt.h.s ft1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft1 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB1_2 ; RV32IZFH-NEXT: bnez s0, .LBB1_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB1_2: ; RV32IZFH-NEXT: .LBB1_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI1_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI1_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB1_9 ; RV32IZFH-NEXT: beqz a3, .LBB1_9
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB1_10 ; RV32IZFH-NEXT: beqz a2, .LBB1_10
; RV32IZFH-NEXT: .LBB1_4: ; RV32IZFH-NEXT: .LBB1_4:
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB1_11 ; RV32IZFH-NEXT: beqz s0, .LBB1_11
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32IZFH-LABEL: test_floor_ui64: ; RV32IZFH-LABEL: test_floor_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt ; RV32IZFH-NEXT: call floorf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB3_2 ; RV32IZFH-NEXT: bnez s0, .LBB3_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB3_2: ; RV32IZFH-NEXT: .LBB3_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI3_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB3_7 ; RV32IZFH-NEXT: beqz a4, .LBB3_7
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: beqz s0, .LBB3_8 ; RV32IZFH-NEXT: beqz s0, .LBB3_8
; RV32IZFH-NEXT: .LBB3_4: ; RV32IZFH-NEXT: .LBB3_4:
; RV32IZFH-NEXT: bnez a4, .LBB3_6 ; RV32IZFH-NEXT: bnez a4, .LBB3_6
; RV32IZFH-NEXT: .LBB3_5: ; RV32IZFH-NEXT: .LBB3_5:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt ; RV32IZFH-NEXT: call ceilf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI5_0)(a0)
; RV32IZFH-NEXT: fcvt.h.s ft1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft1 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB5_2 ; RV32IZFH-NEXT: bnez s0, .LBB5_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB5_2: ; RV32IZFH-NEXT: .LBB5_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI5_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI5_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB5_9 ; RV32IZFH-NEXT: beqz a3, .LBB5_9
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB5_10 ; RV32IZFH-NEXT: beqz a2, .LBB5_10
; RV32IZFH-NEXT: .LBB5_4: ; RV32IZFH-NEXT: .LBB5_4:
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB5_11 ; RV32IZFH-NEXT: beqz s0, .LBB5_11
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; RV32IZFH-LABEL: test_ceil_ui64: ; RV32IZFH-LABEL: test_ceil_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt ; RV32IZFH-NEXT: call ceilf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB7_2 ; RV32IZFH-NEXT: bnez s0, .LBB7_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB7_2: ; RV32IZFH-NEXT: .LBB7_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB7_7 ; RV32IZFH-NEXT: beqz a4, .LBB7_7
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: beqz s0, .LBB7_8 ; RV32IZFH-NEXT: beqz s0, .LBB7_8
; RV32IZFH-NEXT: .LBB7_4: ; RV32IZFH-NEXT: .LBB7_4:
; RV32IZFH-NEXT: bnez a4, .LBB7_6 ; RV32IZFH-NEXT: bnez a4, .LBB7_6
; RV32IZFH-NEXT: .LBB7_5: ; RV32IZFH-NEXT: .LBB7_5:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt ; RV32IZFH-NEXT: call truncf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI9_0)(a0)
; RV32IZFH-NEXT: fcvt.h.s ft1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft1 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB9_2 ; RV32IZFH-NEXT: bnez s0, .LBB9_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB9_2: ; RV32IZFH-NEXT: .LBB9_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI9_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI9_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB9_9 ; RV32IZFH-NEXT: beqz a3, .LBB9_9
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB9_10 ; RV32IZFH-NEXT: beqz a2, .LBB9_10
; RV32IZFH-NEXT: .LBB9_4: ; RV32IZFH-NEXT: .LBB9_4:
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB9_11 ; RV32IZFH-NEXT: beqz s0, .LBB9_11
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; RV32IZFH-LABEL: test_trunc_ui64: ; RV32IZFH-LABEL: test_trunc_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt ; RV32IZFH-NEXT: call truncf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB11_2 ; RV32IZFH-NEXT: bnez s0, .LBB11_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB11_2: ; RV32IZFH-NEXT: .LBB11_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI11_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI11_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB11_7 ; RV32IZFH-NEXT: beqz a4, .LBB11_7
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: beqz s0, .LBB11_8 ; RV32IZFH-NEXT: beqz s0, .LBB11_8
; RV32IZFH-NEXT: .LBB11_4: ; RV32IZFH-NEXT: .LBB11_4:
; RV32IZFH-NEXT: bnez a4, .LBB11_6 ; RV32IZFH-NEXT: bnez a4, .LBB11_6
; RV32IZFH-NEXT: .LBB11_5: ; RV32IZFH-NEXT: .LBB11_5:
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; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt ; RV32IZFH-NEXT: call roundf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI13_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI13_0)(a0)
; RV32IZFH-NEXT: fcvt.h.s ft1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft1 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB13_2 ; RV32IZFH-NEXT: bnez s0, .LBB13_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB13_2: ; RV32IZFH-NEXT: .LBB13_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI13_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI13_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB13_9 ; RV32IZFH-NEXT: beqz a3, .LBB13_9
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB13_10 ; RV32IZFH-NEXT: beqz a2, .LBB13_10
; RV32IZFH-NEXT: .LBB13_4: ; RV32IZFH-NEXT: .LBB13_4:
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB13_11 ; RV32IZFH-NEXT: beqz s0, .LBB13_11
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; RV32IZFH-LABEL: test_round_ui64: ; RV32IZFH-LABEL: test_round_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt ; RV32IZFH-NEXT: call roundf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB15_2 ; RV32IZFH-NEXT: bnez s0, .LBB15_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB15_2: ; RV32IZFH-NEXT: .LBB15_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI15_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI15_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB15_7 ; RV32IZFH-NEXT: beqz a4, .LBB15_7
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: beqz s0, .LBB15_8 ; RV32IZFH-NEXT: beqz s0, .LBB15_8
; RV32IZFH-NEXT: .LBB15_4: ; RV32IZFH-NEXT: .LBB15_4:
; RV32IZFH-NEXT: bnez a4, .LBB15_6 ; RV32IZFH-NEXT: bnez a4, .LBB15_6
; RV32IZFH-NEXT: .LBB15_5: ; RV32IZFH-NEXT: .LBB15_5:
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; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt ; RV32IZFH-NEXT: call roundevenf@plt
; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI17_0)(a0) ; RV32IZFH-NEXT: flw fa1, %lo(.LCPI17_0)(a0)
; RV32IZFH-NEXT: fcvt.h.s ft1, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft1 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa1, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: mv a2, a0 ; RV32IZFH-NEXT: mv a2, a0
; RV32IZFH-NEXT: bnez s0, .LBB17_2 ; RV32IZFH-NEXT: bnez s0, .LBB17_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a2, 0 ; RV32IZFH-NEXT: li a2, 0
; RV32IZFH-NEXT: .LBB17_2: ; RV32IZFH-NEXT: .LBB17_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_1) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_1)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI17_1)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI17_1)(a0)
; RV32IZFH-NEXT: flt.s a3, ft0, fs0 ; RV32IZFH-NEXT: flt.s a3, fa0, fs0
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a3, .LBB17_9 ; RV32IZFH-NEXT: beqz a3, .LBB17_9
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: feq.s a2, fs0, fs0 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
; RV32IZFH-NEXT: beqz a2, .LBB17_10 ; RV32IZFH-NEXT: beqz a2, .LBB17_10
; RV32IZFH-NEXT: .LBB17_4: ; RV32IZFH-NEXT: .LBB17_4:
; RV32IZFH-NEXT: lui a4, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: beqz s0, .LBB17_11 ; RV32IZFH-NEXT: beqz s0, .LBB17_11
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; RV32IZFH-LABEL: test_roundeven_ui64: ; RV32IZFH-LABEL: test_roundeven_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt ; RV32IZFH-NEXT: call roundevenf@plt
; RV32IZFH-NEXT: fcvt.h.s ft0, fa0 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: fcvt.s.h fs0, ft0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x ft0, zero ; RV32IZFH-NEXT: fmv.w.x fa0, zero
; RV32IZFH-NEXT: fle.s s0, ft0, fs0 ; RV32IZFH-NEXT: fle.s s0, fa0, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: mv a3, a0 ; RV32IZFH-NEXT: mv a3, a0
; RV32IZFH-NEXT: bnez s0, .LBB19_2 ; RV32IZFH-NEXT: bnez s0, .LBB19_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: li a3, 0 ; RV32IZFH-NEXT: li a3, 0
; RV32IZFH-NEXT: .LBB19_2: ; RV32IZFH-NEXT: .LBB19_2:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IZFH-NEXT: flw ft0, %lo(.LCPI19_0)(a0) ; RV32IZFH-NEXT: flw fa0, %lo(.LCPI19_0)(a0)
; RV32IZFH-NEXT: flt.s a4, ft0, fs0 ; RV32IZFH-NEXT: flt.s a4, fa0, fs0
; RV32IZFH-NEXT: li a2, -1 ; RV32IZFH-NEXT: li a2, -1
; RV32IZFH-NEXT: li a0, -1 ; RV32IZFH-NEXT: li a0, -1
; RV32IZFH-NEXT: beqz a4, .LBB19_7 ; RV32IZFH-NEXT: beqz a4, .LBB19_7
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: beqz s0, .LBB19_8 ; RV32IZFH-NEXT: beqz s0, .LBB19_8
; RV32IZFH-NEXT: .LBB19_4: ; RV32IZFH-NEXT: .LBB19_4:
; RV32IZFH-NEXT: bnez a4, .LBB19_6 ; RV32IZFH-NEXT: bnez a4, .LBB19_6
; RV32IZFH-NEXT: .LBB19_5: ; RV32IZFH-NEXT: .LBB19_5:
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llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s ; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
@gd = external global double @gd = external global double
define double @constraint_f_double(double %a) nounwind { define double @constraint_f_double(double %a) nounwind {
; RV32F-LABEL: constraint_f_double: ; RV32F-LABEL: constraint_f_double:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16 ; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw a0, 8(sp) ; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp) ; RV32F-NEXT: sw a1, 12(sp)
; RV32F-NEXT: fld ft0, 8(sp) ; RV32F-NEXT: fld fa0, 8(sp)
; RV32F-NEXT: lui a0, %hi(gd) ; RV32F-NEXT: lui a0, %hi(gd)
; RV32F-NEXT: fld ft1, %lo(gd)(a0) ; RV32F-NEXT: fld fa1, %lo(gd)(a0)
; RV32F-NEXT: #APP ; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.d ft0, ft0, ft1 ; RV32F-NEXT: fadd.d fa0, fa0, fa1
; RV32F-NEXT: #NO_APP ; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fsd ft0, 8(sp) ; RV32F-NEXT: fsd fa0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp) ; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp) ; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_double: ; RV64F-LABEL: constraint_f_double:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gd) ; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld ft0, %lo(gd)(a1) ; RV64F-NEXT: fld fa0, %lo(gd)(a1)
; RV64F-NEXT: fmv.d.x ft1, a0 ; RV64F-NEXT: fmv.d.x fa1, a0
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, ft1, ft0 ; RV64F-NEXT: fadd.d fa0, fa1, fa0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0 ; RV64F-NEXT: fmv.x.d a0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load double, double* @gd %1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1) %2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
ret double %2 ret double %2
} }
define double @constraint_f_double_abi_name(double %a) nounwind { define double @constraint_f_double_abi_name(double %a) nounwind {
; RV32F-LABEL: constraint_f_double_abi_name: ; RV32F-LABEL: constraint_f_double_abi_name:
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define double @constraint_gpr(double %x) { define double @constraint_gpr(double %x) {
; RV32F-LABEL: constraint_gpr: ; RV32F-LABEL: constraint_gpr:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -32 ; RV32F-NEXT: addi sp, sp, -32
; RV32F-NEXT: .cfi_def_cfa_offset 32 ; RV32F-NEXT: .cfi_def_cfa_offset 32
; RV32F-NEXT: sw a0, 8(sp) ; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp) ; RV32F-NEXT: sw a1, 12(sp)
; RV32F-NEXT: fld ft0, 8(sp) ; RV32F-NEXT: fld fa0, 8(sp)
; RV32F-NEXT: fsd ft0, 24(sp) ; RV32F-NEXT: fsd fa0, 24(sp)
; RV32F-NEXT: lw a0, 24(sp) ; RV32F-NEXT: lw a0, 24(sp)
; RV32F-NEXT: lw a1, 28(sp) ; RV32F-NEXT: lw a1, 28(sp)
; RV32F-NEXT: #APP ; RV32F-NEXT: #APP
; RV32F-NEXT: mv a0, a0 ; RV32F-NEXT: mv a0, a0
; RV32F-NEXT: #NO_APP ; RV32F-NEXT: #NO_APP
; RV32F-NEXT: sw a1, 20(sp) ; RV32F-NEXT: sw a1, 20(sp)
; RV32F-NEXT: sw a0, 16(sp) ; RV32F-NEXT: sw a0, 16(sp)
; RV32F-NEXT: fld ft0, 16(sp) ; RV32F-NEXT: fld fa0, 16(sp)
; RV32F-NEXT: fsd ft0, 8(sp) ; RV32F-NEXT: fsd fa0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp) ; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp) ; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 32 ; RV32F-NEXT: addi sp, sp, 32
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_gpr: ; RV64F-LABEL: constraint_gpr:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: .cfi_def_cfa_offset 0 ; RV64F-NEXT: .cfi_def_cfa_offset 0
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: mv a0, a0 ; RV64F-NEXT: mv a0, a0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x) %1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

Show All 9 Lines
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
@gf = external global float @gf = external global float
define float @constraint_f_float(float %a) nounwind { define float @constraint_f_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_float: ; RV32F-LABEL: constraint_f_float:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf) ; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw ft0, %lo(gf)(a1) ; RV32F-NEXT: flw fa0, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x ft1, a0 ; RV32F-NEXT: fmv.w.x fa1, a0
; RV32F-NEXT: #APP ; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.s ft0, ft1, ft0 ; RV32F-NEXT: fadd.s fa0, fa1, fa0
; RV32F-NEXT: #NO_APP ; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, ft0 ; RV32F-NEXT: fmv.x.w a0, fa0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: constraint_f_float: ; RV64F-LABEL: constraint_f_float:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf) ; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw ft0, %lo(gf)(a1) ; RV64F-NEXT: flw fa0, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x ft1, a0 ; RV64F-NEXT: fmv.w.x fa1, a0
; RV64F-NEXT: #APP ; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.s ft0, ft1, ft0 ; RV64F-NEXT: fadd.s fa0, fa1, fa0
; RV64F-NEXT: #NO_APP ; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, ft0 ; RV64F-NEXT: fmv.x.w a0, fa0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
%1 = load float, float* @gf %1 = load float, float* @gf
%2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1) %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
ret float %2 ret float %2
} }
define float @constraint_f_float_abi_name(float %a) nounwind { define float @constraint_f_float_abi_name(float %a) nounwind {
; RV32F-LABEL: constraint_f_float_abi_name: ; RV32F-LABEL: constraint_f_float_abi_name:
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llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=zfh -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s ; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32ZFH %s
; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=zfh -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s ; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64ZFH %s
; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=zfh,+d -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s ; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32DZFH %s
; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=zfh,+d -verify-machineinstrs < %s \
; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s ; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64DZFH %s
@gh = external global half @gh = external global half
define half @constraint_f_half(half %a) nounwind { define half @constraint_f_half(half %a) nounwind {
; RV32ZFH-LABEL: constraint_f_half: ; RV32ZFH-LABEL: constraint_f_half:
; RV32ZFH: # %bb.0: ; RV32ZFH: # %bb.0:
; RV32ZFH-NEXT: lui a0, %hi(gh) ; RV32ZFH-NEXT: lui a0, %hi(gh)
; RV32ZFH-NEXT: flh ft0, %lo(gh)(a0) ; RV32ZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV32ZFH-NEXT: #APP ; RV32ZFH-NEXT: #APP
; RV32ZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV32ZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32ZFH-NEXT: #NO_APP ; RV32ZFH-NEXT: #NO_APP
; RV32ZFH-NEXT: ret ; RV32ZFH-NEXT: ret
; ;
; RV64ZFH-LABEL: constraint_f_half: ; RV64ZFH-LABEL: constraint_f_half:
; RV64ZFH: # %bb.0: ; RV64ZFH: # %bb.0:
; RV64ZFH-NEXT: lui a0, %hi(gh) ; RV64ZFH-NEXT: lui a0, %hi(gh)
; RV64ZFH-NEXT: flh ft0, %lo(gh)(a0) ; RV64ZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV64ZFH-NEXT: #APP ; RV64ZFH-NEXT: #APP
; RV64ZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV64ZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64ZFH-NEXT: #NO_APP ; RV64ZFH-NEXT: #NO_APP
; RV64ZFH-NEXT: ret ; RV64ZFH-NEXT: ret
; ;
; RV32DZFH-LABEL: constraint_f_half: ; RV32DZFH-LABEL: constraint_f_half:
; RV32DZFH: # %bb.0: ; RV32DZFH: # %bb.0:
; RV32DZFH-NEXT: lui a0, %hi(gh) ; RV32DZFH-NEXT: lui a0, %hi(gh)
; RV32DZFH-NEXT: flh ft0, %lo(gh)(a0) ; RV32DZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV32DZFH-NEXT: #APP ; RV32DZFH-NEXT: #APP
; RV32DZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV32DZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32DZFH-NEXT: #NO_APP ; RV32DZFH-NEXT: #NO_APP
; RV32DZFH-NEXT: ret ; RV32DZFH-NEXT: ret
; ;
; RV64DZFH-LABEL: constraint_f_half: ; RV64DZFH-LABEL: constraint_f_half:
; RV64DZFH: # %bb.0: ; RV64DZFH: # %bb.0:
; RV64DZFH-NEXT: lui a0, %hi(gh) ; RV64DZFH-NEXT: lui a0, %hi(gh)
; RV64DZFH-NEXT: flh ft0, %lo(gh)(a0) ; RV64DZFH-NEXT: flh fa1, %lo(gh)(a0)
; RV64DZFH-NEXT: #APP ; RV64DZFH-NEXT: #APP
; RV64DZFH-NEXT: fadd.h fa0, fa0, ft0 ; RV64DZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64DZFH-NEXT: #NO_APP ; RV64DZFH-NEXT: #NO_APP
; RV64DZFH-NEXT: ret ; RV64DZFH-NEXT: ret
%1 = load half, half* @gh %1 = load half, half* @gh
%2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1) %2 = tail call half asm "fadd.h $0, $1, $2", "=f,f,f"(half %a, half %1)
ret half %2 ret half %2
} }
define half @constraint_f_half_abi_name(half %a) nounwind { define half @constraint_f_half_abi_name(half %a) nounwind {
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llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
; CHECK-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload ; CHECK-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 64 ; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_float: ; CHECK-RV32IF-LABEL: foo_float:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16 ; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw a0, 12(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw fa0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 4(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw fa1, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f) ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IF-NEXT: flw fa1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IF-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: lw a0, 12(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw fa0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw fa1, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 16 ; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_float: ; CHECK-RV32IFD-LABEL: foo_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f) ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IFD-NEXT: flw fa1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e %1 = load float, float* @e
%2 = load float, float* @f %2 = load float, float* @f
%add = fadd float %1, %2 %add = fadd float %1, %2
store float %add, float* @d store float %add, float* @d
ret void ret void
} }
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; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_fp_float: ; CHECK-RV32IF-LABEL: foo_fp_float:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -32 ; CHECK-RV32IF-NEXT: addi sp, sp, -32
; CHECK-RV32IF-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw fa0, 16(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 12(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw fa1, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: addi s0, sp, 32 ; CHECK-RV32IF-NEXT: addi s0, sp, 32
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f) ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IF-NEXT: flw fa1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IF-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw fa0, 16(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw fa1, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 32 ; CHECK-RV32IF-NEXT: addi sp, sp, 32
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_float: ; CHECK-RV32IFD-LABEL: foo_fp_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw fa0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f) ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IFD-NEXT: flw fa1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.s fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw fa0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e %1 = load float, float* @e
%2 = load float, float* @f %2 = load float, float* @f
%add = fadd float %1, %2 %add = fadd float %1, %2
store float %add, float* @d store float %add, float* @d
ret void ret void
} }
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; CHECK-RV32IF-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 192 ; CHECK-RV32IF-NEXT: addi sp, sp, 192
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_double: ; CHECK-RV32IFD-LABEL: foo_double:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa0, 16(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld fa0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i) ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0) ; CHECK-RV32IFD-NEXT: fld fa1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd fa0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h %1 = load double, double* @h
%2 = load double, double* @i %2 = load double, double* @i
%add = fadd double %1, %2 %add = fadd double %1, %2
store double %add, double* @g store double %add, double* @g
ret void ret void
} }
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; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_double: ; CHECK-RV32IFD-LABEL: foo_fp_double:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill ; CHECK-RV32IFD-NEXT: fsd fa1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld fa0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i) ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0) ; CHECK-RV32IFD-NEXT: fld fa1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.d fa0, fa0, fa1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd fa0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload ; CHECK-RV32IFD-NEXT: fld fa1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h %1 = load double, double* @h
%2 = load double, double* @i %2 = load double, double* @i
%add = fadd double %1, %2 %add = fadd double %1, %2
store double %add, double* @g store double %add, double* @g
ret void ret void
} }
attributes #0 = { "interrupt"="machine" } attributes #0 = { "interrupt"="machine" }
attributes #1 = { "interrupt"="machine" "frame-pointer"="all" } attributes #1 = { "interrupt"="machine" "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/module-target-abi.ll

; RUN: llc -mtriple=riscv32 < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=DEFAULT %s ; RUN: | FileCheck -check-prefix=DEFAULT %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s ; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s
; RV32IF-ILP32F: -target-abi option != target-abi module flag ; RV32IF-ILP32F: -target-abi option != target-abi module flag
; FLAGS: Flags: 0x0 ; FLAGS: Flags: 0x0
define float @foo(i32 %a) nounwind #0 { define float @foo(i32 %a) nounwind #0 {
; DEFAULT: # %bb.0: ; DEFAULT: # %bb.0:
; DEFAULT: fmv.x.w a0, ft0 ; DEFAULT: fmv.x.w a0, fa0
; RV32IF-ILP32: # %bb.0: ; RV32IF-ILP32: # %bb.0:
; RV32IF-ILP32: fmv.x.w a0, ft0 ; RV32IF-ILP32: fmv.x.w a0, fa0
%conv = sitofp i32 %a to float %conv = sitofp i32 %a to float
ret float %conv ret float %conv
} }
attributes #0 = { "target-features"="+f"} attributes #0 = { "target-features"="+f"}
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 1, !"target-abi", !"ilp32"} !0 = !{i32 1, !"target-abi", !"ilp32"}

llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IF ; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IF
; This file exhaustively checks float<->i32 conversions. In general, ; This file exhaustively checks float<->i32 conversions. In general,
; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is ; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
; generated for an fpto[s|u]i conversion if the result doesn't fit in the ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
; target type. ; target type.
define i32 @aext_fptosi(float %a) nounwind strictfp { define i32 @aext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptosi: ; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
define signext i32 @sext_fptosi(float %a) nounwind strictfp { define signext i32 @sext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptosi: ; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
define zeroext i32 @zext_fptosi(float %a) nounwind strictfp { define zeroext i32 @zext_fptosi(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptosi: ; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
define i32 @aext_fptoui(float %a) nounwind strictfp { define i32 @aext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: aext_fptoui: ; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
define signext i32 @sext_fptoui(float %a) nounwind strictfp { define signext i32 @sext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: sext_fptoui: ; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
define zeroext i32 @zext_fptoui(float %a) nounwind strictfp { define zeroext i32 @zext_fptoui(float %a) nounwind strictfp {
; RV64IF-LABEL: zext_fptoui: ; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1 ret i32 %1
} }
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp { define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_aext_i32_to_f32: ; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
declare float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata, metadata) declare float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata, metadata)
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp { define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_sext_i32_to_f32: ; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp { define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: uitofp_zext_i32_to_f32: ; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp { define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_aext_i32_to_f32: ; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata) declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp { define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_sext_i32_to_f32: ; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp { define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF-LABEL: sitofp_zext_i32_to_f32: ; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/rv64f-float-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IF ; RUN: | FileCheck %s -check-prefix=RV64IF
; This file exhaustively checks float<->i32 conversions. In general, ; This file exhaustively checks float<->i32 conversions. In general,
; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is ; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
; generated for an fpto[s|u]i conversion if the result doesn't fit in the ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
; target type. ; target type.
define i32 @aext_fptosi(float %a) nounwind { define i32 @aext_fptosi(float %a) nounwind {
; RV64IF-LABEL: aext_fptosi: ; RV64IF-LABEL: aext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptosi float %a to i32 %1 = fptosi float %a to i32
ret i32 %1 ret i32 %1
} }
define signext i32 @sext_fptosi(float %a) nounwind { define signext i32 @sext_fptosi(float %a) nounwind {
; RV64IF-LABEL: sext_fptosi: ; RV64IF-LABEL: sext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptosi float %a to i32 %1 = fptosi float %a to i32
ret i32 %1 ret i32 %1
} }
define zeroext i32 @zext_fptosi(float %a) nounwind { define zeroext i32 @zext_fptosi(float %a) nounwind {
; RV64IF-LABEL: zext_fptosi: ; RV64IF-LABEL: zext_fptosi:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptosi float %a to i32 %1 = fptosi float %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @aext_fptoui(float %a) nounwind { define i32 @aext_fptoui(float %a) nounwind {
; RV64IF-LABEL: aext_fptoui: ; RV64IF-LABEL: aext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptoui float %a to i32 %1 = fptoui float %a to i32
ret i32 %1 ret i32 %1
} }
define signext i32 @sext_fptoui(float %a) nounwind { define signext i32 @sext_fptoui(float %a) nounwind {
; RV64IF-LABEL: sext_fptoui: ; RV64IF-LABEL: sext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptoui float %a to i32 %1 = fptoui float %a to i32
ret i32 %1 ret i32 %1
} }
define zeroext i32 @zext_fptoui(float %a) nounwind { define zeroext i32 @zext_fptoui(float %a) nounwind {
; RV64IF-LABEL: zext_fptoui: ; RV64IF-LABEL: zext_fptoui:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptoui float %a to i32 %1 = fptoui float %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind { define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_aext_i32: ; RV64IF-LABEL: bcvt_f32_to_aext_i32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x fa0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x fa1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s fa0, fa1, fa0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }
define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind { define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_sext_i32: ; RV64IF-LABEL: bcvt_f32_to_sext_i32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x fa0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x fa1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s fa0, fa1, fa0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind { define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
; RV64IF-LABEL: bcvt_f32_to_zext_i32: ; RV64IF-LABEL: bcvt_f32_to_zext_i32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x fa0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x fa1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s fa0, fa1, fa0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: slli a0, a0, 32 ; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32 ; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }
define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind { define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
; RV64IF-LABEL: bcvt_i64_to_f32_via_i32: ; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x fa0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x fa1, a1
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = trunc i64 %a to i32 %1 = trunc i64 %a to i32
%2 = trunc i64 %b to i32 %2 = trunc i64 %b to i32
%3 = bitcast i32 %1 to float %3 = bitcast i32 %1 to float
%4 = bitcast i32 %2 to float %4 = bitcast i32 %2 to float
%5 = fadd float %3, %4 %5 = fadd float %3, %4
ret float %5 ret float %5
} }
define float @uitofp_aext_i32_to_f32(i32 %a) nounwind { define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: uitofp_aext_i32_to_f32: ; RV64IF-LABEL: uitofp_aext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind { define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: uitofp_sext_i32_to_f32: ; RV64IF-LABEL: uitofp_sext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: uitofp_zext_i32_to_f32: ; RV64IF-LABEL: uitofp_zext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu ft0, a0 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define float @sitofp_aext_i32_to_f32(i32 %a) nounwind { define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
; RV64IF-LABEL: sitofp_aext_i32_to_f32: ; RV64IF-LABEL: sitofp_aext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float %1 = sitofp i32 %a to float
ret float %1 ret float %1
} }
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind { define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: sitofp_sext_i32_to_f32: ; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float %1 = sitofp i32 %a to float
ret float %1 ret float %1
} }
define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
; RV64IF-LABEL: sitofp_zext_i32_to_f32: ; RV64IF-LABEL: sitofp_zext_i32_to_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, fa0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float %1 = sitofp i32 %a to float
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fptoui half %a to i32 %1 = fptoui half %a to i32
ret i32 %1 ret i32 %1
} }
define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind { define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_aext_i16: ; RV64IZFH-LABEL: bcvt_f16_to_aext_i16:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fmv.x.h a0, ft0 ; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = bitcast half %1 to i16 %2 = bitcast half %1 to i16
ret i16 %2 ret i16 %2
} }
define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind { define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_sext_i16: ; RV64IZFH-LABEL: bcvt_f16_to_sext_i16:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fmv.x.h a0, ft0 ; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = bitcast half %1 to i16 %2 = bitcast half %1 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind { define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
; RV64IZFH-LABEL: bcvt_f16_to_zext_i16: ; RV64IZFH-LABEL: bcvt_f16_to_zext_i16:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: fmv.x.h a0, ft0 ; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: slli a0, a0, 48 ; RV64IZFH-NEXT: slli a0, a0, 48
; RV64IZFH-NEXT: srli a0, a0, 48 ; RV64IZFH-NEXT: srli a0, a0, 48
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = bitcast half %1 to i16 %2 = bitcast half %1 to i16
ret i16 %2 ret i16 %2
} }
define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind { define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16: ; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, a0 ; RV64IZFH-NEXT: fmv.h.x fa0, a0
; RV64IZFH-NEXT: fmv.h.x ft1, a1 ; RV64IZFH-NEXT: fmv.h.x fa1, a1
; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1 ; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = trunc i64 %a to i16 %1 = trunc i64 %a to i16
%2 = trunc i64 %b to i16 %2 = trunc i64 %b to i16
%3 = bitcast i16 %1 to half %3 = bitcast i16 %1 to half
%4 = bitcast i16 %2 to half %4 = bitcast i16 %2 to half
%5 = fadd half %3, %4 %5 = fadd half %3, %4
ret half %5 ret half %5
} }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: ceil_nxv1f16: ; CHECK-LABEL: ceil_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI0_1) ; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: ceil_nxv2f16: ; CHECK-LABEL: ceil_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI1_1) ; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: ceil_nxv4f16: ; CHECK-LABEL: ceil_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI2_1) ; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: ceil_nxv8f16: ; CHECK-LABEL: ceil_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
; CHECK-NEXT: vfadd.vf v12, v10, ft0 ; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: ceil_nxv16f16: ; CHECK-LABEL: ceil_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
; CHECK-NEXT: vfadd.vf v16, v12, ft0 ; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: ceil_nxv32f16: ; CHECK-LABEL: ceil_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
; CHECK-NEXT: vfadd.vf v24, v16, ft0 ; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: ceil_nxv1f32: ; CHECK-LABEL: ceil_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI6_1) ; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: ceil_nxv2f32: ; CHECK-LABEL: ceil_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI7_1) ; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: ceil_nxv4f32: ; CHECK-LABEL: ceil_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI8_1) ; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
; CHECK-NEXT: vfadd.vf v12, v10, ft0 ; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: ceil_nxv8f32: ; CHECK-LABEL: ceil_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
; CHECK-NEXT: vfadd.vf v16, v12, ft0 ; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: ceil_nxv16f32: ; CHECK-LABEL: ceil_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
; CHECK-NEXT: vfadd.vf v24, v16, ft0 ; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: ceil_nxv1f64: ; CHECK-LABEL: ceil_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a0, %hi(.LCPI11_1) ; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: ceil_nxv2f64: ; CHECK-LABEL: ceil_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: lui a0, %hi(.LCPI12_1) ; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
; CHECK-NEXT: vfadd.vf v12, v10, ft0 ; CHECK-NEXT: vfadd.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: ceil_nxv4f64: ; CHECK-LABEL: ceil_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v0, v12, v8
; CHECK-NEXT: lui a0, %hi(.LCPI13_1) ; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
; CHECK-NEXT: vfadd.vf v16, v12, ft0 ; CHECK-NEXT: vfadd.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: ceil_nxv8f64: ; CHECK-LABEL: ceil_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: vmflt.vv v0, v16, v8
; CHECK-NEXT: lui a0, %hi(.LCPI14_1) ; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
; CHECK-NEXT: vfadd.vf v24, v16, ft0 ; CHECK-NEXT: vfadd.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: floor_nxv1f16: ; CHECK-LABEL: floor_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI0_1) ; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: floor_nxv2f16: ; CHECK-LABEL: floor_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI1_1) ; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: floor_nxv4f16: ; CHECK-LABEL: floor_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI2_1) ; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: floor_nxv8f16: ; CHECK-LABEL: floor_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
; CHECK-NEXT: vfsub.vf v12, v10, ft0 ; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: floor_nxv16f16: ; CHECK-LABEL: floor_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
; CHECK-NEXT: vfsub.vf v16, v12, ft0 ; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: floor_nxv32f16: ; CHECK-LABEL: floor_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
; CHECK-NEXT: vfsub.vf v24, v16, ft0 ; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: floor_nxv1f32: ; CHECK-LABEL: floor_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI6_1) ; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: floor_nxv2f32: ; CHECK-LABEL: floor_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI7_1) ; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: floor_nxv4f32: ; CHECK-LABEL: floor_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI8_1) ; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
; CHECK-NEXT: vfsub.vf v12, v10, ft0 ; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: floor_nxv8f32: ; CHECK-LABEL: floor_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
; CHECK-NEXT: vfsub.vf v16, v12, ft0 ; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: floor_nxv16f32: ; CHECK-LABEL: floor_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
; CHECK-NEXT: vfsub.vf v24, v16, ft0 ; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: floor_nxv1f64: ; CHECK-LABEL: floor_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a0, %hi(.LCPI11_1) ; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: floor_nxv2f64: ; CHECK-LABEL: floor_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: lui a0, %hi(.LCPI12_1) ; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
; CHECK-NEXT: vfsub.vf v12, v10, ft0 ; CHECK-NEXT: vfsub.vf v12, v10, fa0
; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0 ; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft1 ; CHECK-NEXT: vmflt.vf v0, v12, fa1
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: floor_nxv4f64: ; CHECK-LABEL: floor_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI13_1) ; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
; CHECK-NEXT: vfsub.vf v16, v12, ft0 ; CHECK-NEXT: vfsub.vf v16, v12, fa0
; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0 ; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft1 ; CHECK-NEXT: vmflt.vf v0, v16, fa1
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: floor_nxv8f64: ; CHECK-LABEL: floor_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: vmflt.vv v0, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI14_1) ; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
; CHECK-NEXT: vfsub.vf v24, v16, ft0 ; CHECK-NEXT: vfsub.vf v24, v16, fa0
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfsgnjx.vv v24, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v24, v8, v8
; CHECK-NEXT: vmflt.vf v0, v24, ft1 ; CHECK-NEXT: vmflt.vf v0, v24, fa1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <4 x float> %c, <4 x float>* %x store <4 x float> %c, <4 x float>* %x
ret void ret void
} }
; double vectors should be scalarized ; double vectors should be scalarized
define void @fadd_v2f64(<2 x double>* %x, <2 x double>* %y) { define void @fadd_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fadd_v2f64: ; CHECK-LABEL: fadd_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fld ft0, 8(a0) ; CHECK-NEXT: fld fa0, 8(a0)
; CHECK-NEXT: fld ft1, 0(a0) ; CHECK-NEXT: fld fa1, 0(a0)
; CHECK-NEXT: fld ft2, 0(a1) ; CHECK-NEXT: fld fa2, 0(a1)
; CHECK-NEXT: fld ft3, 8(a1) ; CHECK-NEXT: fld fa3, 8(a1)
; CHECK-NEXT: fadd.d ft1, ft1, ft2 ; CHECK-NEXT: fadd.d fa1, fa1, fa2
; CHECK-NEXT: fadd.d ft0, ft0, ft3 ; CHECK-NEXT: fadd.d fa0, fa0, fa3
; CHECK-NEXT: fsd ft0, 8(a0) ; CHECK-NEXT: fsd fa0, 8(a0)
; CHECK-NEXT: fsd ft1, 0(a0) ; CHECK-NEXT: fsd fa1, 0(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y %b = load <2 x double>, <2 x double>* %y
%c = fadd <2 x double> %a, %b %c = fadd <2 x double> %a, %b
store <2 x double> %c, <2 x double>* %x store <2 x double> %c, <2 x double>* %x
ret void ret void
} }
Show All 13 Lines; CHECK-NEXT: ret
store <2 x float> %c, <2 x float>* %x store <2 x float> %c, <2 x float>* %x
ret void ret void
} }
; double vectors should be scalarized ; double vectors should be scalarized
define void @fadd_v1f64(<1 x double>* %x, <1 x double>* %y) { define void @fadd_v1f64(<1 x double>* %x, <1 x double>* %y) {
; CHECK-LABEL: fadd_v1f64: ; CHECK-LABEL: fadd_v1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fld ft0, 0(a0) ; CHECK-NEXT: fld fa0, 0(a0)
; CHECK-NEXT: fld ft1, 0(a1) ; CHECK-NEXT: fld fa1, 0(a1)
; CHECK-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-NEXT: fadd.d fa0, fa0, fa1
; CHECK-NEXT: fsd ft0, 0(a0) ; CHECK-NEXT: fsd fa0, 0(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <1 x double>, <1 x double>* %x %a = load <1 x double>, <1 x double>* %x
%b = load <1 x double>, <1 x double>* %y %b = load <1 x double>, <1 x double>* %y
%c = fadd <1 x double> %a, %b %c = fadd <1 x double> %a, %b
store <1 x double> %c, <1 x double>* %x store <1 x double> %c, <1 x double>* %x
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant2_v4f32: ; CHECK-LABEL: buildvec_dominant2_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI6_0) ; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1) ; CHECK-NEXT: flw fa1, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa1
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0 %v0 = insertelement <4 x float> poison, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }
define void @buildvec_merge0_v4f32(<4 x float>* %x, float %f) { define void @buildvec_merge0_v4f32(<4 x float>* %x, float %f) {
; RV32-LABEL: buildvec_merge0_v4f32: ; RV32-LABEL: buildvec_merge0_v4f32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 6 ; RV32-NEXT: li a1, 6
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: lui a2, %hi(.LCPI7_0) ; RV32-NEXT: lui a2, %hi(.LCPI7_0)
; RV32-NEXT: flw ft0, %lo(.LCPI7_0)(a2) ; RV32-NEXT: flw fa1, %lo(.LCPI7_0)(a2)
; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vfmv.v.f v8, fa0 ; RV32-NEXT: vfmv.v.f v8, fa0
; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV32-NEXT: vfmerge.vfm v8, v8, fa1, v0
; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: buildvec_merge0_v4f32: ; RV64-LABEL: buildvec_merge0_v4f32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI7_0) ; RV64-NEXT: lui a1, %hi(.LCPI7_0)
; RV64-NEXT: flw ft0, %lo(.LCPI7_0)(a1) ; RV64-NEXT: flw fa1, %lo(.LCPI7_0)(a1)
; RV64-NEXT: li a1, 6 ; RV64-NEXT: li a1, 6
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vfmv.v.f v8, fa0 ; RV64-NEXT: vfmv.v.f v8, fa0
; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV64-NEXT: vfmerge.vfm v8, v8, fa1, v0
; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0 %v0 = insertelement <4 x float> poison, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
%v2 = insertelement <4 x float> %v1, float 2.0, i32 2 %v2 = insertelement <4 x float> %v1, float 2.0, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Show All 27 Lines; CHECK-NEXT: ret
ret <8 x float> %s ret <8 x float> %s
} }
define <4 x double> @shuffle_fv_v4f64(<4 x double> %x) { define <4 x double> @shuffle_fv_v4f64(<4 x double> %x) {
; RV32-LABEL: shuffle_fv_v4f64: ; RV32-LABEL: shuffle_fv_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 9 ; RV32-NEXT: li a0, 9
; RV32-NEXT: lui a1, %hi(.LCPI2_0) ; RV32-NEXT: lui a1, %hi(.LCPI2_0)
; RV32-NEXT: fld ft0, %lo(.LCPI2_0)(a1) ; RV32-NEXT: fld fa0, %lo(.LCPI2_0)(a1)
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: shuffle_fv_v4f64: ; RV64-LABEL: shuffle_fv_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI2_0) ; RV64-NEXT: lui a0, %hi(.LCPI2_0)
; RV64-NEXT: fld ft0, %lo(.LCPI2_0)(a0) ; RV64-NEXT: fld fa0, %lo(.LCPI2_0)(a0)
; RV64-NEXT: li a0, 9 ; RV64-NEXT: li a0, 9
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 3> %s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @shuffle_vf_v4f64(<4 x double> %x) { define <4 x double> @shuffle_vf_v4f64(<4 x double> %x) {
; RV32-LABEL: shuffle_vf_v4f64: ; RV32-LABEL: shuffle_vf_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 6 ; RV32-NEXT: li a0, 6
; RV32-NEXT: lui a1, %hi(.LCPI3_0) ; RV32-NEXT: lui a1, %hi(.LCPI3_0)
; RV32-NEXT: fld ft0, %lo(.LCPI3_0)(a1) ; RV32-NEXT: fld fa0, %lo(.LCPI3_0)(a1)
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: shuffle_vf_v4f64: ; RV64-LABEL: shuffle_vf_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI3_0) ; RV64-NEXT: lui a0, %hi(.LCPI3_0)
; RV64-NEXT: fld ft0, %lo(.LCPI3_0)(a0) ; RV64-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
; RV64-NEXT: li a0, 6 ; RV64-NEXT: li a0, 6
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0 ; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 3> %s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) { define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_permute_shuffle_vu_v4f64: ; RV32-LABEL: vrgather_permute_shuffle_vu_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Show First 20 Lines • Show All 1,964 Lines • ▼ Show 20 Lines
} }
define void @trunc_v8f16(<8 x half>* %x) { define void @trunc_v8f16(<8 x half>* %x) {
; CHECK-LABEL: trunc_v8f16: ; CHECK-LABEL: trunc_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI91_0) ; CHECK-NEXT: lui a1, %hi(.LCPI91_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI91_0)(a1) ; CHECK-NEXT: flh fa0, %lo(.LCPI91_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.trunc.v8f16(<8 x half>) declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
define void @trunc_v4f32(<4 x float>* %x) { define void @trunc_v4f32(<4 x float>* %x) {
; CHECK-LABEL: trunc_v4f32: ; CHECK-LABEL: trunc_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI92_0) ; CHECK-NEXT: lui a1, %hi(.LCPI92_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI92_0)(a1) ; CHECK-NEXT: flw fa0, %lo(.LCPI92_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.trunc.v4f32(<4 x float>) declare <4 x float> @llvm.trunc.v4f32(<4 x float>)
define void @trunc_v2f64(<2 x double>* %x) { define void @trunc_v2f64(<2 x double>* %x) {
; CHECK-LABEL: trunc_v2f64: ; CHECK-LABEL: trunc_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI93_0) ; CHECK-NEXT: lui a1, %hi(.LCPI93_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI93_0)(a1) ; CHECK-NEXT: fld fa0, %lo(.LCPI93_0)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.trunc.v2f64(<2 x double>) declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
define void @ceil_v8f16(<8 x half>* %x) { define void @ceil_v8f16(<8 x half>* %x) {
; CHECK-LABEL: ceil_v8f16: ; CHECK-LABEL: ceil_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI94_0) ; CHECK-NEXT: lui a1, %hi(.LCPI94_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI94_0)(a1) ; CHECK-NEXT: flh fa0, %lo(.LCPI94_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI94_1) ; CHECK-NEXT: lui a1, %hi(.LCPI94_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI94_1)(a1) ; CHECK-NEXT: flh fa1, %lo(.LCPI94_1)(a1)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.ceil.v8f16(<8 x half>) declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
define void @ceil_v4f32(<4 x float>* %x) { define void @ceil_v4f32(<4 x float>* %x) {
; CHECK-LABEL: ceil_v4f32: ; CHECK-LABEL: ceil_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI95_0) ; CHECK-NEXT: lui a1, %hi(.LCPI95_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI95_0)(a1) ; CHECK-NEXT: flw fa0, %lo(.LCPI95_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI95_1) ; CHECK-NEXT: lui a1, %hi(.LCPI95_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI95_1)(a1) ; CHECK-NEXT: flw fa1, %lo(.LCPI95_1)(a1)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.ceil.v4f32(<4 x float>) declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
define void @ceil_v2f64(<2 x double>* %x) { define void @ceil_v2f64(<2 x double>* %x) {
; CHECK-LABEL: ceil_v2f64: ; CHECK-LABEL: ceil_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI96_0) ; CHECK-NEXT: lui a1, %hi(.LCPI96_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI96_0)(a1) ; CHECK-NEXT: fld fa0, %lo(.LCPI96_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: lui a1, %hi(.LCPI96_1) ; CHECK-NEXT: lui a1, %hi(.LCPI96_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI96_1)(a1) ; CHECK-NEXT: fld fa1, %lo(.LCPI96_1)(a1)
; CHECK-NEXT: vfadd.vf v10, v9, ft0 ; CHECK-NEXT: vfadd.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
define void @floor_v8f16(<8 x half>* %x) { define void @floor_v8f16(<8 x half>* %x) {
; CHECK-LABEL: floor_v8f16: ; CHECK-LABEL: floor_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI97_0) ; CHECK-NEXT: lui a1, %hi(.LCPI97_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI97_0)(a1) ; CHECK-NEXT: flh fa0, %lo(.LCPI97_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI97_1) ; CHECK-NEXT: lui a1, %hi(.LCPI97_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI97_1)(a1) ; CHECK-NEXT: flh fa1, %lo(.LCPI97_1)(a1)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.floor.v8f16(<8 x half>) declare <8 x half> @llvm.floor.v8f16(<8 x half>)
define void @floor_v4f32(<4 x float>* %x) { define void @floor_v4f32(<4 x float>* %x) {
; CHECK-LABEL: floor_v4f32: ; CHECK-LABEL: floor_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI98_0) ; CHECK-NEXT: lui a1, %hi(.LCPI98_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI98_0)(a1) ; CHECK-NEXT: flw fa0, %lo(.LCPI98_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI98_1) ; CHECK-NEXT: lui a1, %hi(.LCPI98_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI98_1)(a1) ; CHECK-NEXT: flw fa1, %lo(.LCPI98_1)(a1)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.floor.v4f32(<4 x float>) declare <4 x float> @llvm.floor.v4f32(<4 x float>)
define void @floor_v2f64(<2 x double>* %x) { define void @floor_v2f64(<2 x double>* %x) {
; CHECK-LABEL: floor_v2f64: ; CHECK-LABEL: floor_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: lui a1, %hi(.LCPI99_0) ; CHECK-NEXT: lui a1, %hi(.LCPI99_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI99_0)(a1) ; CHECK-NEXT: fld fa0, %lo(.LCPI99_0)(a1)
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: lui a1, %hi(.LCPI99_1) ; CHECK-NEXT: lui a1, %hi(.LCPI99_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI99_1)(a1) ; CHECK-NEXT: fld fa1, %lo(.LCPI99_1)(a1)
; CHECK-NEXT: vfsub.vf v10, v9, ft0 ; CHECK-NEXT: vfsub.vf v10, v9, fa0
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft1 ; CHECK-NEXT: vmflt.vf v0, v10, fa1
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.floor.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.floor.v2f64(<2 x double>) declare <2 x double> @llvm.floor.v2f64(<2 x double>)
define void @round_v8f16(<8 x half>* %x) { define void @round_v8f16(<8 x half>* %x) {
; CHECK-LABEL: round_v8f16: ; CHECK-LABEL: round_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI100_0) ; CHECK-NEXT: lui a1, %hi(.LCPI100_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI100_0)(a1) ; CHECK-NEXT: flh fa0, %lo(.LCPI100_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI100_1) ; CHECK-NEXT: lui a1, %hi(.LCPI100_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI100_1)(a1) ; CHECK-NEXT: flh fa1, %lo(.LCPI100_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.round.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.round.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.round.v8f16(<8 x half>) declare <8 x half> @llvm.round.v8f16(<8 x half>)
define void @round_v4f32(<4 x float>* %x) { define void @round_v4f32(<4 x float>* %x) {
; CHECK-LABEL: round_v4f32: ; CHECK-LABEL: round_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI101_0) ; CHECK-NEXT: lui a1, %hi(.LCPI101_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI101_0)(a1) ; CHECK-NEXT: flw fa0, %lo(.LCPI101_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI101_1) ; CHECK-NEXT: lui a1, %hi(.LCPI101_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI101_1)(a1) ; CHECK-NEXT: flw fa1, %lo(.LCPI101_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.round.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.round.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.round.v4f32(<4 x float>) declare <4 x float> @llvm.round.v4f32(<4 x float>)
define void @round_v2f64(<2 x double>* %x) { define void @round_v2f64(<2 x double>* %x) {
; CHECK-LABEL: round_v2f64: ; CHECK-LABEL: round_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI102_0) ; CHECK-NEXT: lui a1, %hi(.LCPI102_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI102_0)(a1) ; CHECK-NEXT: fld fa0, %lo(.LCPI102_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI102_1) ; CHECK-NEXT: lui a1, %hi(.LCPI102_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI102_1)(a1) ; CHECK-NEXT: fld fa1, %lo(.LCPI102_1)(a1)
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.round.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.round.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.round.v2f64(<2 x double>) declare <2 x double> @llvm.round.v2f64(<2 x double>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %res_ptr) nounwind { define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1f16: ; CHECK-LABEL: masked_load_v1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <1 x half>, <1 x half>* %m_ptr %m = load <1 x half>, <1 x half>* %m_ptr
%mask = fcmp oeq <1 x half> %m, zeroinitializer %mask = fcmp oeq <1 x half> %m, zeroinitializer
%load = call <1 x half> @llvm.masked.load.v1f16(<1 x half>* %a, i32 8, <1 x i1> %mask, <1 x half> undef) %load = call <1 x half> @llvm.masked.load.v1f16(<1 x half>* %a, i32 8, <1 x i1> %mask, <1 x half> undef)
store <1 x half> %load, <1 x half>* %res_ptr store <1 x half> %load, <1 x half>* %res_ptr
ret void ret void
} }
declare <1 x half> @llvm.masked.load.v1f16(<1 x half>*, i32, <1 x i1>, <1 x half>) declare <1 x half> @llvm.masked.load.v1f16(<1 x half>*, i32, <1 x i1>, <1 x half>)
define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float>* %res_ptr) nounwind { define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1f32: ; CHECK-LABEL: masked_load_v1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <1 x float>, <1 x float>* %m_ptr %m = load <1 x float>, <1 x float>* %m_ptr
%mask = fcmp oeq <1 x float> %m, zeroinitializer %mask = fcmp oeq <1 x float> %m, zeroinitializer
%load = call <1 x float> @llvm.masked.load.v1f32(<1 x float>* %a, i32 8, <1 x i1> %mask, <1 x float> undef) %load = call <1 x float> @llvm.masked.load.v1f32(<1 x float>* %a, i32 8, <1 x i1> %mask, <1 x float> undef)
store <1 x float> %load, <1 x float>* %res_ptr store <1 x float> %load, <1 x float>* %res_ptr
ret void ret void
} }
declare <1 x float> @llvm.masked.load.v1f32(<1 x float>*, i32, <1 x i1>, <1 x float>) declare <1 x float> @llvm.masked.load.v1f32(<1 x float>*, i32, <1 x i1>, <1 x float>)
define void @masked_load_v1f64(<1 x double>* %a, <1 x double>* %m_ptr, <1 x double>* %res_ptr) nounwind { define void @masked_load_v1f64(<1 x double>* %a, <1 x double>* %m_ptr, <1 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v1f64: ; RV32-LABEL: masked_load_v1f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v1f64: ; RV64-LABEL: masked_load_v1f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <1 x double>, <1 x double>* %m_ptr %m = load <1 x double>, <1 x double>* %m_ptr
%mask = fcmp oeq <1 x double> %m, zeroinitializer %mask = fcmp oeq <1 x double> %m, zeroinitializer
%load = call <1 x double> @llvm.masked.load.v1f64(<1 x double>* %a, i32 8, <1 x i1> %mask, <1 x double> undef) %load = call <1 x double> @llvm.masked.load.v1f64(<1 x double>* %a, i32 8, <1 x i1> %mask, <1 x double> undef)
store <1 x double> %load, <1 x double>* %res_ptr store <1 x double> %load, <1 x double>* %res_ptr
ret void ret void
} }
declare <1 x double> @llvm.masked.load.v1f64(<1 x double>*, i32, <1 x i1>, <1 x double>) declare <1 x double> @llvm.masked.load.v1f64(<1 x double>*, i32, <1 x i1>, <1 x double>)
define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* %res_ptr) nounwind { define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2f16: ; CHECK-LABEL: masked_load_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <2 x half>, <2 x half>* %m_ptr %m = load <2 x half>, <2 x half>* %m_ptr
%mask = fcmp oeq <2 x half> %m, zeroinitializer %mask = fcmp oeq <2 x half> %m, zeroinitializer
%load = call <2 x half> @llvm.masked.load.v2f16(<2 x half>* %a, i32 8, <2 x i1> %mask, <2 x half> undef) %load = call <2 x half> @llvm.masked.load.v2f16(<2 x half>* %a, i32 8, <2 x i1> %mask, <2 x half> undef)
store <2 x half> %load, <2 x half>* %res_ptr store <2 x half> %load, <2 x half>* %res_ptr
ret void ret void
} }
declare <2 x half> @llvm.masked.load.v2f16(<2 x half>*, i32, <2 x i1>, <2 x half>) declare <2 x half> @llvm.masked.load.v2f16(<2 x half>*, i32, <2 x i1>, <2 x half>)
define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float>* %res_ptr) nounwind { define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2f32: ; CHECK-LABEL: masked_load_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <2 x float>, <2 x float>* %m_ptr %m = load <2 x float>, <2 x float>* %m_ptr
%mask = fcmp oeq <2 x float> %m, zeroinitializer %mask = fcmp oeq <2 x float> %m, zeroinitializer
%load = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %a, i32 8, <2 x i1> %mask, <2 x float> undef) %load = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %a, i32 8, <2 x i1> %mask, <2 x float> undef)
store <2 x float> %load, <2 x float>* %res_ptr store <2 x float> %load, <2 x float>* %res_ptr
ret void ret void
} }
declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>) declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)
define void @masked_load_v2f64(<2 x double>* %a, <2 x double>* %m_ptr, <2 x double>* %res_ptr) nounwind { define void @masked_load_v2f64(<2 x double>* %a, <2 x double>* %m_ptr, <2 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v2f64: ; RV32-LABEL: masked_load_v2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v2f64: ; RV64-LABEL: masked_load_v2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <2 x double>, <2 x double>* %m_ptr %m = load <2 x double>, <2 x double>* %m_ptr
%mask = fcmp oeq <2 x double> %m, zeroinitializer %mask = fcmp oeq <2 x double> %m, zeroinitializer
%load = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %a, i32 8, <2 x i1> %mask, <2 x double> undef) %load = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %a, i32 8, <2 x i1> %mask, <2 x double> undef)
store <2 x double> %load, <2 x double>* %res_ptr store <2 x double> %load, <2 x double>* %res_ptr
ret void ret void
} }
declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>) declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* %res_ptr) nounwind { define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v4f16: ; CHECK-LABEL: masked_load_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <4 x half>, <4 x half>* %m_ptr %m = load <4 x half>, <4 x half>* %m_ptr
%mask = fcmp oeq <4 x half> %m, zeroinitializer %mask = fcmp oeq <4 x half> %m, zeroinitializer
%load = call <4 x half> @llvm.masked.load.v4f16(<4 x half>* %a, i32 8, <4 x i1> %mask, <4 x half> undef) %load = call <4 x half> @llvm.masked.load.v4f16(<4 x half>* %a, i32 8, <4 x i1> %mask, <4 x half> undef)
store <4 x half> %load, <4 x half>* %res_ptr store <4 x half> %load, <4 x half>* %res_ptr
ret void ret void
} }
declare <4 x half> @llvm.masked.load.v4f16(<4 x half>*, i32, <4 x i1>, <4 x half>) declare <4 x half> @llvm.masked.load.v4f16(<4 x half>*, i32, <4 x i1>, <4 x half>)
define void @masked_load_v4f32(<4 x float>* %a, <4 x float>* %m_ptr, <4 x float>* %res_ptr) nounwind { define void @masked_load_v4f32(<4 x float>* %a, <4 x float>* %m_ptr, <4 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v4f32: ; CHECK-LABEL: masked_load_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <4 x float>, <4 x float>* %m_ptr %m = load <4 x float>, <4 x float>* %m_ptr
%mask = fcmp oeq <4 x float> %m, zeroinitializer %mask = fcmp oeq <4 x float> %m, zeroinitializer
%load = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %a, i32 8, <4 x i1> %mask, <4 x float> undef) %load = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %a, i32 8, <4 x i1> %mask, <4 x float> undef)
store <4 x float> %load, <4 x float>* %res_ptr store <4 x float> %load, <4 x float>* %res_ptr
ret void ret void
} }
declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)
define void @masked_load_v4f64(<4 x double>* %a, <4 x double>* %m_ptr, <4 x double>* %res_ptr) nounwind { define void @masked_load_v4f64(<4 x double>* %a, <4 x double>* %m_ptr, <4 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v4f64: ; RV32-LABEL: masked_load_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v4f64: ; RV64-LABEL: masked_load_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <4 x double>, <4 x double>* %m_ptr %m = load <4 x double>, <4 x double>* %m_ptr
%mask = fcmp oeq <4 x double> %m, zeroinitializer %mask = fcmp oeq <4 x double> %m, zeroinitializer
%load = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %a, i32 8, <4 x i1> %mask, <4 x double> undef) %load = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %a, i32 8, <4 x i1> %mask, <4 x double> undef)
store <4 x double> %load, <4 x double>* %res_ptr store <4 x double> %load, <4 x double>* %res_ptr
ret void ret void
} }
declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>) declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
define void @masked_load_v8f16(<8 x half>* %a, <8 x half>* %m_ptr, <8 x half>* %res_ptr) nounwind { define void @masked_load_v8f16(<8 x half>* %a, <8 x half>* %m_ptr, <8 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v8f16: ; CHECK-LABEL: masked_load_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <8 x half>, <8 x half>* %m_ptr %m = load <8 x half>, <8 x half>* %m_ptr
%mask = fcmp oeq <8 x half> %m, zeroinitializer %mask = fcmp oeq <8 x half> %m, zeroinitializer
%load = call <8 x half> @llvm.masked.load.v8f16(<8 x half>* %a, i32 8, <8 x i1> %mask, <8 x half> undef) %load = call <8 x half> @llvm.masked.load.v8f16(<8 x half>* %a, i32 8, <8 x i1> %mask, <8 x half> undef)
store <8 x half> %load, <8 x half>* %res_ptr store <8 x half> %load, <8 x half>* %res_ptr
ret void ret void
} }
declare <8 x half> @llvm.masked.load.v8f16(<8 x half>*, i32, <8 x i1>, <8 x half>) declare <8 x half> @llvm.masked.load.v8f16(<8 x half>*, i32, <8 x i1>, <8 x half>)
define void @masked_load_v8f32(<8 x float>* %a, <8 x float>* %m_ptr, <8 x float>* %res_ptr) nounwind { define void @masked_load_v8f32(<8 x float>* %a, <8 x float>* %m_ptr, <8 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v8f32: ; CHECK-LABEL: masked_load_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <8 x float>, <8 x float>* %m_ptr %m = load <8 x float>, <8 x float>* %m_ptr
%mask = fcmp oeq <8 x float> %m, zeroinitializer %mask = fcmp oeq <8 x float> %m, zeroinitializer
%load = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %a, i32 8, <8 x i1> %mask, <8 x float> undef) %load = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %a, i32 8, <8 x i1> %mask, <8 x float> undef)
store <8 x float> %load, <8 x float>* %res_ptr store <8 x float> %load, <8 x float>* %res_ptr
ret void ret void
} }
declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>) declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
define void @masked_load_v8f64(<8 x double>* %a, <8 x double>* %m_ptr, <8 x double>* %res_ptr) nounwind { define void @masked_load_v8f64(<8 x double>* %a, <8 x double>* %m_ptr, <8 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v8f64: ; RV32-LABEL: masked_load_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v8f64: ; RV64-LABEL: masked_load_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <8 x double>, <8 x double>* %m_ptr %m = load <8 x double>, <8 x double>* %m_ptr
%mask = fcmp oeq <8 x double> %m, zeroinitializer %mask = fcmp oeq <8 x double> %m, zeroinitializer
%load = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %a, i32 8, <8 x i1> %mask, <8 x double> undef) %load = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %a, i32 8, <8 x i1> %mask, <8 x double> undef)
store <8 x double> %load, <8 x double>* %res_ptr store <8 x double> %load, <8 x double>* %res_ptr
ret void ret void
} }
declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>) declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)
define void @masked_load_v16f16(<16 x half>* %a, <16 x half>* %m_ptr, <16 x half>* %res_ptr) nounwind { define void @masked_load_v16f16(<16 x half>* %a, <16 x half>* %m_ptr, <16 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v16f16: ; CHECK-LABEL: masked_load_v16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <16 x half>, <16 x half>* %m_ptr %m = load <16 x half>, <16 x half>* %m_ptr
%mask = fcmp oeq <16 x half> %m, zeroinitializer %mask = fcmp oeq <16 x half> %m, zeroinitializer
%load = call <16 x half> @llvm.masked.load.v16f16(<16 x half>* %a, i32 8, <16 x i1> %mask, <16 x half> undef) %load = call <16 x half> @llvm.masked.load.v16f16(<16 x half>* %a, i32 8, <16 x i1> %mask, <16 x half> undef)
store <16 x half> %load, <16 x half>* %res_ptr store <16 x half> %load, <16 x half>* %res_ptr
ret void ret void
} }
declare <16 x half> @llvm.masked.load.v16f16(<16 x half>*, i32, <16 x i1>, <16 x half>) declare <16 x half> @llvm.masked.load.v16f16(<16 x half>*, i32, <16 x i1>, <16 x half>)
define void @masked_load_v16f32(<16 x float>* %a, <16 x float>* %m_ptr, <16 x float>* %res_ptr) nounwind { define void @masked_load_v16f32(<16 x float>* %a, <16 x float>* %m_ptr, <16 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v16f32: ; CHECK-LABEL: masked_load_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <16 x float>, <16 x float>* %m_ptr %m = load <16 x float>, <16 x float>* %m_ptr
%mask = fcmp oeq <16 x float> %m, zeroinitializer %mask = fcmp oeq <16 x float> %m, zeroinitializer
%load = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %a, i32 8, <16 x i1> %mask, <16 x float> undef) %load = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %a, i32 8, <16 x i1> %mask, <16 x float> undef)
store <16 x float> %load, <16 x float>* %res_ptr store <16 x float> %load, <16 x float>* %res_ptr
ret void ret void
} }
declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
define void @masked_load_v16f64(<16 x double>* %a, <16 x double>* %m_ptr, <16 x double>* %res_ptr) nounwind { define void @masked_load_v16f64(<16 x double>* %a, <16 x double>* %m_ptr, <16 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v16f64: ; RV32-LABEL: masked_load_v16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v16f64: ; RV64-LABEL: masked_load_v16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <16 x double>, <16 x double>* %m_ptr %m = load <16 x double>, <16 x double>* %m_ptr
%mask = fcmp oeq <16 x double> %m, zeroinitializer %mask = fcmp oeq <16 x double> %m, zeroinitializer
%load = call <16 x double> @llvm.masked.load.v16f64(<16 x double>* %a, i32 8, <16 x i1> %mask, <16 x double> undef) %load = call <16 x double> @llvm.masked.load.v16f64(<16 x double>* %a, i32 8, <16 x i1> %mask, <16 x double> undef)
store <16 x double> %load, <16 x double>* %res_ptr store <16 x double> %load, <16 x double>* %res_ptr
ret void ret void
} }
declare <16 x double> @llvm.masked.load.v16f64(<16 x double>*, i32, <16 x i1>, <16 x double>) declare <16 x double> @llvm.masked.load.v16f64(<16 x double>*, i32, <16 x i1>, <16 x double>)
define void @masked_load_v32f16(<32 x half>* %a, <32 x half>* %m_ptr, <32 x half>* %res_ptr) nounwind { define void @masked_load_v32f16(<32 x half>* %a, <32 x half>* %m_ptr, <32 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v32f16: ; CHECK-LABEL: masked_load_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <32 x half>, <32 x half>* %m_ptr %m = load <32 x half>, <32 x half>* %m_ptr
%mask = fcmp oeq <32 x half> %m, zeroinitializer %mask = fcmp oeq <32 x half> %m, zeroinitializer
%load = call <32 x half> @llvm.masked.load.v32f16(<32 x half>* %a, i32 8, <32 x i1> %mask, <32 x half> undef) %load = call <32 x half> @llvm.masked.load.v32f16(<32 x half>* %a, i32 8, <32 x i1> %mask, <32 x half> undef)
store <32 x half> %load, <32 x half>* %res_ptr store <32 x half> %load, <32 x half>* %res_ptr
ret void ret void
} }
declare <32 x half> @llvm.masked.load.v32f16(<32 x half>*, i32, <32 x i1>, <32 x half>) declare <32 x half> @llvm.masked.load.v32f16(<32 x half>*, i32, <32 x i1>, <32 x half>)
define void @masked_load_v32f32(<32 x float>* %a, <32 x float>* %m_ptr, <32 x float>* %res_ptr) nounwind { define void @masked_load_v32f32(<32 x float>* %a, <32 x float>* %m_ptr, <32 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v32f32: ; CHECK-LABEL: masked_load_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <32 x float>, <32 x float>* %m_ptr %m = load <32 x float>, <32 x float>* %m_ptr
%mask = fcmp oeq <32 x float> %m, zeroinitializer %mask = fcmp oeq <32 x float> %m, zeroinitializer
%load = call <32 x float> @llvm.masked.load.v32f32(<32 x float>* %a, i32 8, <32 x i1> %mask, <32 x float> undef) %load = call <32 x float> @llvm.masked.load.v32f32(<32 x float>* %a, i32 8, <32 x i1> %mask, <32 x float> undef)
store <32 x float> %load, <32 x float>* %res_ptr store <32 x float> %load, <32 x float>* %res_ptr
ret void ret void
} }
declare <32 x float> @llvm.masked.load.v32f32(<32 x float>*, i32, <32 x i1>, <32 x float>) declare <32 x float> @llvm.masked.load.v32f32(<32 x float>*, i32, <32 x i1>, <32 x float>)
define void @masked_load_v32f64(<32 x double>* %a, <32 x double>* %m_ptr, <32 x double>* %res_ptr) nounwind { define void @masked_load_v32f64(<32 x double>* %a, <32 x double>* %m_ptr, <32 x double>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v32f64: ; RV32-LABEL: masked_load_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi a3, a1, 128 ; RV32-NEXT: addi a3, a1, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v16, (a1) ; RV32-NEXT: vle64.v v16, (a1)
; RV32-NEXT: vle64.v v24, (a3) ; RV32-NEXT: vle64.v v24, (a3)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v8, v16, ft0 ; RV32-NEXT: vmfeq.vf v8, v16, fa0
; RV32-NEXT: vmfeq.vf v0, v24, ft0 ; RV32-NEXT: vmfeq.vf v0, v24, fa0
; RV32-NEXT: addi a1, a0, 128 ; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vle64.v v16, (a1), v0.t ; RV32-NEXT: vle64.v v16, (a1), v0.t
; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vle64.v v8, (a0), v0.t ; RV32-NEXT: vle64.v v8, (a0), v0.t
; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: addi a0, a2, 128 ; RV32-NEXT: addi a0, a2, 128
; RV32-NEXT: vse64.v v16, (a0) ; RV32-NEXT: vse64.v v16, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v32f64: ; RV64-LABEL: masked_load_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi a3, a1, 128 ; RV64-NEXT: addi a3, a1, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v16, (a1) ; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: vle64.v v24, (a3) ; RV64-NEXT: vle64.v v24, (a3)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v8, v16, ft0 ; RV64-NEXT: vmfeq.vf v8, v16, fa0
; RV64-NEXT: vmfeq.vf v0, v24, ft0 ; RV64-NEXT: vmfeq.vf v0, v24, fa0
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vle64.v v16, (a1), v0.t ; RV64-NEXT: vle64.v v16, (a1), v0.t
; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vle64.v v8, (a0), v0.t ; RV64-NEXT: vle64.v v8, (a0), v0.t
; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: addi a0, a2, 128 ; RV64-NEXT: addi a0, a2, 128
; RV64-NEXT: vse64.v v16, (a0) ; RV64-NEXT: vse64.v v16, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <32 x double>, <32 x double>* %m_ptr %m = load <32 x double>, <32 x double>* %m_ptr
%mask = fcmp oeq <32 x double> %m, zeroinitializer %mask = fcmp oeq <32 x double> %m, zeroinitializer
%load = call <32 x double> @llvm.masked.load.v32f64(<32 x double>* %a, i32 8, <32 x i1> %mask, <32 x double> undef) %load = call <32 x double> @llvm.masked.load.v32f64(<32 x double>* %a, i32 8, <32 x i1> %mask, <32 x double> undef)
store <32 x double> %load, <32 x double>* %res_ptr store <32 x double> %load, <32 x double>* %res_ptr
ret void ret void
} }
declare <32 x double> @llvm.masked.load.v32f64(<32 x double>*, i32, <32 x i1>, <32 x double>) declare <32 x double> @llvm.masked.load.v32f64(<32 x double>*, i32, <32 x i1>, <32 x double>)
define void @masked_load_v64f16(<64 x half>* %a, <64 x half>* %m_ptr, <64 x half>* %res_ptr) nounwind { define void @masked_load_v64f16(<64 x half>* %a, <64 x half>* %m_ptr, <64 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v64f16: ; CHECK-LABEL: masked_load_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 64 ; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <64 x half>, <64 x half>* %m_ptr %m = load <64 x half>, <64 x half>* %m_ptr
%mask = fcmp oeq <64 x half> %m, zeroinitializer %mask = fcmp oeq <64 x half> %m, zeroinitializer
%load = call <64 x half> @llvm.masked.load.v64f16(<64 x half>* %a, i32 8, <64 x i1> %mask, <64 x half> undef) %load = call <64 x half> @llvm.masked.load.v64f16(<64 x half>* %a, i32 8, <64 x i1> %mask, <64 x half> undef)
store <64 x half> %load, <64 x half>* %res_ptr store <64 x half> %load, <64 x half>* %res_ptr
ret void ret void
} }
declare <64 x half> @llvm.masked.load.v64f16(<64 x half>*, i32, <64 x i1>, <64 x half>) declare <64 x half> @llvm.masked.load.v64f16(<64 x half>*, i32, <64 x i1>, <64 x half>)
define void @masked_load_v64f32(<64 x float>* %a, <64 x float>* %m_ptr, <64 x float>* %res_ptr) nounwind { define void @masked_load_v64f32(<64 x float>* %a, <64 x float>* %m_ptr, <64 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v64f32: ; CHECK-LABEL: masked_load_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: li a4, 32 ; CHECK-NEXT: li a4, 32
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v16, (a1) ; CHECK-NEXT: vle32.v v16, (a1)
; CHECK-NEXT: vle32.v v24, (a3) ; CHECK-NEXT: vle32.v v24, (a3)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v8, v16, ft0 ; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vmfeq.vf v0, v24, ft0 ; CHECK-NEXT: vmfeq.vf v0, v24, fa0
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle32.v v16, (a1), v0.t ; CHECK-NEXT: vle32.v v16, (a1), v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128 ; CHECK-NEXT: addi a0, a2, 128
; CHECK-NEXT: vse32.v v16, (a0) ; CHECK-NEXT: vse32.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <64 x float>, <64 x float>* %m_ptr %m = load <64 x float>, <64 x float>* %m_ptr
%mask = fcmp oeq <64 x float> %m, zeroinitializer %mask = fcmp oeq <64 x float> %m, zeroinitializer
%load = call <64 x float> @llvm.masked.load.v64f32(<64 x float>* %a, i32 8, <64 x i1> %mask, <64 x float> undef) %load = call <64 x float> @llvm.masked.load.v64f32(<64 x float>* %a, i32 8, <64 x i1> %mask, <64 x float> undef)
store <64 x float> %load, <64 x float>* %res_ptr store <64 x float> %load, <64 x float>* %res_ptr
ret void ret void
} }
declare <64 x float> @llvm.masked.load.v64f32(<64 x float>*, i32, <64 x i1>, <64 x float>) declare <64 x float> @llvm.masked.load.v64f32(<64 x float>*, i32, <64 x i1>, <64 x float>)
define void @masked_load_v128f16(<128 x half>* %a, <128 x half>* %m_ptr, <128 x half>* %res_ptr) nounwind { define void @masked_load_v128f16(<128 x half>* %a, <128 x half>* %m_ptr, <128 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v128f16: ; CHECK-LABEL: masked_load_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: li a4, 64 ; CHECK-NEXT: li a4, 64
; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v16, (a1) ; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vle16.v v24, (a3) ; CHECK-NEXT: vle16.v v24, (a3)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v8, v16, ft0 ; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vmfeq.vf v0, v24, ft0 ; CHECK-NEXT: vmfeq.vf v0, v24, fa0
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle16.v v16, (a1), v0.t ; CHECK-NEXT: vle16.v v16, (a1), v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128 ; CHECK-NEXT: addi a0, a2, 128
; CHECK-NEXT: vse16.v v16, (a0) ; CHECK-NEXT: vse16.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <128 x half>, <128 x half>* %m_ptr %m = load <128 x half>, <128 x half>* %m_ptr
%mask = fcmp oeq <128 x half> %m, zeroinitializer %mask = fcmp oeq <128 x half> %m, zeroinitializer
%load = call <128 x half> @llvm.masked.load.v128f16(<128 x half>* %a, i32 8, <128 x i1> %mask, <128 x half> undef) %load = call <128 x half> @llvm.masked.load.v128f16(<128 x half>* %a, i32 8, <128 x i1> %mask, <128 x half> undef)
store <128 x half> %load, <128 x half>* %res_ptr store <128 x half> %load, <128 x half>* %res_ptr
ret void ret void
} }
declare <128 x half> @llvm.masked.load.v128f16(<128 x half>*, i32, <128 x i1>, <128 x half>) declare <128 x half> @llvm.masked.load.v128f16(<128 x half>*, i32, <128 x i1>, <128 x half>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind { define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1f16: ; CHECK-LABEL: masked_store_v1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <1 x half>, <1 x half>* %m_ptr %m = load <1 x half>, <1 x half>* %m_ptr
%mask = fcmp oeq <1 x half> %m, zeroinitializer %mask = fcmp oeq <1 x half> %m, zeroinitializer
%val = load <1 x half>, <1 x half>* %val_ptr %val = load <1 x half>, <1 x half>* %val_ptr
call void @llvm.masked.store.v1f16.p0v1f16(<1 x half> %val, <1 x half>* %a, i32 8, <1 x i1> %mask) call void @llvm.masked.store.v1f16.p0v1f16(<1 x half> %val, <1 x half>* %a, i32 8, <1 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v1f16.p0v1f16(<1 x half>, <1 x half>*, i32, <1 x i1>) declare void @llvm.masked.store.v1f16.p0v1f16(<1 x half>, <1 x half>*, i32, <1 x i1>)
define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x float>* %m_ptr) nounwind { define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1f32: ; CHECK-LABEL: masked_store_v1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <1 x float>, <1 x float>* %m_ptr %m = load <1 x float>, <1 x float>* %m_ptr
%mask = fcmp oeq <1 x float> %m, zeroinitializer %mask = fcmp oeq <1 x float> %m, zeroinitializer
%val = load <1 x float>, <1 x float>* %val_ptr %val = load <1 x float>, <1 x float>* %val_ptr
call void @llvm.masked.store.v1f32.p0v1f32(<1 x float> %val, <1 x float>* %a, i32 8, <1 x i1> %mask) call void @llvm.masked.store.v1f32.p0v1f32(<1 x float> %val, <1 x float>* %a, i32 8, <1 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v1f32.p0v1f32(<1 x float>, <1 x float>*, i32, <1 x i1>) declare void @llvm.masked.store.v1f32.p0v1f32(<1 x float>, <1 x float>*, i32, <1 x i1>)
define void @masked_store_v1f64(<1 x double>* %val_ptr, <1 x double>* %a, <1 x double>* %m_ptr) nounwind { define void @masked_store_v1f64(<1 x double>* %val_ptr, <1 x double>* %a, <1 x double>* %m_ptr) nounwind {
; RV32-LABEL: masked_store_v1f64: ; RV32-LABEL: masked_store_v1f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v9, (a0) ; RV32-NEXT: vle64.v v9, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v9, (a1), v0.t ; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_store_v1f64: ; RV64-LABEL: masked_store_v1f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v9, (a0) ; RV64-NEXT: vle64.v v9, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v9, (a1), v0.t ; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <1 x double>, <1 x double>* %m_ptr %m = load <1 x double>, <1 x double>* %m_ptr
%mask = fcmp oeq <1 x double> %m, zeroinitializer %mask = fcmp oeq <1 x double> %m, zeroinitializer
%val = load <1 x double>, <1 x double>* %val_ptr %val = load <1 x double>, <1 x double>* %val_ptr
call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> %val, <1 x double>* %a, i32 8, <1 x i1> %mask) call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> %val, <1 x double>* %a, i32 8, <1 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32, <1 x i1>) declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32, <1 x i1>)
define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half>* %m_ptr) nounwind { define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2f16: ; CHECK-LABEL: masked_store_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <2 x half>, <2 x half>* %m_ptr %m = load <2 x half>, <2 x half>* %m_ptr
%mask = fcmp oeq <2 x half> %m, zeroinitializer %mask = fcmp oeq <2 x half> %m, zeroinitializer
%val = load <2 x half>, <2 x half>* %val_ptr %val = load <2 x half>, <2 x half>* %val_ptr
call void @llvm.masked.store.v2f16.p0v2f16(<2 x half> %val, <2 x half>* %a, i32 8, <2 x i1> %mask) call void @llvm.masked.store.v2f16.p0v2f16(<2 x half> %val, <2 x half>* %a, i32 8, <2 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v2f16.p0v2f16(<2 x half>, <2 x half>*, i32, <2 x i1>) declare void @llvm.masked.store.v2f16.p0v2f16(<2 x half>, <2 x half>*, i32, <2 x i1>)
define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x float>* %m_ptr) nounwind { define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2f32: ; CHECK-LABEL: masked_store_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <2 x float>, <2 x float>* %m_ptr %m = load <2 x float>, <2 x float>* %m_ptr
%mask = fcmp oeq <2 x float> %m, zeroinitializer %mask = fcmp oeq <2 x float> %m, zeroinitializer
%val = load <2 x float>, <2 x float>* %val_ptr %val = load <2 x float>, <2 x float>* %val_ptr
call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %a, i32 8, <2 x i1> %mask) call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %a, i32 8, <2 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>) declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)
define void @masked_store_v2f64(<2 x double>* %val_ptr, <2 x double>* %a, <2 x double>* %m_ptr) nounwind { define void @masked_store_v2f64(<2 x double>* %val_ptr, <2 x double>* %a, <2 x double>* %m_ptr) nounwind {
; RV32-LABEL: masked_store_v2f64: ; RV32-LABEL: masked_store_v2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v9, (a0) ; RV32-NEXT: vle64.v v9, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v9, (a1), v0.t ; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_store_v2f64: ; RV64-LABEL: masked_store_v2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v9, (a0) ; RV64-NEXT: vle64.v v9, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v9, (a1), v0.t ; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <2 x double>, <2 x double>* %m_ptr %m = load <2 x double>, <2 x double>* %m_ptr
%mask = fcmp oeq <2 x double> %m, zeroinitializer %mask = fcmp oeq <2 x double> %m, zeroinitializer
%val = load <2 x double>, <2 x double>* %val_ptr %val = load <2 x double>, <2 x double>* %val_ptr
call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %a, i32 8, <2 x i1> %mask) call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %a, i32 8, <2 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>) declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half>* %m_ptr) nounwind { define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v4f16: ; CHECK-LABEL: masked_store_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <4 x half>, <4 x half>* %m_ptr %m = load <4 x half>, <4 x half>* %m_ptr
%mask = fcmp oeq <4 x half> %m, zeroinitializer %mask = fcmp oeq <4 x half> %m, zeroinitializer
%val = load <4 x half>, <4 x half>* %val_ptr %val = load <4 x half>, <4 x half>* %val_ptr
call void @llvm.masked.store.v4f16.p0v4f16(<4 x half> %val, <4 x half>* %a, i32 8, <4 x i1> %mask) call void @llvm.masked.store.v4f16.p0v4f16(<4 x half> %val, <4 x half>* %a, i32 8, <4 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v4f16.p0v4f16(<4 x half>, <4 x half>*, i32, <4 x i1>) declare void @llvm.masked.store.v4f16.p0v4f16(<4 x half>, <4 x half>*, i32, <4 x i1>)
define void @masked_store_v4f32(<4 x float>* %val_ptr, <4 x float>* %a, <4 x float>* %m_ptr) nounwind { define void @masked_store_v4f32(<4 x float>* %val_ptr, <4 x float>* %a, <4 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v4f32: ; CHECK-LABEL: masked_store_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <4 x float>, <4 x float>* %m_ptr %m = load <4 x float>, <4 x float>* %m_ptr
%mask = fcmp oeq <4 x float> %m, zeroinitializer %mask = fcmp oeq <4 x float> %m, zeroinitializer
%val = load <4 x float>, <4 x float>* %val_ptr %val = load <4 x float>, <4 x float>* %val_ptr
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %val, <4 x float>* %a, i32 8, <4 x i1> %mask) call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %val, <4 x float>* %a, i32 8, <4 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)
define void @masked_store_v4f64(<4 x double>* %val_ptr, <4 x double>* %a, <4 x double>* %m_ptr) nounwind { define void @masked_store_v4f64(<4 x double>* %val_ptr, <4 x double>* %a, <4 x double>* %m_ptr) nounwind {
; RV32-LABEL: masked_store_v4f64: ; RV32-LABEL: masked_store_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v10, (a0) ; RV32-NEXT: vle64.v v10, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v10, (a1), v0.t ; RV32-NEXT: vse64.v v10, (a1), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_store_v4f64: ; RV64-LABEL: masked_store_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v10, (a0) ; RV64-NEXT: vle64.v v10, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v10, (a1), v0.t ; RV64-NEXT: vse64.v v10, (a1), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <4 x double>, <4 x double>* %m_ptr %m = load <4 x double>, <4 x double>* %m_ptr
%mask = fcmp oeq <4 x double> %m, zeroinitializer %mask = fcmp oeq <4 x double> %m, zeroinitializer
%val = load <4 x double>, <4 x double>* %val_ptr %val = load <4 x double>, <4 x double>* %val_ptr
call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %val, <4 x double>* %a, i32 8, <4 x i1> %mask) call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %val, <4 x double>* %a, i32 8, <4 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v4f64.p0v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>) declare void @llvm.masked.store.v4f64.p0v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>)
define void @masked_store_v8f16(<8 x half>* %val_ptr, <8 x half>* %a, <8 x half>* %m_ptr) nounwind { define void @masked_store_v8f16(<8 x half>* %val_ptr, <8 x half>* %a, <8 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v8f16: ; CHECK-LABEL: masked_store_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <8 x half>, <8 x half>* %m_ptr %m = load <8 x half>, <8 x half>* %m_ptr
%mask = fcmp oeq <8 x half> %m, zeroinitializer %mask = fcmp oeq <8 x half> %m, zeroinitializer
%val = load <8 x half>, <8 x half>* %val_ptr %val = load <8 x half>, <8 x half>* %val_ptr
call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %val, <8 x half>* %a, i32 8, <8 x i1> %mask) call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %val, <8 x half>* %a, i32 8, <8 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v8f16.p0v8f16(<8 x half>, <8 x half>*, i32, <8 x i1>) declare void @llvm.masked.store.v8f16.p0v8f16(<8 x half>, <8 x half>*, i32, <8 x i1>)
define void @masked_store_v8f32(<8 x float>* %val_ptr, <8 x float>* %a, <8 x float>* %m_ptr) nounwind { define void @masked_store_v8f32(<8 x float>* %val_ptr, <8 x float>* %a, <8 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v8f32: ; CHECK-LABEL: masked_store_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v10, (a1), v0.t ; CHECK-NEXT: vse32.v v10, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <8 x float>, <8 x float>* %m_ptr %m = load <8 x float>, <8 x float>* %m_ptr
%mask = fcmp oeq <8 x float> %m, zeroinitializer %mask = fcmp oeq <8 x float> %m, zeroinitializer
%val = load <8 x float>, <8 x float>* %val_ptr %val = load <8 x float>, <8 x float>* %val_ptr
call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %val, <8 x float>* %a, i32 8, <8 x i1> %mask) call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %val, <8 x float>* %a, i32 8, <8 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>) declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
define void @masked_store_v8f64(<8 x double>* %val_ptr, <8 x double>* %a, <8 x double>* %m_ptr) nounwind { define void @masked_store_v8f64(<8 x double>* %val_ptr, <8 x double>* %a, <8 x double>* %m_ptr) nounwind {
; RV32-LABEL: masked_store_v8f64: ; RV32-LABEL: masked_store_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v12, (a0) ; RV32-NEXT: vle64.v v12, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v12, (a1), v0.t ; RV32-NEXT: vse64.v v12, (a1), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_store_v8f64: ; RV64-LABEL: masked_store_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: vle64.v v12, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v12, (a1), v0.t ; RV64-NEXT: vse64.v v12, (a1), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <8 x double>, <8 x double>* %m_ptr %m = load <8 x double>, <8 x double>* %m_ptr
%mask = fcmp oeq <8 x double> %m, zeroinitializer %mask = fcmp oeq <8 x double> %m, zeroinitializer
%val = load <8 x double>, <8 x double>* %val_ptr %val = load <8 x double>, <8 x double>* %val_ptr
call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %val, <8 x double>* %a, i32 8, <8 x i1> %mask) call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %val, <8 x double>* %a, i32 8, <8 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>) declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
define void @masked_store_v16f16(<16 x half>* %val_ptr, <16 x half>* %a, <16 x half>* %m_ptr) nounwind { define void @masked_store_v16f16(<16 x half>* %val_ptr, <16 x half>* %a, <16 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v16f16: ; CHECK-LABEL: masked_store_v16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v10, (a1), v0.t ; CHECK-NEXT: vse16.v v10, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <16 x half>, <16 x half>* %m_ptr %m = load <16 x half>, <16 x half>* %m_ptr
%mask = fcmp oeq <16 x half> %m, zeroinitializer %mask = fcmp oeq <16 x half> %m, zeroinitializer
%val = load <16 x half>, <16 x half>* %val_ptr %val = load <16 x half>, <16 x half>* %val_ptr
call void @llvm.masked.store.v16f16.p0v16f16(<16 x half> %val, <16 x half>* %a, i32 8, <16 x i1> %mask) call void @llvm.masked.store.v16f16.p0v16f16(<16 x half> %val, <16 x half>* %a, i32 8, <16 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v16f16.p0v16f16(<16 x half>, <16 x half>*, i32, <16 x i1>) declare void @llvm.masked.store.v16f16.p0v16f16(<16 x half>, <16 x half>*, i32, <16 x i1>)
define void @masked_store_v16f32(<16 x float>* %val_ptr, <16 x float>* %a, <16 x float>* %m_ptr) nounwind { define void @masked_store_v16f32(<16 x float>* %val_ptr, <16 x float>* %a, <16 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v16f32: ; CHECK-LABEL: masked_store_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v12, (a1), v0.t ; CHECK-NEXT: vse32.v v12, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <16 x float>, <16 x float>* %m_ptr %m = load <16 x float>, <16 x float>* %m_ptr
%mask = fcmp oeq <16 x float> %m, zeroinitializer %mask = fcmp oeq <16 x float> %m, zeroinitializer
%val = load <16 x float>, <16 x float>* %val_ptr %val = load <16 x float>, <16 x float>* %val_ptr
call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %val, <16 x float>* %a, i32 8, <16 x i1> %mask) call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %val, <16 x float>* %a, i32 8, <16 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
define void @masked_store_v16f64(<16 x double>* %val_ptr, <16 x double>* %a, <16 x double>* %m_ptr) nounwind { define void @masked_store_v16f64(<16 x double>* %val_ptr, <16 x double>* %a, <16 x double>* %m_ptr) nounwind {
; RV32-LABEL: masked_store_v16f64: ; RV32-LABEL: masked_store_v16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vse64.v v16, (a1), v0.t ; RV32-NEXT: vse64.v v16, (a1), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_store_v16f64: ; RV64-LABEL: masked_store_v16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vse64.v v16, (a1), v0.t ; RV64-NEXT: vse64.v v16, (a1), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%m = load <16 x double>, <16 x double>* %m_ptr %m = load <16 x double>, <16 x double>* %m_ptr
%mask = fcmp oeq <16 x double> %m, zeroinitializer %mask = fcmp oeq <16 x double> %m, zeroinitializer
%val = load <16 x double>, <16 x double>* %val_ptr %val = load <16 x double>, <16 x double>* %val_ptr
call void @llvm.masked.store.v16f64.p0v16f64(<16 x double> %val, <16 x double>* %a, i32 8, <16 x i1> %mask) call void @llvm.masked.store.v16f64.p0v16f64(<16 x double> %val, <16 x double>* %a, i32 8, <16 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v16f64.p0v16f64(<16 x double>, <16 x double>*, i32, <16 x i1>) declare void @llvm.masked.store.v16f64.p0v16f64(<16 x double>, <16 x double>*, i32, <16 x i1>)
define void @masked_store_v32f16(<32 x half>* %val_ptr, <32 x half>* %a, <32 x half>* %m_ptr) nounwind { define void @masked_store_v32f16(<32 x half>* %val_ptr, <32 x half>* %a, <32 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v32f16: ; CHECK-LABEL: masked_store_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v12, (a0) ; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v12, (a1), v0.t ; CHECK-NEXT: vse16.v v12, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <32 x half>, <32 x half>* %m_ptr %m = load <32 x half>, <32 x half>* %m_ptr
%mask = fcmp oeq <32 x half> %m, zeroinitializer %mask = fcmp oeq <32 x half> %m, zeroinitializer
%val = load <32 x half>, <32 x half>* %val_ptr %val = load <32 x half>, <32 x half>* %val_ptr
call void @llvm.masked.store.v32f16.p0v32f16(<32 x half> %val, <32 x half>* %a, i32 8, <32 x i1> %mask) call void @llvm.masked.store.v32f16.p0v32f16(<32 x half> %val, <32 x half>* %a, i32 8, <32 x i1> %mask)
ret void ret void
} }
declare void @llvm.masked.store.v32f16.p0v32f16(<32 x half>, <32 x half>*, i32, <32 x i1>) declare void @llvm.masked.store.v32f16.p0v32f16(<32 x half>, <32 x half>*, i32, <32 x i1>)
define void @masked_store_v32f32(<32 x float>* %val_ptr, <32 x float>* %a, <32 x float>* %m_ptr) nounwind { define void @masked_store_v32f32(<32 x float>* %val_ptr, <32 x float>* %a, <32 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v32f32: ; CHECK-LABEL: masked_store_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse32.v v16, (a1), v0.t ; CHECK-NEXT: vse32.v v16, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <32 x float>, <32 x float>* %m_ptr %m = load <32 x float>, <32 x float>* %m_ptr
%mask = fcmp oeq <32 x float> %m, zeroinitializer %mask = fcmp oeq <32 x float> %m, zeroinitializer
%val = load <32 x float>, <32 x float>* %val_ptr %val = load <32 x float>, <32 x float>* %val_ptr
call void @llvm.masked.store.v32f32.p0v32f32(<32 x float> %val, <32 x float>* %a, i32 8, <32 x i1> %mask) call void @llvm.masked.store.v32f32.p0v32f32(<32 x float> %val, <32 x float>* %a, i32 8, <32 x i1> %mask)
ret void ret void
} }
Show All 10 Lines
; RV32-NEXT: vle64.v v8, (a2) ; RV32-NEXT: vle64.v v8, (a2)
; RV32-NEXT: addi a2, a2, 128 ; RV32-NEXT: addi a2, a2, 128
; RV32-NEXT: vle64.v v16, (a2) ; RV32-NEXT: vle64.v v16, (a2)
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, fa0
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmfeq.vf v8, v16, ft0 ; RV32-NEXT: vmfeq.vf v8, v16, fa0
; RV32-NEXT: vse64.v v24, (a1), v0.t ; RV32-NEXT: vse64.v v24, (a1), v0.t
; RV32-NEXT: addi a0, a1, 128 ; RV32-NEXT: addi a0, a1, 128
; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vse64.v v8, (a0), v0.t ; RV32-NEXT: vse64.v v8, (a0), v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
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; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: addi a2, a2, 128 ; RV64-NEXT: addi a2, a2, 128
; RV64-NEXT: vle64.v v16, (a2) ; RV64-NEXT: vle64.v v16, (a2)
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, fa0
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16 ; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vmfeq.vf v8, v16, ft0 ; RV64-NEXT: vmfeq.vf v8, v16, fa0
; RV64-NEXT: vse64.v v24, (a1), v0.t ; RV64-NEXT: vse64.v v24, (a1), v0.t
; RV64-NEXT: addi a0, a1, 128 ; RV64-NEXT: addi a0, a1, 128
; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0), v0.t ; RV64-NEXT: vse64.v v8, (a0), v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
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define void @masked_store_v64f16(<64 x half>* %val_ptr, <64 x half>* %a, <64 x half>* %m_ptr) nounwind { define void @masked_store_v64f16(<64 x half>* %val_ptr, <64 x half>* %a, <64 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v64f16: ; CHECK-LABEL: masked_store_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 64 ; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vse16.v v16, (a1), v0.t ; CHECK-NEXT: vse16.v v16, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%m = load <64 x half>, <64 x half>* %m_ptr %m = load <64 x half>, <64 x half>* %m_ptr
%mask = fcmp oeq <64 x half> %m, zeroinitializer %mask = fcmp oeq <64 x half> %m, zeroinitializer
%val = load <64 x half>, <64 x half>* %val_ptr %val = load <64 x half>, <64 x half>* %val_ptr
call void @llvm.masked.store.v64f16.p0v64f16(<64 x half> %val, <64 x half>* %a, i32 8, <64 x i1> %mask) call void @llvm.masked.store.v64f16.p0v64f16(<64 x half> %val, <64 x half>* %a, i32 8, <64 x i1> %mask)
ret void ret void
} }
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; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: addi a2, a2, 128 ; CHECK-NEXT: addi a2, a2, 128
; CHECK-NEXT: vle32.v v16, (a2) ; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vf v8, v16, ft0 ; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vse32.v v24, (a1), v0.t ; CHECK-NEXT: vse32.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128 ; CHECK-NEXT: addi a0, a1, 128
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a0), v0.t ; CHECK-NEXT: vse32.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
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; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vle16.v v8, (a2)
; CHECK-NEXT: addi a2, a2, 128 ; CHECK-NEXT: addi a2, a2, 128
; CHECK-NEXT: vle16.v v16, (a2) ; CHECK-NEXT: vle16.v v16, (a2)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vf v8, v16, ft0 ; CHECK-NEXT: vmfeq.vf v8, v16, fa0
; CHECK-NEXT: vse16.v v24, (a1), v0.t ; CHECK-NEXT: vse16.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128 ; CHECK-NEXT: addi a0, a1, 128
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse16.v v8, (a0), v0.t ; CHECK-NEXT: vse16.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bltu a0, a2, .LBB8_4 ; CHECK-NEXT: bltu a0, a2, .LBB8_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: .LBB8_4: ; CHECK-NEXT: .LBB8_4:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl) %r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r ret float %r
} }
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; CHECK-NEXT: bltu a0, a2, .LBB9_4 ; CHECK-NEXT: bltu a0, a2, .LBB9_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: .LBB9_4: ; CHECK-NEXT: .LBB9_4:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl) %r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r ret float %r
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>) declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) { define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v1f16: ; CHECK-LABEL: vreduce_fadd_v1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x %v = load <1 x half>, <1 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) { define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f16: ; CHECK-LABEL: vreduce_ord_fadd_v1f16:
Show All 11 Lines
declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>) declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) { define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v2f16: ; CHECK-LABEL: vreduce_fadd_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x %v = load <2 x half>, <2 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) { define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f16: ; CHECK-LABEL: vreduce_ord_fadd_v2f16:
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declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>) declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) { define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v4f16: ; CHECK-LABEL: vreduce_fadd_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) { define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f16: ; CHECK-LABEL: vreduce_ord_fadd_v4f16:
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declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>) declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) { define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v8f16: ; CHECK-LABEL: vreduce_fadd_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x %v = load <8 x half>, <8 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v8f16(<8 x half>* %x, half %s) { define half @vreduce_ord_fadd_v8f16(<8 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f16: ; CHECK-LABEL: vreduce_ord_fadd_v8f16:
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declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>) declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) { define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v16f16: ; CHECK-LABEL: vreduce_fadd_v16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vfmv.s.f v10, ft0 ; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x %v = load <16 x half>, <16 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) { define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v16f16: ; CHECK-LABEL: vreduce_ord_fadd_v16f16:
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declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>) declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) { define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v32f16: ; CHECK-LABEL: vreduce_fadd_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v12, ft0 ; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x %v = load <32 x half>, <32 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) { define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f16: ; CHECK-LABEL: vreduce_ord_fadd_v32f16:
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declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>) declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) { define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v64f16: ; CHECK-LABEL: vreduce_fadd_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x %v = load <64 x half>, <64 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) { define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v64f16: ; CHECK-LABEL: vreduce_ord_fadd_v64f16:
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; CHECK-LABEL: vreduce_fadd_v128f16: ; CHECK-LABEL: vreduce_fadd_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x %v = load <128 x half>, <128 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) { define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v128f16: ; CHECK-LABEL: vreduce_ord_fadd_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v16, v16, v24 ; CHECK-NEXT: vfredosum.vs v16, v16, v24
; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v16 ; CHECK-NEXT: vfredosum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x %v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>) declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) { define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v1f32: ; CHECK-LABEL: vreduce_fadd_v1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x %v = load <1 x float>, <1 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) { define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f32: ; CHECK-LABEL: vreduce_ord_fadd_v1f32:
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define float @vreduce_fwadd_v1f32(<1 x half>* %x, float %s) { define float @vreduce_fwadd_v1f32(<1 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v1f32: ; CHECK-LABEL: vreduce_fwadd_v1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v9 ; CHECK-NEXT: vfmv.f.s fa1, v9
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x %v = load <1 x half>, <1 x half>* %x
%e = fpext <1 x half> %v to <1 x float> %e = fpext <1 x half> %v to <1 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v1f32(<1 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v1f32(<1 x half>* %x, float %s) {
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declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) { define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v2f32: ; CHECK-LABEL: vreduce_fadd_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x %v = load <2 x float>, <2 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) { define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f32: ; CHECK-LABEL: vreduce_ord_fadd_v2f32:
Show All 9 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
define float @vreduce_fwadd_v2f32(<2 x half>* %x, float %s) { define float @vreduce_fwadd_v2f32(<2 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v2f32: ; CHECK-LABEL: vreduce_fwadd_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x %v = load <2 x half>, <2 x half>* %x
%e = fpext <2 x half> %v to <2 x float> %e = fpext <2 x half> %v to <2 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v2f32(<2 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v2f32(<2 x half>* %x, float %s) {
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declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) { define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v4f32: ; CHECK-LABEL: vreduce_fadd_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v4f32(<4 x float>* %x, float %s) { define float @vreduce_ord_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f32: ; CHECK-LABEL: vreduce_ord_fadd_v4f32:
Show All 9 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
define float @vreduce_fwadd_v4f32(<4 x half>* %x, float %s) { define float @vreduce_fwadd_v4f32(<4 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v4f32: ; CHECK-LABEL: vreduce_fwadd_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%e = fpext <4 x half> %v to <4 x float> %e = fpext <4 x half> %v to <4 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v4f32(<4 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v4f32(<4 x half>* %x, float %s) {
Show All 16 Lines
declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) { define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v8f32: ; CHECK-LABEL: vreduce_fadd_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vfmv.s.f v10, ft0 ; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x float>, <8 x float>* %x %v = load <8 x float>, <8 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) { define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f32: ; CHECK-LABEL: vreduce_ord_fadd_v8f32:
Show All 9 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
define float @vreduce_fwadd_v8f32(<8 x half>* %x, float %s) { define float @vreduce_fwadd_v8f32(<8 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v8f32: ; CHECK-LABEL: vreduce_fwadd_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x %v = load <8 x half>, <8 x half>* %x
%e = fpext <8 x half> %v to <8 x float> %e = fpext <8 x half> %v to <8 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v8f32(<8 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v8f32(<8 x half>* %x, float %s) {
Show All 16 Lines
declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>) declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) { define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v16f32: ; CHECK-LABEL: vreduce_fadd_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vfmv.s.f v12, ft0 ; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x %v = load <16 x float>, <16 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) { define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v16f32: ; CHECK-LABEL: vreduce_ord_fadd_v16f32:
Show All 9 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
define float @vreduce_fwadd_v16f32(<16 x half>* %x, float %s) { define float @vreduce_fwadd_v16f32(<16 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v16f32: ; CHECK-LABEL: vreduce_fwadd_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v10, ft0 ; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v10 ; CHECK-NEXT: vfwredusum.vs v8, v8, v10
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x %v = load <16 x half>, <16 x half>* %x
%e = fpext <16 x half> %v to <16 x float> %e = fpext <16 x half> %v to <16 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v16f32(<16 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v16f32(<16 x half>* %x, float %s) {
Show All 17 Lines
declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>) declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) { define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v32f32: ; CHECK-LABEL: vreduce_fadd_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x float>, <32 x float>* %x %v = load <32 x float>, <32 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) { define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f32: ; CHECK-LABEL: vreduce_ord_fadd_v32f32:
Show All 13 Lines
} }
define float @vreduce_fwadd_v32f32(<32 x half>* %x, float %s) { define float @vreduce_fwadd_v32f32(<32 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v32f32: ; CHECK-LABEL: vreduce_fwadd_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v12, ft0 ; CHECK-NEXT: vfmv.s.f v12, fa1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v12 ; CHECK-NEXT: vfwredusum.vs v8, v8, v12
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x %v = load <32 x half>, <32 x half>* %x
%e = fpext <32 x half> %v to <32 x float> %e = fpext <32 x half> %v to <32 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v32f32(<32 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v32f32(<32 x half>* %x, float %s) {
Show All 21 Lines
; CHECK-LABEL: vreduce_fadd_v64f32: ; CHECK-LABEL: vreduce_fadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x %v = load <64 x float>, <64 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) { define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v64f32: ; CHECK-LABEL: vreduce_ord_fadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v16, v16, v24 ; CHECK-NEXT: vfredosum.vs v16, v16, v24
; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v16 ; CHECK-NEXT: vfredosum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x %v = load <64 x float>, <64 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fwadd_v64f32(<64 x half>* %x, float %s) { define float @vreduce_fwadd_v64f32(<64 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_fwadd_v64f32: ; CHECK-LABEL: vreduce_fwadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v16, v8, a0 ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v24, v16 ; CHECK-NEXT: vfwcvt.f.f.v v24, v16
; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfadd.vv v8, v16, v24 ; CHECK-NEXT: vfadd.vv v8, v16, v24
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x %v = load <64 x half>, <64 x half>* %x
%e = fpext <64 x half> %v to <64 x float> %e = fpext <64 x half> %v to <64 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v64f32(<64 x half>* %x, float %s) { define float @vreduce_ord_fwadd_v64f32(<64 x half>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fwadd_v64f32: ; CHECK-LABEL: vreduce_ord_fwadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v16, v16, v24 ; CHECK-NEXT: vfwredosum.vs v16, v16, v24
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v8, v8, v16 ; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x %v = load <64 x half>, <64 x half>* %x
%e = fpext <64 x half> %v to <64 x float> %e = fpext <64 x half> %v to <64 x float>
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e) %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>) declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)
define double @vreduce_fadd_v1f64(<1 x double>* %x, double %s) { define double @vreduce_fadd_v1f64(<1 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v1f64: ; CHECK-LABEL: vreduce_fadd_v1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <1 x double>, <1 x double>* %x %v = load <1 x double>, <1 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v1f64(<1 x double>* %x, double %s) { define double @vreduce_ord_fadd_v1f64(<1 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f64: ; CHECK-LABEL: vreduce_ord_fadd_v1f64:
Show All 11 Lines
define double @vreduce_fwadd_v1f64(<1 x float>* %x, double %s) { define double @vreduce_fwadd_v1f64(<1 x float>* %x, double %s) {
; CHECK-LABEL: vreduce_fwadd_v1f64: ; CHECK-LABEL: vreduce_fwadd_v1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v9 ; CHECK-NEXT: vfmv.f.s fa1, v9
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x %v = load <1 x float>, <1 x float>* %x
%e = fpext <1 x float> %v to <1 x double> %e = fpext <1 x float> %v to <1 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v1f64(<1 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v1f64(<1 x float>* %x, double %s) {
Show All 16 Lines
declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) { define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) {
; RV32-LABEL: vreduce_fadd_v2f64: ; RV32-LABEL: vreduce_fadd_v2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v9 ; RV32-NEXT: vfredusum.vs v8, v8, v9
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_v2f64: ; RV64-LABEL: vreduce_fadd_v2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v9 ; RV64-NEXT: vfredusum.vs v8, v8, v9
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <2 x double>, <2 x double>* %x %v = load <2 x double>, <2 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v2f64(<2 x double>* %x, double %s) { define double @vreduce_ord_fadd_v2f64(<2 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f64: ; CHECK-LABEL: vreduce_ord_fadd_v2f64:
Show All 9 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
define double @vreduce_fwadd_v2f64(<2 x float>* %x, double %s) { define double @vreduce_fwadd_v2f64(<2 x float>* %x, double %s) {
; RV32-LABEL: vreduce_fwadd_v2f64: ; RV32-LABEL: vreduce_fwadd_v2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9 ; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_v2f64: ; RV64-LABEL: vreduce_fwadd_v2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9 ; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <2 x float>, <2 x float>* %x %v = load <2 x float>, <2 x float>* %x
%e = fpext <2 x float> %v to <2 x double> %e = fpext <2 x float> %v to <2 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v2f64(<2 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v2f64(<2 x float>* %x, double %s) {
Show All 16 Lines
declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>) declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) { define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) {
; RV32-LABEL: vreduce_fadd_v4f64: ; RV32-LABEL: vreduce_fadd_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v10, ft0 ; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v10 ; RV32-NEXT: vfredusum.vs v8, v8, v10
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_v4f64: ; RV64-LABEL: vreduce_fadd_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v10, ft0 ; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v10 ; RV64-NEXT: vfredusum.vs v8, v8, v10
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) { define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f64: ; CHECK-LABEL: vreduce_ord_fadd_v4f64:
Show All 9 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
define double @vreduce_fwadd_v4f64(<4 x float>* %x, double %s) { define double @vreduce_fwadd_v4f64(<4 x float>* %x, double %s) {
; RV32-LABEL: vreduce_fwadd_v4f64: ; RV32-LABEL: vreduce_fwadd_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9 ; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_v4f64: ; RV64-LABEL: vreduce_fwadd_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9 ; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%e = fpext <4 x float> %v to <4 x double> %e = fpext <4 x float> %v to <4 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v4f64(<4 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v4f64(<4 x float>* %x, double %s) {
Show All 16 Lines
declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>) declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) { define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) {
; RV32-LABEL: vreduce_fadd_v8f64: ; RV32-LABEL: vreduce_fadd_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v12, ft0 ; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v12 ; RV32-NEXT: vfredusum.vs v8, v8, v12
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_v8f64: ; RV64-LABEL: vreduce_fadd_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v12, ft0 ; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v12 ; RV64-NEXT: vfredusum.vs v8, v8, v12
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <8 x double>, <8 x double>* %x %v = load <8 x double>, <8 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) { define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f64: ; CHECK-LABEL: vreduce_ord_fadd_v8f64:
Show All 9 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
define double @vreduce_fwadd_v8f64(<8 x float>* %x, double %s) { define double @vreduce_fwadd_v8f64(<8 x float>* %x, double %s) {
; RV32-LABEL: vreduce_fwadd_v8f64: ; RV32-LABEL: vreduce_fwadd_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v10, ft0 ; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v10 ; RV32-NEXT: vfwredusum.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_v8f64: ; RV64-LABEL: vreduce_fwadd_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v10, ft0 ; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v10 ; RV64-NEXT: vfwredusum.vs v8, v8, v10
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <8 x float>, <8 x float>* %x %v = load <8 x float>, <8 x float>* %x
%e = fpext <8 x float> %v to <8 x double> %e = fpext <8 x float> %v to <8 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v8f64(<8 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v8f64(<8 x float>* %x, double %s) {
Show All 16 Lines
declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>) declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) { define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) {
; RV32-LABEL: vreduce_fadd_v16f64: ; RV32-LABEL: vreduce_fadd_v16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v16, ft0 ; RV32-NEXT: vfmv.s.f v16, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v16 ; RV32-NEXT: vfredusum.vs v8, v8, v16
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_v16f64: ; RV64-LABEL: vreduce_fadd_v16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v16, ft0 ; RV64-NEXT: vfmv.s.f v16, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v16 ; RV64-NEXT: vfredusum.vs v8, v8, v16
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <16 x double>, <16 x double>* %x %v = load <16 x double>, <16 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) { define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v16f64: ; CHECK-LABEL: vreduce_ord_fadd_v16f64:
Show All 9 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
define double @vreduce_fwadd_v16f64(<16 x float>* %x, double %s) { define double @vreduce_fwadd_v16f64(<16 x float>* %x, double %s) {
; RV32-LABEL: vreduce_fwadd_v16f64: ; RV32-LABEL: vreduce_fwadd_v16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v12, ft0 ; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v12 ; RV32-NEXT: vfwredusum.vs v8, v8, v12
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_v16f64: ; RV64-LABEL: vreduce_fwadd_v16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v12, ft0 ; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v12 ; RV64-NEXT: vfwredusum.vs v8, v8, v12
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <16 x float>, <16 x float>* %x %v = load <16 x float>, <16 x float>* %x
%e = fpext <16 x float> %v to <16 x double> %e = fpext <16 x float> %v to <16 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v16f64(<16 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v16f64(<16 x float>* %x, double %s) {
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define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) { define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) {
; RV32-LABEL: vreduce_fadd_v32f64: ; RV32-LABEL: vreduce_fadd_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v24, ft0 ; RV32-NEXT: vfmv.s.f v24, fa1
; RV32-NEXT: vfadd.vv v8, v8, v16 ; RV32-NEXT: vfadd.vv v8, v8, v16
; RV32-NEXT: vfredusum.vs v8, v8, v24 ; RV32-NEXT: vfredusum.vs v8, v8, v24
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_v32f64: ; RV64-LABEL: vreduce_fadd_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v24, ft0 ; RV64-NEXT: vfmv.s.f v24, fa1
; RV64-NEXT: vfadd.vv v8, v8, v16 ; RV64-NEXT: vfadd.vv v8, v8, v16
; RV64-NEXT: vfredusum.vs v8, v8, v24 ; RV64-NEXT: vfredusum.vs v8, v8, v24
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <32 x double>, <32 x double>* %x %v = load <32 x double>, <32 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) { define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f64: ; CHECK-LABEL: vreduce_ord_fadd_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v16, (a0) ; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v24 ; CHECK-NEXT: vfredosum.vs v8, v8, v24
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vfredosum.vs v8, v16, v8 ; CHECK-NEXT: vfredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x %v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fwadd_v32f64(<32 x float>* %x, double %s) { define double @vreduce_fwadd_v32f64(<32 x float>* %x, double %s) {
; RV32-LABEL: vreduce_fwadd_v32f64: ; RV32-LABEL: vreduce_fwadd_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu
; RV32-NEXT: vslidedown.vi v16, v8, 16 ; RV32-NEXT: vslidedown.vi v16, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vfwcvt.f.f.v v24, v16 ; RV32-NEXT: vfwcvt.f.f.v v24, v16
; RV32-NEXT: vfwcvt.f.f.v v16, v8 ; RV32-NEXT: vfwcvt.f.f.v v16, v8
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfadd.vv v8, v16, v24 ; RV32-NEXT: vfadd.vv v8, v16, v24
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vfmv.s.f v16, ft0 ; RV32-NEXT: vfmv.s.f v16, fa1
; RV32-NEXT: vfredusum.vs v8, v8, v16 ; RV32-NEXT: vfredusum.vs v8, v8, v16
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_v32f64: ; RV64-LABEL: vreduce_fwadd_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a1, 32 ; RV64-NEXT: li a1, 32
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV64-NEXT: vfwcvt.f.f.v v24, v16 ; RV64-NEXT: vfwcvt.f.f.v v24, v16
; RV64-NEXT: vfwcvt.f.f.v v16, v8 ; RV64-NEXT: vfwcvt.f.f.v v16, v8
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfadd.vv v8, v16, v24 ; RV64-NEXT: vfadd.vv v8, v16, v24
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vfmv.s.f v16, ft0 ; RV64-NEXT: vfmv.s.f v16, fa1
; RV64-NEXT: vfredusum.vs v8, v8, v16 ; RV64-NEXT: vfredusum.vs v8, v8, v16
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <32 x float>, <32 x float>* %x %v = load <32 x float>, <32 x float>* %x
%e = fpext <32 x float> %v to <32 x double> %e = fpext <32 x float> %v to <32 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v32f64(<32 x float>* %x, double %s) { define double @vreduce_ord_fwadd_v32f64(<32 x float>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fwadd_v32f64: ; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v16, v16, v24 ; CHECK-NEXT: vfwredosum.vs v16, v16, v24
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vfmv.f.s fa0, v16
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v16, ft0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfwredosum.vs v8, v8, v16 ; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x float>, <32 x float>* %x %v = load <32 x float>, <32 x float>* %x
%e = fpext <32 x float> %v to <32 x double> %e = fpext <32 x float> %v to <32 x double>
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e) %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
▲ Show 20 Lines • Show All 612 Lines • ▼ Show 20 Lines
define float @vreduce_nsz_fadd_v4f32(<4 x float>* %x, float %s) { define float @vreduce_nsz_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_nsz_fadd_v4f32: ; CHECK-LABEL: vreduce_nsz_fadd_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) %red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
ret float %red ret float %red
} }

llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: round_nxv1f16: ; CHECK-LABEL: round_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI0_1) ; CHECK-NEXT: lui a0, %hi(.LCPI0_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI0_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.round.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.round.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.round.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.round.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: round_nxv2f16: ; CHECK-LABEL: round_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI1_1) ; CHECK-NEXT: lui a0, %hi(.LCPI1_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI1_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI1_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.round.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.round.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.round.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.round.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: round_nxv4f16: ; CHECK-LABEL: round_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI2_1) ; CHECK-NEXT: lui a0, %hi(.LCPI2_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI2_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI2_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.round.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.round.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.round.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.round.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: round_nxv8f16: ; CHECK-LABEL: round_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: lui a0, %hi(.LCPI3_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI3_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI3_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfadd.vf v10, v10, ft1 ; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.round.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.round.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.round.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.round.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: round_nxv16f16: ; CHECK-LABEL: round_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: lui a0, %hi(.LCPI4_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI4_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI4_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfadd.vf v12, v12, ft1 ; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.round.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.round.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.round.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.round.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: round_nxv32f16: ; CHECK-LABEL: round_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: flh ft1, %lo(.LCPI5_1)(a0) ; CHECK-NEXT: flh fa1, %lo(.LCPI5_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfadd.vf v16, v16, ft1 ; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.round.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.round.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.round.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.round.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: round_nxv1f32: ; CHECK-LABEL: round_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI6_1) ; CHECK-NEXT: lui a0, %hi(.LCPI6_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI6_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI6_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.round.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.round.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.round.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.round.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: round_nxv2f32: ; CHECK-LABEL: round_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI7_1) ; CHECK-NEXT: lui a0, %hi(.LCPI7_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI7_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.round.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.round.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.round.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.round.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: round_nxv4f32: ; CHECK-LABEL: round_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI8_1) ; CHECK-NEXT: lui a0, %hi(.LCPI8_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI8_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI8_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfadd.vf v10, v10, ft1 ; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: round_nxv8f32: ; CHECK-LABEL: round_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI9_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI9_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfadd.vf v12, v12, ft1 ; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: round_nxv16f32: ; CHECK-LABEL: round_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: flw ft1, %lo(.LCPI10_1)(a0) ; CHECK-NEXT: flw fa1, %lo(.LCPI10_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfadd.vf v16, v16, ft1 ; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: round_nxv1f64: ; CHECK-LABEL: round_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI11_1) ; CHECK-NEXT: lui a0, %hi(.LCPI11_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI11_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI11_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfadd.vf v9, v9, ft1 ; CHECK-NEXT: vfadd.vf v9, v9, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v9
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.round.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.round.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.round.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.round.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: round_nxv2f64: ; CHECK-LABEL: round_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI12_1) ; CHECK-NEXT: lui a0, %hi(.LCPI12_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI12_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI12_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfadd.vf v10, v10, ft1 ; CHECK-NEXT: vfadd.vf v10, v10, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v10
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.round.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.round.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.round.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.round.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: round_nxv4f64: ; CHECK-LABEL: round_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI13_1) ; CHECK-NEXT: lui a0, %hi(.LCPI13_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI13_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI13_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfadd.vf v12, v12, ft1 ; CHECK-NEXT: vfadd.vf v12, v12, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v12
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.round.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.round.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.round.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.round.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: round_nxv8f64: ; CHECK-LABEL: round_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: lui a0, %hi(.LCPI14_1) ; CHECK-NEXT: lui a0, %hi(.LCPI14_1)
; CHECK-NEXT: fld ft1, %lo(.LCPI14_1)(a0) ; CHECK-NEXT: fld fa1, %lo(.LCPI14_1)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfadd.vf v16, v16, ft1 ; CHECK-NEXT: vfadd.vf v16, v16, fa1
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.round.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.round.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.round.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.round.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @trunc_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @trunc_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: trunc_nxv1f16: ; CHECK-LABEL: trunc_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @trunc_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @trunc_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: trunc_nxv2f16: ; CHECK-LABEL: trunc_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.trunc.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.trunc.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.trunc.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.trunc.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @trunc_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @trunc_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: trunc_nxv4f16: ; CHECK-LABEL: trunc_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @trunc_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @trunc_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: trunc_nxv8f16: ; CHECK-LABEL: trunc_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.trunc.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.trunc.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.trunc.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.trunc.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @trunc_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @trunc_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: trunc_nxv16f16: ; CHECK-LABEL: trunc_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.trunc.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.trunc.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.trunc.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.trunc.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @trunc_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @trunc_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: trunc_nxv32f16: ; CHECK-LABEL: trunc_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.trunc.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.trunc.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.trunc.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.trunc.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @trunc_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @trunc_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: trunc_nxv1f32: ; CHECK-LABEL: trunc_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @trunc_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @trunc_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: trunc_nxv2f32: ; CHECK-LABEL: trunc_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.trunc.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.trunc.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.trunc.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.trunc.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @trunc_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @trunc_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: trunc_nxv4f32: ; CHECK-LABEL: trunc_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @trunc_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @trunc_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: trunc_nxv8f32: ; CHECK-LABEL: trunc_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.trunc.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.trunc.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.trunc.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.trunc.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: trunc_nxv16f32: ; CHECK-LABEL: trunc_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw fa0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.trunc.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.trunc.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.trunc.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.trunc.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @trunc_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @trunc_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: trunc_nxv1f64: ; CHECK-LABEL: trunc_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfsgnjx.vv v9, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v9, v8, v8
; CHECK-NEXT: vmflt.vf v0, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vfcvt.f.x.v v9, v9 ; CHECK-NEXT: vfcvt.f.x.v v9, v9
; CHECK-NEXT: vfsgnj.vv v9, v9, v8 ; CHECK-NEXT: vfsgnj.vv v9, v9, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: trunc_nxv2f64: ; CHECK-LABEL: trunc_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfsgnjx.vv v10, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v10, v8, v8
; CHECK-NEXT: vmflt.vf v0, v10, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-NEXT: vfcvt.f.x.v v10, v10
; CHECK-NEXT: vfsgnj.vv v10, v10, v8 ; CHECK-NEXT: vfsgnj.vv v10, v10, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.trunc.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.trunc.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.trunc.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.trunc.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: trunc_nxv4f64: ; CHECK-LABEL: trunc_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfsgnjx.vv v12, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v12, v8, v8
; CHECK-NEXT: vmflt.vf v0, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vfcvt.f.x.v v12, v12 ; CHECK-NEXT: vfcvt.f.x.v v12, v12
; CHECK-NEXT: vfsgnj.vv v12, v12, v8 ; CHECK-NEXT: vfsgnj.vv v12, v12, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @trunc_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @trunc_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: trunc_nxv8f64: ; CHECK-LABEL: trunc_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld fa0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfsgnjx.vv v16, v8, v8 ; CHECK-NEXT: vfsgnjx.vv v16, v8, v8
; CHECK-NEXT: vmflt.vf v0, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, fa0
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: vfcvt.f.x.v v16, v16
; CHECK-NEXT: vfsgnj.vv v16, v16, v8 ; CHECK-NEXT: vfsgnj.vv v16, v16, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

Show First 20 Lines • Show All 2,506 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR ; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
; node. Ensure we correctly (custom) lower this. ; node. Ensure we correctly (custom) lower this.
define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) { define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK-LABEL: fcmp_oeq_vf_nx16f64: ; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.d.w ft0, zero ; CHECK-NEXT: fcvt.d.w fa0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfeq.vf v24, v16, ft0 ; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer %vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc ret <vscale x 16 x i1> %vc
} }
attributes #0 = { "no-nans-fp-math"="true" } attributes #0 = { "no-nans-fp-math"="true" }

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

Show First 20 Lines • Show All 2,506 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR ; This fcmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
; node. Ensure we correctly (custom) lower this. ; node. Ensure we correctly (custom) lower this.
define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) { define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK-LABEL: fcmp_oeq_vf_nx16f64: ; CHECK-LABEL: fcmp_oeq_vf_nx16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.d.x ft0, zero ; CHECK-NEXT: fmv.d.x fa0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfeq.vf v24, v16, ft0 ; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer %vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc ret <vscale x 16 x i1> %vc
} }
attributes #0 = { "no-nans-fp-math"="true" } attributes #0 = { "no-nans-fp-math"="true" }

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

Show First 20 Lines • Show All 1,534 Lines • ▼ Show 20 Lines
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB26_7 ; CHECK-NEXT: beqz a4, .LBB26_7
; CHECK-NEXT: .LBB26_5: # %for.body.preheader ; CHECK-NEXT: .LBB26_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB26_6: # %for.body ; CHECK-NEXT: .LBB26_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fmul.s ft0, ft0, fa0 ; CHECK-NEXT: fmul.s fa1, fa1, fa0
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB26_6 ; CHECK-NEXT: bgeu a1, a2, .LBB26_6
; CHECK-NEXT: .LBB26_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB26_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB27_7 ; CHECK-NEXT: beqz a4, .LBB27_7
; CHECK-NEXT: .LBB27_5: # %for.body.preheader ; CHECK-NEXT: .LBB27_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB27_6: # %for.body ; CHECK-NEXT: .LBB27_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fdiv.s ft0, ft0, fa0 ; CHECK-NEXT: fdiv.s fa1, fa1, fa0
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB27_6 ; CHECK-NEXT: bgeu a1, a2, .LBB27_6
; CHECK-NEXT: .LBB27_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB27_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB28_7 ; CHECK-NEXT: beqz a4, .LBB28_7
; CHECK-NEXT: .LBB28_5: # %for.body.preheader ; CHECK-NEXT: .LBB28_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB28_6: # %for.body ; CHECK-NEXT: .LBB28_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fdiv.s ft0, fa0, ft0 ; CHECK-NEXT: fdiv.s fa1, fa0, fa1
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB28_6 ; CHECK-NEXT: bgeu a1, a2, .LBB28_6
; CHECK-NEXT: .LBB28_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB28_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB29_7 ; CHECK-NEXT: beqz a4, .LBB29_7
; CHECK-NEXT: .LBB29_5: # %for.body.preheader ; CHECK-NEXT: .LBB29_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB29_6: # %for.body ; CHECK-NEXT: .LBB29_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fadd.s ft0, ft0, fa0 ; CHECK-NEXT: fadd.s fa1, fa1, fa0
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB29_6 ; CHECK-NEXT: bgeu a1, a2, .LBB29_6
; CHECK-NEXT: .LBB29_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB29_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB30_7 ; CHECK-NEXT: beqz a4, .LBB30_7
; CHECK-NEXT: .LBB30_5: # %for.body.preheader ; CHECK-NEXT: .LBB30_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB30_6: # %for.body ; CHECK-NEXT: .LBB30_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fsub.s ft0, ft0, fa0 ; CHECK-NEXT: fsub.s fa1, fa1, fa0
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB30_6 ; CHECK-NEXT: bgeu a1, a2, .LBB30_6
; CHECK-NEXT: .LBB30_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB30_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB31_7 ; CHECK-NEXT: beqz a4, .LBB31_7
; CHECK-NEXT: .LBB31_5: # %for.body.preheader ; CHECK-NEXT: .LBB31_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a3, -1024 ; CHECK-NEXT: addi a1, a3, -1024
; CHECK-NEXT: slli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB31_6: # %for.body ; CHECK-NEXT: .LBB31_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: fsub.s ft0, fa0, ft0 ; CHECK-NEXT: fsub.s fa1, fa0, fa1
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a1, a1, 1 ; CHECK-NEXT: addi a1, a1, 1
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a1, a2, .LBB31_6 ; CHECK-NEXT: bgeu a1, a2, .LBB31_6
; CHECK-NEXT: .LBB31_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB31_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
%1 = shl i64 %0, 1 %1 = shl i64 %0, 1
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; CHECK-NEXT: beqz a5, .LBB34_7 ; CHECK-NEXT: beqz a5, .LBB34_7
; CHECK-NEXT: .LBB34_5: # %for.body.preheader ; CHECK-NEXT: .LBB34_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a4, -1024 ; CHECK-NEXT: addi a2, a4, -1024
; CHECK-NEXT: slli a3, a4, 2 ; CHECK-NEXT: slli a3, a4, 2
; CHECK-NEXT: add a1, a1, a3 ; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB34_6: # %for.body ; CHECK-NEXT: .LBB34_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: flw ft1, 0(a1) ; CHECK-NEXT: flw fa2, 0(a1)
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: fmadd.s ft0, ft0, fa0, ft1 ; CHECK-NEXT: fmadd.s fa1, fa1, fa0, fa2
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a2, a2, 1 ; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: addi a1, a1, 4 ; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a2, a3, .LBB34_6 ; CHECK-NEXT: bgeu a2, a3, .LBB34_6
; CHECK-NEXT: .LBB34_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB34_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: beqz a5, .LBB35_7 ; CHECK-NEXT: beqz a5, .LBB35_7
; CHECK-NEXT: .LBB35_5: # %for.body.preheader ; CHECK-NEXT: .LBB35_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a4, -1024 ; CHECK-NEXT: addi a2, a4, -1024
; CHECK-NEXT: slli a3, a4, 2 ; CHECK-NEXT: slli a3, a4, 2
; CHECK-NEXT: add a1, a1, a3 ; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB35_6: # %for.body ; CHECK-NEXT: .LBB35_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft0, 0(a0) ; CHECK-NEXT: flw fa1, 0(a0)
; CHECK-NEXT: flw ft1, 0(a1) ; CHECK-NEXT: flw fa2, 0(a1)
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: fmadd.s ft0, fa0, ft0, ft1 ; CHECK-NEXT: fmadd.s fa1, fa0, fa1, fa2
; CHECK-NEXT: fsw ft0, 0(a0) ; CHECK-NEXT: fsw fa1, 0(a0)
; CHECK-NEXT: addi a2, a2, 1 ; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: addi a1, a1, 4 ; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: bgeu a2, a3, .LBB35_6 ; CHECK-NEXT: bgeu a2, a3, .LBB35_6
; CHECK-NEXT: .LBB35_7: # %for.cond.cleanup ; CHECK-NEXT: .LBB35_7: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call i64 @llvm.vscale.i64() %0 = call i64 @llvm.vscale.i64()
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llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>) declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) { define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f16: ; CHECK-LABEL: vreduce_fadd_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>) declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) { define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f16: ; CHECK-LABEL: vreduce_fadd_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>) declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) { define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f16: ; CHECK-LABEL: vreduce_fadd_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: fmv.h.x fa1, zero
; CHECK-NEXT: fneg.h ft0, ft0 ; CHECK-NEXT: fneg.h fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>) declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) { define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f32: ; CHECK-LABEL: vreduce_fadd_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) { define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f32: ; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v) %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) { define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv1f32: ; CHECK-LABEL: vreduce_fwadd_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %v to <vscale x 1 x float> %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) { define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32: ; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32:
Show All 10 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>) declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) { define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f32: ; CHECK-LABEL: vreduce_fadd_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) { define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f32: ; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v) %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) { define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv2f32: ; CHECK-LABEL: vreduce_fwadd_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = fpext <vscale x 2 x half> %v to <vscale x 2 x float> %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) { define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32: ; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32:
Show All 10 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>) declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) { define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f32: ; CHECK-LABEL: vreduce_fadd_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v10, ft0 ; CHECK-NEXT: vfmv.s.f v10, fa1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) { define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f32: ; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v10 ; CHECK-NEXT: vfredosum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v) %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) { define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
; CHECK-LABEL: vreduce_fwadd_nxv4f32: ; CHECK-LABEL: vreduce_fwadd_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x fa1, zero
; CHECK-NEXT: fneg.s ft0, ft0 ; CHECK-NEXT: fneg.s fa1, fa1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vfmv.s.f v9, fa1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfwredusum.vs v8, v8, v9 ; CHECK-NEXT: vfwredusum.vs v8, v8, v9
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = fpext <vscale x 4 x half> %v to <vscale x 4 x float> %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e) %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) { define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32: ; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32:
Show All 10 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>) declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) { define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv1f64: ; RV32-LABEL: vreduce_fadd_nxv1f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v9 ; RV32-NEXT: vfredusum.vs v8, v8, v9
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_nxv1f64: ; RV64-LABEL: vreduce_fadd_nxv1f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v9 ; RV64-NEXT: vfredusum.vs v8, v8, v9
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) { define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f64: ; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v) %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) { define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv1f64: ; RV32-LABEL: vreduce_fwadd_nxv1f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9 ; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_nxv1f64: ; RV64-LABEL: vreduce_fwadd_nxv1f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9 ; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%e = fpext <vscale x 1 x float> %v to <vscale x 1 x double> %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) { define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64: ; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64:
Show All 10 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>) declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) { define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv2f64: ; RV32-LABEL: vreduce_fadd_nxv2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v10, ft0 ; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v10 ; RV32-NEXT: vfredusum.vs v8, v8, v10
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_nxv2f64: ; RV64-LABEL: vreduce_fadd_nxv2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v10, ft0 ; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v10 ; RV64-NEXT: vfredusum.vs v8, v8, v10
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) { define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f64: ; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v10 ; CHECK-NEXT: vfredosum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v) %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) { define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv2f64: ; RV32-LABEL: vreduce_fwadd_nxv2f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v9, ft0 ; RV32-NEXT: vfmv.s.f v9, fa1
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v9 ; RV32-NEXT: vfwredusum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_nxv2f64: ; RV64-LABEL: vreduce_fwadd_nxv2f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v9, ft0 ; RV64-NEXT: vfmv.s.f v9, fa1
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v9 ; RV64-NEXT: vfwredusum.vs v8, v8, v9
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%e = fpext <vscale x 2 x float> %v to <vscale x 2 x double> %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) { define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64: ; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64:
Show All 10 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>) declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) { define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; RV32-LABEL: vreduce_fadd_nxv4f64: ; RV32-LABEL: vreduce_fadd_nxv4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v12, ft0 ; RV32-NEXT: vfmv.s.f v12, fa1
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v12 ; RV32-NEXT: vfredusum.vs v8, v8, v12
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fadd_nxv4f64: ; RV64-LABEL: vreduce_fadd_nxv4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v12, ft0 ; RV64-NEXT: vfmv.s.f v12, fa1
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v12 ; RV64-NEXT: vfredusum.vs v8, v8, v12
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) { define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f64: ; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfredosum.vs v8, v8, v12 ; CHECK-NEXT: vfredosum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v) %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) { define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
; RV32-LABEL: vreduce_fwadd_nxv4f64: ; RV32-LABEL: vreduce_fwadd_nxv4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w fa1, zero
; RV32-NEXT: fneg.d ft0, ft0 ; RV32-NEXT: fneg.d fa1, fa1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfmv.s.f v10, ft0 ; RV32-NEXT: vfmv.s.f v10, fa1
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32-NEXT: vfwredusum.vs v8, v8, v10 ; RV32-NEXT: vfwredusum.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: vfmv.f.s fa1, v8
; RV32-NEXT: fadd.d fa0, fa0, ft0 ; RV32-NEXT: fadd.d fa0, fa0, fa1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_fwadd_nxv4f64: ; RV64-LABEL: vreduce_fwadd_nxv4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x fa1, zero
; RV64-NEXT: fneg.d ft0, ft0 ; RV64-NEXT: fneg.d fa1, fa1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfmv.s.f v10, ft0 ; RV64-NEXT: vfmv.s.f v10, fa1
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64-NEXT: vfwredusum.vs v8, v8, v10 ; RV64-NEXT: vfwredusum.vs v8, v8, v10
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: vfmv.f.s fa1, v8
; RV64-NEXT: fadd.d fa0, fa0, ft0 ; RV64-NEXT: fadd.d fa0, fa0, fa1
; RV64-NEXT: ret ; RV64-NEXT: ret
%e = fpext <vscale x 4 x float> %v to <vscale x 4 x double> %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e) %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) { define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64: ; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64:
▲ Show 20 Lines • Show All 612 Lines • ▼ Show 20 Lines
define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) { define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32: ; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, zero ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa1, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, fa1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v) %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red ret float %red
} }

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v24, v0, a1 ; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: sub a1, a0, a2 ; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: bltu a0, a1, .LBB6_4 ; CHECK-NEXT: bltu a0, a1, .LBB6_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB6_4: ; CHECK-NEXT: .LBB6_4:
; CHECK-NEXT: vsetvli zero, a4, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a4, e16, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
Show All 15 Lines
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v24, v0, a1 ; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m8, tu, mu
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: sub a1, a0, a2 ; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: bltu a0, a1, .LBB7_4 ; CHECK-NEXT: bltu a0, a1, .LBB7_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB7_4: ; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: vsetvli zero, a4, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a4, e16, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-const.ll

Show First 20 Lines • Show All 238 Lines • ▼ Show 20 Lines
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IF-LABEL: select_const_fp: ; RV32IF-LABEL: select_const_fp:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: bnez a0, .LBB4_2 ; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI4_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI4_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: ; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI4_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV32IF-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_fp: ; RV32IBT-LABEL: select_const_fp:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: lui a1, 264192 ; RV32IBT-NEXT: lui a1, 264192
; RV32IBT-NEXT: lui a2, 263168 ; RV32IBT-NEXT: lui a2, 263168
; RV32IBT-NEXT: cmov a0, a0, a2, a1 ; RV32IBT-NEXT: cmov a0, a0, a2, a1
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
; ;
; RV32IFBT-LABEL: select_const_fp: ; RV32IFBT-LABEL: select_const_fp:
; RV32IFBT: # %bb.0: ; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: bnez a0, .LBB4_2 ; RV32IFBT-NEXT: bnez a0, .LBB4_2
; RV32IFBT-NEXT: # %bb.1: ; RV32IFBT-NEXT: # %bb.1:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_0) ; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_0)
; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV32IFBT-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV32IFBT-NEXT: fmv.x.w a0, ft0 ; RV32IFBT-NEXT: fmv.x.w a0, fa0
; RV32IFBT-NEXT: ret ; RV32IFBT-NEXT: ret
; RV32IFBT-NEXT: .LBB4_2: ; RV32IFBT-NEXT: .LBB4_2:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_1) ; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_1)
; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV32IFBT-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
; RV32IFBT-NEXT: fmv.x.w a0, ft0 ; RV32IFBT-NEXT: fmv.x.w a0, fa0
; RV32IFBT-NEXT: ret ; RV32IFBT-NEXT: ret
; ;
; RV64I-LABEL: select_const_fp: ; RV64I-LABEL: select_const_fp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui a0, 263168 ; RV64I-NEXT: lui a0, 263168
; RV64I-NEXT: bnez a1, .LBB4_2 ; RV64I-NEXT: bnez a1, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 264192 ; RV64I-NEXT: lui a0, 264192
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_fp: ; RV64IFD-LABEL: select_const_fp:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bnez a0, .LBB4_2 ; RV64IFD-NEXT: bnez a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV64IFD-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV64IFD-NEXT: fmv.x.w a0, ft0 ; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB4_2: ; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV64IFD-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
; RV64IFD-NEXT: fmv.x.w a0, ft0 ; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV64IBT-LABEL: select_const_fp: ; RV64IBT-LABEL: select_const_fp:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: lui a1, 264192 ; RV64IBT-NEXT: lui a1, 264192
; RV64IBT-NEXT: lui a2, 263168 ; RV64IBT-NEXT: lui a2, 263168
; RV64IBT-NEXT: cmov a0, a0, a2, a1 ; RV64IBT-NEXT: cmov a0, a0, a2, a1
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
; ;
; RV64IFDBT-LABEL: select_const_fp: ; RV64IFDBT-LABEL: select_const_fp:
; RV64IFDBT: # %bb.0: ; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: bnez a0, .LBB4_2 ; RV64IFDBT-NEXT: bnez a0, .LBB4_2
; RV64IFDBT-NEXT: # %bb.1: ; RV64IFDBT-NEXT: # %bb.1:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_0) ; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_0)
; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV64IFDBT-NEXT: flw fa0, %lo(.LCPI4_0)(a0)
; RV64IFDBT-NEXT: fmv.x.w a0, ft0 ; RV64IFDBT-NEXT: fmv.x.w a0, fa0
; RV64IFDBT-NEXT: ret ; RV64IFDBT-NEXT: ret
; RV64IFDBT-NEXT: .LBB4_2: ; RV64IFDBT-NEXT: .LBB4_2:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1) ; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1)
; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV64IFDBT-NEXT: flw fa0, %lo(.LCPI4_1)(a0)
; RV64IFDBT-NEXT: fmv.x.w a0, ft0 ; RV64IFDBT-NEXT: fmv.x.w a0, fa0
; RV64IFDBT-NEXT: ret ; RV64IFDBT-NEXT: ret
%1 = select i1 %a, float 3.0, float 4.0 %1 = select i1 %a, float 3.0, float 4.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
} }
define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind { define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
; RV32I-LABEL: cmovfloat: ; RV32I-LABEL: cmovfloat:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB4_2 ; RV32I-NEXT: bnez a0, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: fmv.w.x ft0, a4 ; RV32I-NEXT: fmv.w.x fa0, a4
; RV32I-NEXT: fmv.w.x ft1, a2 ; RV32I-NEXT: fmv.w.x fa1, a2
; RV32I-NEXT: j .LBB4_3 ; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: fmv.w.x ft0, a3 ; RV32I-NEXT: fmv.w.x fa0, a3
; RV32I-NEXT: fmv.w.x ft1, a1 ; RV32I-NEXT: fmv.w.x fa1, a1
; RV32I-NEXT: .LBB4_3: # %entry ; RV32I-NEXT: .LBB4_3: # %entry
; RV32I-NEXT: fadd.s ft0, ft1, ft0 ; RV32I-NEXT: fadd.s fa0, fa1, fa0
; RV32I-NEXT: fmv.x.w a0, ft0 ; RV32I-NEXT: fmv.x.w a0, fa0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovfloat: ; RV32IBT-LABEL: cmovfloat:
; RV32IBT: # %bb.0: # %entry ; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a0, a0, 1 ; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: bnez a0, .LBB4_2 ; RV32IBT-NEXT: bnez a0, .LBB4_2
; RV32IBT-NEXT: # %bb.1: # %entry ; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: fmv.w.x ft0, a4 ; RV32IBT-NEXT: fmv.w.x fa0, a4
; RV32IBT-NEXT: fmv.w.x ft1, a2 ; RV32IBT-NEXT: fmv.w.x fa1, a2
; RV32IBT-NEXT: j .LBB4_3 ; RV32IBT-NEXT: j .LBB4_3
; RV32IBT-NEXT: .LBB4_2: ; RV32IBT-NEXT: .LBB4_2:
; RV32IBT-NEXT: fmv.w.x ft0, a3 ; RV32IBT-NEXT: fmv.w.x fa0, a3
; RV32IBT-NEXT: fmv.w.x ft1, a1 ; RV32IBT-NEXT: fmv.w.x fa1, a1
; RV32IBT-NEXT: .LBB4_3: # %entry ; RV32IBT-NEXT: .LBB4_3: # %entry
; RV32IBT-NEXT: fadd.s ft0, ft1, ft0 ; RV32IBT-NEXT: fadd.s fa0, fa1, fa0
; RV32IBT-NEXT: fmv.x.w a0, ft0 ; RV32IBT-NEXT: fmv.x.w a0, fa0
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
; ;
; RV64I-LABEL: cmovfloat: ; RV64I-LABEL: cmovfloat:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB4_2 ; RV64I-NEXT: bnez a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: fmv.w.x ft0, a4 ; RV64I-NEXT: fmv.w.x fa0, a4
; RV64I-NEXT: fmv.w.x ft1, a2 ; RV64I-NEXT: fmv.w.x fa1, a2
; RV64I-NEXT: j .LBB4_3 ; RV64I-NEXT: j .LBB4_3
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: fmv.w.x ft0, a3 ; RV64I-NEXT: fmv.w.x fa0, a3
; RV64I-NEXT: fmv.w.x ft1, a1 ; RV64I-NEXT: fmv.w.x fa1, a1
; RV64I-NEXT: .LBB4_3: # %entry ; RV64I-NEXT: .LBB4_3: # %entry
; RV64I-NEXT: fadd.s ft0, ft1, ft0 ; RV64I-NEXT: fadd.s fa0, fa1, fa0
; RV64I-NEXT: fmv.x.w a0, ft0 ; RV64I-NEXT: fmv.x.w a0, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IBT-LABEL: cmovfloat: ; RV64IBT-LABEL: cmovfloat:
; RV64IBT: # %bb.0: # %entry ; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a0, a0, 1 ; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB4_2 ; RV64IBT-NEXT: bnez a0, .LBB4_2
; RV64IBT-NEXT: # %bb.1: # %entry ; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: fmv.w.x ft0, a4 ; RV64IBT-NEXT: fmv.w.x fa0, a4
; RV64IBT-NEXT: fmv.w.x ft1, a2 ; RV64IBT-NEXT: fmv.w.x fa1, a2
; RV64IBT-NEXT: j .LBB4_3 ; RV64IBT-NEXT: j .LBB4_3
; RV64IBT-NEXT: .LBB4_2: ; RV64IBT-NEXT: .LBB4_2:
; RV64IBT-NEXT: fmv.w.x ft0, a3 ; RV64IBT-NEXT: fmv.w.x fa0, a3
; RV64IBT-NEXT: fmv.w.x ft1, a1 ; RV64IBT-NEXT: fmv.w.x fa1, a1
; RV64IBT-NEXT: .LBB4_3: # %entry ; RV64IBT-NEXT: .LBB4_3: # %entry
; RV64IBT-NEXT: fadd.s ft0, ft1, ft0 ; RV64IBT-NEXT: fadd.s fa0, fa1, fa0
; RV64IBT-NEXT: fmv.x.w a0, ft0 ; RV64IBT-NEXT: fmv.x.w a0, fa0
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
entry: entry:
%cond1 = select i1 %a, float %b, float %c %cond1 = select i1 %a, float %b, float %c
%cond2 = select i1 %a, float %d, float %e %cond2 = select i1 %a, float %d, float %e
%ret = fadd float %cond1, %cond2 %ret = fadd float %cond1, %cond2
ret float %ret ret float %ret
} }
define double @cmovdouble(i1 %a, double %b, double %c) nounwind { define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
; RV32I-LABEL: cmovdouble: ; RV32I-LABEL: cmovdouble:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw a3, 8(sp) ; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: sw a4, 12(sp) ; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: fld ft0, 8(sp) ; RV32I-NEXT: fld fa0, 8(sp)
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: beqz a0, .LBB5_2 ; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: fld ft0, 8(sp) ; RV32I-NEXT: fld fa0, 8(sp)
; RV32I-NEXT: .LBB5_2: # %entry ; RV32I-NEXT: .LBB5_2: # %entry
; RV32I-NEXT: fsd ft0, 8(sp) ; RV32I-NEXT: fsd fa0, 8(sp)
; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw a1, 12(sp) ; RV32I-NEXT: lw a1, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovdouble: ; RV32IBT-LABEL: cmovdouble:
; RV32IBT: # %bb.0: # %entry ; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi sp, sp, -16 ; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw a3, 8(sp) ; RV32IBT-NEXT: sw a3, 8(sp)
; RV32IBT-NEXT: sw a4, 12(sp) ; RV32IBT-NEXT: sw a4, 12(sp)
; RV32IBT-NEXT: fld ft0, 8(sp) ; RV32IBT-NEXT: fld fa0, 8(sp)
; RV32IBT-NEXT: sw a1, 8(sp) ; RV32IBT-NEXT: sw a1, 8(sp)
; RV32IBT-NEXT: andi a0, a0, 1 ; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: sw a2, 12(sp) ; RV32IBT-NEXT: sw a2, 12(sp)
; RV32IBT-NEXT: beqz a0, .LBB5_2 ; RV32IBT-NEXT: beqz a0, .LBB5_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: fld ft0, 8(sp) ; RV32IBT-NEXT: fld fa0, 8(sp)
; RV32IBT-NEXT: .LBB5_2: # %entry ; RV32IBT-NEXT: .LBB5_2: # %entry
; RV32IBT-NEXT: fsd ft0, 8(sp) ; RV32IBT-NEXT: fsd fa0, 8(sp)
; RV32IBT-NEXT: lw a0, 8(sp) ; RV32IBT-NEXT: lw a0, 8(sp)
; RV32IBT-NEXT: lw a1, 12(sp) ; RV32IBT-NEXT: lw a1, 12(sp)
; RV32IBT-NEXT: addi sp, sp, 16 ; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
; ;
; RV64I-LABEL: cmovdouble: ; RV64I-LABEL: cmovdouble:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB5_2 ; RV64I-NEXT: bnez a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: fmv.d.x ft0, a2 ; RV64I-NEXT: fmv.d.x fa0, a2
; RV64I-NEXT: fmv.x.d a0, ft0 ; RV64I-NEXT: fmv.x.d a0, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: fmv.d.x ft0, a1 ; RV64I-NEXT: fmv.d.x fa0, a1
; RV64I-NEXT: fmv.x.d a0, ft0 ; RV64I-NEXT: fmv.x.d a0, fa0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IBT-LABEL: cmovdouble: ; RV64IBT-LABEL: cmovdouble:
; RV64IBT: # %bb.0: # %entry ; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a0, a0, 1 ; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB5_2 ; RV64IBT-NEXT: bnez a0, .LBB5_2
; RV64IBT-NEXT: # %bb.1: # %entry ; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: fmv.d.x ft0, a2 ; RV64IBT-NEXT: fmv.d.x fa0, a2
; RV64IBT-NEXT: fmv.x.d a0, ft0 ; RV64IBT-NEXT: fmv.x.d a0, fa0
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
; RV64IBT-NEXT: .LBB5_2: ; RV64IBT-NEXT: .LBB5_2:
; RV64IBT-NEXT: fmv.d.x ft0, a1 ; RV64IBT-NEXT: fmv.d.x fa0, a1
; RV64IBT-NEXT: fmv.x.d a0, ft0 ; RV64IBT-NEXT: fmv.x.d a0, fa0
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
entry: entry:
%cond = select i1 %a, double %b, double %c %cond = select i1 %a, double %b, double %c
ret double %cond ret double %cond
} }
; Check that selects with dependencies on previous ones aren't incorrectly ; Check that selects with dependencies on previous ones aren't incorrectly
; optimized. ; optimized.
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

Show All 10 Lines
declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float>, float, i64); declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float>, float, i64);
declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double>, double, i64); declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double>, double, i64);
define <vscale x 1 x half> @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: fsh ft0, 14(sp) # 2-byte Folded Spill ; CHECK-NEXT: fsh fa0, 14(sp) # 2-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: flh ft0, 14(sp) # 2-byte Folded Reload ; CHECK-NEXT: flh fa0, 14(sp) # 2-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0) %a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(<vscale x 1 x half> undef, half %a, i64 %1) %b = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(<vscale x 1 x half> undef, half %a, i64 %1)
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
define <vscale x 1 x float> @intrinsic_vfmv.f.s_s_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind { define <vscale x 1 x float> @intrinsic_vfmv.f.s_s_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw fa0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw fa0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0) %a = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float> undef, float %a, i64 %1) %b = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float> undef, float %a, i64 %1)
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
define <vscale x 1 x double> @intrinsic_vfmv.f.s_s_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind { define <vscale x 1 x double> @intrinsic_vfmv.f.s_s_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: fsd fa0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0) %a = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double> undef, double %a, i64 %1) %b = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double> undef, double %a, i64 %1)
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }

llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll

; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \ ; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \
; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s ; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s
; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension ; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension
define float @foo(i32 %a) nounwind #0 { define float @foo(i32 %a) nounwind #0 {
; RV32IF-ILP32: fcvt.s.w ft0, a0 ; RV32IF-ILP32: fcvt.s.w fa0, a0
; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0 ; RV32IF-ILP32-NEXT: fmv.x.w a0, fa0
; RV32IF-ILP32F: fcvt.s.w fa0, a0 ; RV32IF-ILP32F: fcvt.s.w fa0, a0
; RV32IF-ILP32F-NEXT: ret ; RV32IF-ILP32F-NEXT: ret
%conv = sitofp i32 %a to float %conv = sitofp i32 %a to float
ret float %conv ret float %conv
} }
attributes #0 = { "target-features"="+f"} attributes #0 = { "target-features"="+f"}

llvm/test/CodeGen/RISCV/vararg.ll

Show First 20 Lines • Show All 683 Lines • ▼ Show 20 Lines
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld fa0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 0(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd fa0, 0(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va2_va_arg: ; LP64-LP64F-LP64D-FPELIM-LABEL: va2_va_arg:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld ft0, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fld fa0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd ft0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: fsd fa0, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
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llvm/test/CodeGen/RISCV/zfh-imm.ll

Show All 28 Lines
; RV64IDZFH-NEXT: fmv.h.x fa0, zero ; RV64IDZFH-NEXT: fmv.h.x fa0, zero
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
ret half 0.0 ret half 0.0
} }
define half @f16_negative_zero(half *%pf) nounwind { define half @f16_negative_zero(half *%pf) nounwind {
; RV32IZFH-LABEL: f16_negative_zero: ; RV32IZFH-LABEL: f16_negative_zero:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x fa0, zero
; RV32IZFH-NEXT: fneg.h fa0, ft0 ; RV32IZFH-NEXT: fneg.h fa0, fa0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: f16_negative_zero: ; RV32IDZFH-LABEL: f16_negative_zero:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fmv.h.x ft0, zero ; RV32IDZFH-NEXT: fmv.h.x fa0, zero
; RV32IDZFH-NEXT: fneg.h fa0, ft0 ; RV32IDZFH-NEXT: fneg.h fa0, fa0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: f16_negative_zero: ; RV64IZFH-LABEL: f16_negative_zero:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero ; RV64IZFH-NEXT: fmv.h.x fa0, zero
; RV64IZFH-NEXT: fneg.h fa0, ft0 ; RV64IZFH-NEXT: fneg.h fa0, fa0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: f16_negative_zero: ; RV64IDZFH-LABEL: f16_negative_zero:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmv.h.x ft0, zero ; RV64IDZFH-NEXT: fmv.h.x fa0, zero
; RV64IDZFH-NEXT: fneg.h fa0, ft0 ; RV64IDZFH-NEXT: fneg.h fa0, fa0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
ret half -0.0 ret half -0.0
} }