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[RISCV] Simplify the definitions of interrupt CSRs
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Authored by wangpc on Jul 10 2023, 5:31 AM.

Details

Summary

For CSR_Interrupt, we can generate the register list via a single
sequence.

For CSR_XLEN_F32_Interrupt and CSR_XLEN_F64_Interrupt, I don't
see the reason why we need to keep the order the same as how we used
to allocate registers (and we have changed the order in D146488), so
I fold them into one sequence.

There are some *.ll changes because of the order change.

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Event Timeline

wangpc created this revision.Jul 10 2023, 5:31 AM
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wangpc requested review of this revision.Jul 10 2023, 5:31 AM
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This revision is now accepted and ready to land.Jul 10 2023, 1:44 PM
This revision was landed with ongoing or failed builds.Jul 10 2023, 8:21 PM
This revision was automatically updated to reflect the committed changes.