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Differential D144535

[RISCV] Enable machine copy propagation for copy-like instructions
ClosedPublic

Authored by • pcwang-thead on Feb 21 2023, 10:18 PM.

Details

Reviewers
asb
reames
craig.topper
kito-cheng
Commits
rG5fdab3c81bb2: [RISCV] Enable machine copy propagation for copy-like instructions
Summary

Like what has been done in AArch64 (D125335).

We enable this under -O2 to show the codegen diffs here but we
may only do this under -O3 like AArch64.

There are two cases that we may produce these eliminable copies:

  1. ISel of FrameIndex. Like rvv/fixed-vectors-calling-conv.ll.
  2. Tail duplication. Like select-optimize-multiple.ll.

Diff Detail

Event Timeline

• pcwang-thead created this revision.Feb 21 2023, 10:18 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2023, 10:18 PM
Herald added subscribers: luke, VincentWu, armkevincheng and 30 others. · View Herald Transcript
• pcwang-thead requested review of this revision.Feb 21 2023, 10:18 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2023, 10:18 PM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B215162: Diff 499368.Feb 21 2023, 11:10 PM
craig.topper added inline comments.Feb 22 2023, 10:13 AM
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
355

Can this be before the two Expand passes? Especially the one that says "last possible moment"?

• pcwang-thead updated this revision to Diff 499715.Feb 22 2023, 8:25 PM

Insert MachineCopyPropagation pass before RISCVExpandAtomicPseudo.

• pcwang-thead marked an inline comment as done.Feb 22 2023, 8:28 PM
• pcwang-thead added inline comments.
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
355

How about between the two Expand passes? we may produce MVs when expanding PseudoCCMOVGPR.

craig.topper added inline comments.Feb 22 2023, 8:33 PM
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
355

Would optimizing them break the macrofusion that PseudoCCMOVGPR represents?

Harbormaster completed remote builds in B215420: Diff 499715.Feb 22 2023, 10:00 PM
• pcwang-thead marked 2 inline comments as done.Feb 22 2023, 10:27 PM
• pcwang-thead added inline comments.
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
355

After thinking, I think MVs produced by PseudoCCMOVGPR won't be eliminatable.

dst = falsev
branch
  |   \
  |   TrueBB: 
  |     dst = truev
  |   /
MergeBB:
  usage of dst

For these kinds of CFGs, truev could be propagated only if we do tail duplication and CFG becomes like below, but we won't run tail duplication again after expanding.

dst = falsev
branch
  |         \
MergeBB   TrueBB: 
  |         dst = truev
  |         duplicated MergeBB
  |         /
Successor of MergeBB

So I think it has no impact on the macrofusion.

Another reason why we inserted it after expanding pseudos is because some internal pseudos in our downstream will produce MVs.

• pcwang-thead marked an inline comment as done.Mar 2 2023, 6:33 PM

Gentle ping.

craig.topper added a comment.Mar 2 2023, 10:08 PM

Is this expensive compile time wise? Why did AArch64 make it -O3 only?

• pcwang-thead added a comment.Mar 2 2023, 10:25 PM
In D144535#4166316, @craig.topper wrote:

Is this expensive compile time wise? Why did AArch64 make it -O3 only?

I haven't evaluated the impact on compile time, there is about 0.16% increase from AArch64's result. And I think it won't be too expensive since there are already two runs of Machine Copy Propagation Pass in the pipeline.
The reason why AArch64 made it -O3 only is because the gains is not very large compared with the increase of compile time, may we be more aggressive since the gains seem to be larger for RISCV?

craig.topper accepted this revision.Mar 3 2023, 10:28 AM

LGTM

This revision is now accepted and ready to land.Mar 3 2023, 10:28 AM
This revision was landed with ongoing or failed builds.Mar 7 2023, 1:54 AM
Closed by commit rG5fdab3c81bb2: [RISCV] Enable machine copy propagation for copy-like instructions (authored by • pcwang-thead). · Explain Why
This revision was automatically updated to reflect the committed changes.
• pcwang-thead added a commit: rG5fdab3c81bb2: [RISCV] Enable machine copy propagation for copy-like instructions.
asb mentioned this in D146037: [RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation.Mar 14 2023, 5:41 AM
asb mentioned this in rG084e4138930d: [RISCV] Fix regression due to interaction of MachineOutliner and….Mar 14 2023, 10:56 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
11 lines
test/
CodeGen/
RISCV/
1 line
64 lines
8 lines
12 lines
rvv/
12 lines
2 lines
2 lines
14 lines
8 lines
2 lines
2 lines
Transforms/
LoopStrengthReduce/
RISCV/
3 lines

Diff 502955

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
static cl::opt<int> RVVVectorBitsMinOpt( static cl::opt<int> RVVVectorBitsMinOpt(
"riscv-v-vector-bits-min", "riscv-v-vector-bits-min",
cl::desc("Assume V extension vector registers are at least this big, " cl::desc("Assume V extension vector registers are at least this big, "
"with zero meaning no minimum size is assumed. A value of -1 " "with zero meaning no minimum size is assumed. A value of -1 "
"means use Zvl*b extension. This is primarily used to enable " "means use Zvl*b extension. This is primarily used to enable "
"autovectorization with fixed width vectors."), "autovectorization with fixed width vectors."),
cl::init(-1), cl::Hidden); cl::init(-1), cl::Hidden);
static cl::opt<bool> EnableRISCVCopyPropagation(
"riscv-enable-copy-propagation",
cl::desc("Enable the copy propagation with RISCV copy instr"),
cl::init(true), cl::Hidden);
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
auto *PR = PassRegistry::getPassRegistry(); auto *PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR); initializeGlobalISel(*PR);
initializeRISCVMakeCompressibleOptPass(*PR); initializeRISCVMakeCompressibleOptPass(*PR);
initializeRISCVGatherScatterLoweringPass(*PR); initializeRISCVGatherScatterLoweringPass(*PR);
initializeRISCVCodeGenPreparePass(*PR); initializeRISCVCodeGenPreparePass(*PR);
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
void RISCVPassConfig::addPreEmitPass() { void RISCVPassConfig::addPreEmitPass() {
addPass(&BranchRelaxationPassID); addPass(&BranchRelaxationPassID);
addPass(createRISCVMakeCompressibleOptPass()); addPass(createRISCVMakeCompressibleOptPass());
} }
void RISCVPassConfig::addPreEmitPass2() { void RISCVPassConfig::addPreEmitPass2() {
addPass(createRISCVExpandPseudoPass()); addPass(createRISCVExpandPseudoPass());
// Do the copy propagation after expanding pseudos because we may produce some
// MVs when expanding.
if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
addPass(createMachineCopyPropagationPass(true));
// Schedule the expansion of AMOs at the last possible moment, avoiding the // Schedule the expansion of AMOs at the last possible moment, avoiding the
// possibility for other passes to break the requirements for forward // possibility for other passes to break the requirements for forward
// progress in the LR/SC block. // progress in the LR/SC block.
addPass(createRISCVExpandAtomicPseudoPass()); addPass(createRISCVExpandAtomicPseudoPass());
} }
craig.topperUnsubmitted
Done
ReplyInline Actions

Can this be before the two Expand passes? Especially the one that says "last possible moment"?

craig.topper: Can this be before the two Expand passes? Especially the one that says "last possible moment"?
pcwang-theadAuthorUnsubmitted
Done
ReplyInline Actions

How about between the two Expand passes? we may produce MVs when expanding PseudoCCMOVGPR.

pcwang-thead: How about between the two Expand passes? we may produce MVs when expanding `PseudoCCMOVGPR`.
craig.topperUnsubmitted
Done
ReplyInline Actions

Would optimizing them break the macrofusion that PseudoCCMOVGPR represents?

craig.topper: Would optimizing them break the macrofusion that `PseudoCCMOVGPR` represents?
pcwang-theadAuthorUnsubmitted
Done
ReplyInline Actions

After thinking, I think MVs produced by PseudoCCMOVGPR won't be eliminatable.

dst = falsev
branch
  |   \
  |   TrueBB: 
  |     dst = truev
  |   /
MergeBB:
  usage of dst

For these kinds of CFGs, truev could be propagated only if we do tail duplication and CFG becomes like below, but we won't run tail duplication again after expanding.

dst = falsev
branch
  |         \
MergeBB   TrueBB: 
  |         dst = truev
  |         duplicated MergeBB
  |         /
Successor of MergeBB

So I think it has no impact on the macrofusion.

Another reason why we inserted it after expanding pseudos is because some internal pseudos in our downstream will produce MVs.

pcwang-thead: After thinking, I think MVs produced by `PseudoCCMOVGPR` won't be eliminatable. ``` dst =…
void RISCVPassConfig::addMachineSSAOptimization() { void RISCVPassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization(); TargetPassConfig::addMachineSSAOptimization();
if (EnableMachineCombiner) if (EnableMachineCombiner)
addPass(&MachineCombinerID); addPass(&MachineCombinerID);
if (TM->getTargetTriple().getArch() == Triple::riscv64) { if (TM->getTargetTriple().getArch() == Triple::riscv64) {
addPass(createRISCVSExtWRemovalPass()); addPass(createRISCVSExtWRemovalPass());
addPass(createRISCVStripWSuffixPass()); addPass(createRISCVStripWSuffixPass());
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/O3-pipeline.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Live DEBUG_VALUE analysis ; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Machine Sanitizer Binary Metadata ; CHECK-NEXT: Machine Sanitizer Binary Metadata
; CHECK-NEXT: Machine Outliner ; CHECK-NEXT: Machine Outliner
; CHECK-NEXT: FunctionPass Manager ; CHECK-NEXT: FunctionPass Manager
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis ; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISCV pseudo instruction expansion pass ; CHECK-NEXT: RISCV pseudo instruction expansion pass
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass ; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: RISCV Assembly Printer ; CHECK-NEXT: RISCV Assembly Printer
; CHECK-NEXT: Free MachineFunction ; CHECK-NEXT: Free MachineFunction

llvm/test/CodeGen/RISCV/copyprop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O3 -mtriple=riscv64 -riscv-enable-copy-propagation=false | FileCheck %s --check-prefix=NOPROP
; RUN: llc < %s -O3 -mtriple=riscv64 -riscv-enable-copy-propagation=true | FileCheck %s --check-prefix=PROP
define void @copyprop_after_mbp(i32 %v, i32* %a, i32* %b, i32* %c, i32* %d) {
; NOPROP-LABEL: copyprop_after_mbp:
; NOPROP: # %bb.0:
; NOPROP-NEXT: sext.w a0, a0
; NOPROP-NEXT: li a5, 10
; NOPROP-NEXT: bne a0, a5, .LBB0_2
; NOPROP-NEXT: # %bb.1: # %bb.0
; NOPROP-NEXT: li a0, 15
; NOPROP-NEXT: sw a0, 0(a2)
; NOPROP-NEXT: li a0, 1
; NOPROP-NEXT: sw a0, 0(a1)
; NOPROP-NEXT: li a0, 12
; NOPROP-NEXT: sw a0, 0(a4)
; NOPROP-NEXT: ret
; NOPROP-NEXT: .LBB0_2: # %bb.1
; NOPROP-NEXT: li a0, 0
; NOPROP-NEXT: li a2, 25
; NOPROP-NEXT: sw a2, 0(a3)
; NOPROP-NEXT: sw a0, 0(a1)
; NOPROP-NEXT: li a0, 12
; NOPROP-NEXT: sw a0, 0(a4)
; NOPROP-NEXT: ret
;
; PROP-LABEL: copyprop_after_mbp:
; PROP: # %bb.0:
; PROP-NEXT: sext.w a0, a0
; PROP-NEXT: li a5, 10
; PROP-NEXT: bne a0, a5, .LBB0_2
; PROP-NEXT: # %bb.1: # %bb.0
; PROP-NEXT: li a0, 15
; PROP-NEXT: sw a0, 0(a2)
; PROP-NEXT: li a0, 1
; PROP-NEXT: sw a0, 0(a1)
; PROP-NEXT: li a0, 12
; PROP-NEXT: sw a0, 0(a4)
; PROP-NEXT: ret
; PROP-NEXT: .LBB0_2: # %bb.1
; PROP-NEXT: li a2, 25
; PROP-NEXT: sw a2, 0(a3)
; PROP-NEXT: sw zero, 0(a1)
; PROP-NEXT: li a0, 12
; PROP-NEXT: sw a0, 0(a4)
; PROP-NEXT: ret
%1 = icmp eq i32 %v, 10
br i1 %1, label %bb.0, label %bb.1
bb.0:
store i32 15, i32* %b, align 4
br label %bb.2
bb.1:
store i32 25, i32* %c, align 4
br label %bb.2
bb.2:
%2 = phi i32 [ 1, %bb.0 ], [ 0, %bb.1 ]
store i32 %2, i32* %a, align 4
store i32 12, i32* %d, align 4
ret void
}

llvm/test/CodeGen/RISCV/fpclamptosat.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: addiw a2, a1, -1 ; RV64IFD-NEXT: addiw a2, a1, -1
; RV64IFD-NEXT: bge a0, a2, .LBB0_3 ; RV64IFD-NEXT: bge a0, a2, .LBB0_3
; RV64IFD-NEXT: # %bb.1: # %entry ; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: bge a1, a0, .LBB0_4 ; RV64IFD-NEXT: bge a1, a0, .LBB0_4
; RV64IFD-NEXT: .LBB0_2: # %entry ; RV64IFD-NEXT: .LBB0_2: # %entry
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB0_3: # %entry ; RV64IFD-NEXT: .LBB0_3: # %entry
; RV64IFD-NEXT: mv a0, a2 ; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: blt a1, a0, .LBB0_2 ; RV64IFD-NEXT: blt a1, a2, .LBB0_2
; RV64IFD-NEXT: .LBB0_4: # %entry ; RV64IFD-NEXT: .LBB0_4: # %entry
; RV64IFD-NEXT: lui a0, 524288 ; RV64IFD-NEXT: lui a0, 524288
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
entry: entry:
%conv = fptosi double %x to i64 %conv = fptosi double %x to i64
%0 = icmp slt i64 %conv, 2147483647 %0 = icmp slt i64 %conv, 2147483647
%spec.store.select = select i1 %0, i64 %conv, i64 2147483647 %spec.store.select = select i1 %0, i64 %conv, i64 2147483647
%1 = icmp sgt i64 %spec.store.select, -2147483648 %1 = icmp sgt i64 %spec.store.select, -2147483648
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; RV64-NEXT: addiw a2, a1, -1 ; RV64-NEXT: addiw a2, a1, -1
; RV64-NEXT: bge a0, a2, .LBB3_3 ; RV64-NEXT: bge a0, a2, .LBB3_3
; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: bge a1, a0, .LBB3_4 ; RV64-NEXT: bge a1, a0, .LBB3_4
; RV64-NEXT: .LBB3_2: # %entry ; RV64-NEXT: .LBB3_2: # %entry
; RV64-NEXT: ret ; RV64-NEXT: ret
; RV64-NEXT: .LBB3_3: # %entry ; RV64-NEXT: .LBB3_3: # %entry
; RV64-NEXT: mv a0, a2 ; RV64-NEXT: mv a0, a2
; RV64-NEXT: blt a1, a0, .LBB3_2 ; RV64-NEXT: blt a1, a2, .LBB3_2
; RV64-NEXT: .LBB3_4: # %entry ; RV64-NEXT: .LBB3_4: # %entry
; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: lui a0, 524288
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%conv = fptosi float %x to i64 %conv = fptosi float %x to i64
%0 = icmp slt i64 %conv, 2147483647 %0 = icmp slt i64 %conv, 2147483647
%spec.store.select = select i1 %0, i64 %conv, i64 2147483647 %spec.store.select = select i1 %0, i64 %conv, i64 2147483647
%1 = icmp sgt i64 %spec.store.select, -2147483648 %1 = icmp sgt i64 %spec.store.select, -2147483648
▲ Show 20 Lines • Show All 1,753 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: addiw a2, a1, -1 ; RV64IFD-NEXT: addiw a2, a1, -1
; RV64IFD-NEXT: bge a0, a2, .LBB27_3 ; RV64IFD-NEXT: bge a0, a2, .LBB27_3
; RV64IFD-NEXT: # %bb.1: # %entry ; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: bge a1, a0, .LBB27_4 ; RV64IFD-NEXT: bge a1, a0, .LBB27_4
; RV64IFD-NEXT: .LBB27_2: # %entry ; RV64IFD-NEXT: .LBB27_2: # %entry
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB27_3: # %entry ; RV64IFD-NEXT: .LBB27_3: # %entry
; RV64IFD-NEXT: mv a0, a2 ; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: blt a1, a0, .LBB27_2 ; RV64IFD-NEXT: blt a1, a2, .LBB27_2
; RV64IFD-NEXT: .LBB27_4: # %entry ; RV64IFD-NEXT: .LBB27_4: # %entry
; RV64IFD-NEXT: lui a0, 524288 ; RV64IFD-NEXT: lui a0, 524288
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
entry: entry:
%conv = fptosi double %x to i64 %conv = fptosi double %x to i64
%spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647) %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)
%spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648) %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)
%conv6 = trunc i64 %spec.store.select7 to i32 %conv6 = trunc i64 %spec.store.select7 to i32
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; RV64-NEXT: addiw a2, a1, -1 ; RV64-NEXT: addiw a2, a1, -1
; RV64-NEXT: bge a0, a2, .LBB30_3 ; RV64-NEXT: bge a0, a2, .LBB30_3
; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: bge a1, a0, .LBB30_4 ; RV64-NEXT: bge a1, a0, .LBB30_4
; RV64-NEXT: .LBB30_2: # %entry ; RV64-NEXT: .LBB30_2: # %entry
; RV64-NEXT: ret ; RV64-NEXT: ret
; RV64-NEXT: .LBB30_3: # %entry ; RV64-NEXT: .LBB30_3: # %entry
; RV64-NEXT: mv a0, a2 ; RV64-NEXT: mv a0, a2
; RV64-NEXT: blt a1, a0, .LBB30_2 ; RV64-NEXT: blt a1, a2, .LBB30_2
; RV64-NEXT: .LBB30_4: # %entry ; RV64-NEXT: .LBB30_4: # %entry
; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: lui a0, 524288
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%conv = fptosi float %x to i64 %conv = fptosi float %x to i64
%spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647) %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)
%spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648) %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)
%conv6 = trunc i64 %spec.store.select7 to i32 %conv6 = trunc i64 %spec.store.select7 to i32
▲ Show 20 Lines • Show All 1,838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 21 Lines
; CHECK-NOV-NEXT: bge a2, a1, .LBB0_8 ; CHECK-NOV-NEXT: bge a2, a1, .LBB0_8
; CHECK-NOV-NEXT: .LBB0_4: # %entry ; CHECK-NOV-NEXT: .LBB0_4: # %entry
; CHECK-NOV-NEXT: ret ; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB0_5: # %entry ; CHECK-NOV-NEXT: .LBB0_5: # %entry
; CHECK-NOV-NEXT: mv a1, a3 ; CHECK-NOV-NEXT: mv a1, a3
; CHECK-NOV-NEXT: blt a0, a3, .LBB0_2 ; CHECK-NOV-NEXT: blt a0, a3, .LBB0_2
; CHECK-NOV-NEXT: .LBB0_6: # %entry ; CHECK-NOV-NEXT: .LBB0_6: # %entry
; CHECK-NOV-NEXT: mv a0, a3 ; CHECK-NOV-NEXT: mv a0, a3
; CHECK-NOV-NEXT: blt a2, a0, .LBB0_3 ; CHECK-NOV-NEXT: blt a2, a3, .LBB0_3
; CHECK-NOV-NEXT: .LBB0_7: # %entry ; CHECK-NOV-NEXT: .LBB0_7: # %entry
; CHECK-NOV-NEXT: lui a0, 524288 ; CHECK-NOV-NEXT: lui a0, 524288
; CHECK-NOV-NEXT: blt a2, a1, .LBB0_4 ; CHECK-NOV-NEXT: blt a2, a1, .LBB0_4
; CHECK-NOV-NEXT: .LBB0_8: # %entry ; CHECK-NOV-NEXT: .LBB0_8: # %entry
; CHECK-NOV-NEXT: lui a1, 524288 ; CHECK-NOV-NEXT: lui a1, 524288
; CHECK-NOV-NEXT: ret ; CHECK-NOV-NEXT: ret
; ;
; CHECK-V-LABEL: stest_f64i32: ; CHECK-V-LABEL: stest_f64i32:
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
; CHECK-NOV-NEXT: mv a2, a6 ; CHECK-NOV-NEXT: mv a2, a6
; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz ; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz
; CHECK-NOV-NEXT: blt a4, a6, .LBB3_3 ; CHECK-NOV-NEXT: blt a4, a6, .LBB3_3
; CHECK-NOV-NEXT: .LBB3_12: # %entry ; CHECK-NOV-NEXT: .LBB3_12: # %entry
; CHECK-NOV-NEXT: mv a4, a6 ; CHECK-NOV-NEXT: mv a4, a6
; CHECK-NOV-NEXT: blt a5, a6, .LBB3_4 ; CHECK-NOV-NEXT: blt a5, a6, .LBB3_4
; CHECK-NOV-NEXT: .LBB3_13: # %entry ; CHECK-NOV-NEXT: .LBB3_13: # %entry
; CHECK-NOV-NEXT: mv a5, a6 ; CHECK-NOV-NEXT: mv a5, a6
; CHECK-NOV-NEXT: blt a3, a5, .LBB3_5 ; CHECK-NOV-NEXT: blt a3, a6, .LBB3_5
; CHECK-NOV-NEXT: .LBB3_14: # %entry ; CHECK-NOV-NEXT: .LBB3_14: # %entry
; CHECK-NOV-NEXT: lui a5, 524288 ; CHECK-NOV-NEXT: lui a5, 524288
; CHECK-NOV-NEXT: blt a3, a4, .LBB3_6 ; CHECK-NOV-NEXT: blt a3, a4, .LBB3_6
; CHECK-NOV-NEXT: .LBB3_15: # %entry ; CHECK-NOV-NEXT: .LBB3_15: # %entry
; CHECK-NOV-NEXT: lui a4, 524288 ; CHECK-NOV-NEXT: lui a4, 524288
; CHECK-NOV-NEXT: blt a3, a2, .LBB3_7 ; CHECK-NOV-NEXT: blt a3, a2, .LBB3_7
; CHECK-NOV-NEXT: .LBB3_16: # %entry ; CHECK-NOV-NEXT: .LBB3_16: # %entry
; CHECK-NOV-NEXT: lui a2, 524288 ; CHECK-NOV-NEXT: lui a2, 524288
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; CHECK-NOV-NEXT: mv s2, a4 ; CHECK-NOV-NEXT: mv s2, a4
; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz ; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz
; CHECK-NOV-NEXT: blt a2, a4, .LBB6_3 ; CHECK-NOV-NEXT: blt a2, a4, .LBB6_3
; CHECK-NOV-NEXT: .LBB6_12: # %entry ; CHECK-NOV-NEXT: .LBB6_12: # %entry
; CHECK-NOV-NEXT: mv a2, a4 ; CHECK-NOV-NEXT: mv a2, a4
; CHECK-NOV-NEXT: blt a3, a4, .LBB6_4 ; CHECK-NOV-NEXT: blt a3, a4, .LBB6_4
; CHECK-NOV-NEXT: .LBB6_13: # %entry ; CHECK-NOV-NEXT: .LBB6_13: # %entry
; CHECK-NOV-NEXT: mv a3, a4 ; CHECK-NOV-NEXT: mv a3, a4
; CHECK-NOV-NEXT: blt a1, a3, .LBB6_5 ; CHECK-NOV-NEXT: blt a1, a4, .LBB6_5
; CHECK-NOV-NEXT: .LBB6_14: # %entry ; CHECK-NOV-NEXT: .LBB6_14: # %entry
; CHECK-NOV-NEXT: lui a3, 524288 ; CHECK-NOV-NEXT: lui a3, 524288
; CHECK-NOV-NEXT: blt a1, a2, .LBB6_6 ; CHECK-NOV-NEXT: blt a1, a2, .LBB6_6
; CHECK-NOV-NEXT: .LBB6_15: # %entry ; CHECK-NOV-NEXT: .LBB6_15: # %entry
; CHECK-NOV-NEXT: lui a2, 524288 ; CHECK-NOV-NEXT: lui a2, 524288
; CHECK-NOV-NEXT: blt a1, s2, .LBB6_7 ; CHECK-NOV-NEXT: blt a1, s2, .LBB6_7
; CHECK-NOV-NEXT: .LBB6_16: # %entry ; CHECK-NOV-NEXT: .LBB6_16: # %entry
; CHECK-NOV-NEXT: lui s2, 524288 ; CHECK-NOV-NEXT: lui s2, 524288
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; CHECK-NOV-NEXT: bge a2, a1, .LBB27_8 ; CHECK-NOV-NEXT: bge a2, a1, .LBB27_8
; CHECK-NOV-NEXT: .LBB27_4: # %entry ; CHECK-NOV-NEXT: .LBB27_4: # %entry
; CHECK-NOV-NEXT: ret ; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB27_5: # %entry ; CHECK-NOV-NEXT: .LBB27_5: # %entry
; CHECK-NOV-NEXT: mv a1, a3 ; CHECK-NOV-NEXT: mv a1, a3
; CHECK-NOV-NEXT: blt a0, a3, .LBB27_2 ; CHECK-NOV-NEXT: blt a0, a3, .LBB27_2
; CHECK-NOV-NEXT: .LBB27_6: # %entry ; CHECK-NOV-NEXT: .LBB27_6: # %entry
; CHECK-NOV-NEXT: mv a0, a3 ; CHECK-NOV-NEXT: mv a0, a3
; CHECK-NOV-NEXT: blt a2, a0, .LBB27_3 ; CHECK-NOV-NEXT: blt a2, a3, .LBB27_3
; CHECK-NOV-NEXT: .LBB27_7: # %entry ; CHECK-NOV-NEXT: .LBB27_7: # %entry
; CHECK-NOV-NEXT: lui a0, 524288 ; CHECK-NOV-NEXT: lui a0, 524288
; CHECK-NOV-NEXT: blt a2, a1, .LBB27_4 ; CHECK-NOV-NEXT: blt a2, a1, .LBB27_4
; CHECK-NOV-NEXT: .LBB27_8: # %entry ; CHECK-NOV-NEXT: .LBB27_8: # %entry
; CHECK-NOV-NEXT: lui a1, 524288 ; CHECK-NOV-NEXT: lui a1, 524288
; CHECK-NOV-NEXT: ret ; CHECK-NOV-NEXT: ret
; ;
; CHECK-V-LABEL: stest_f64i32_mm: ; CHECK-V-LABEL: stest_f64i32_mm:
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; CHECK-NOV-NEXT: mv a2, a6 ; CHECK-NOV-NEXT: mv a2, a6
; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz ; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz
; CHECK-NOV-NEXT: blt a4, a6, .LBB30_3 ; CHECK-NOV-NEXT: blt a4, a6, .LBB30_3
; CHECK-NOV-NEXT: .LBB30_12: # %entry ; CHECK-NOV-NEXT: .LBB30_12: # %entry
; CHECK-NOV-NEXT: mv a4, a6 ; CHECK-NOV-NEXT: mv a4, a6
; CHECK-NOV-NEXT: blt a5, a6, .LBB30_4 ; CHECK-NOV-NEXT: blt a5, a6, .LBB30_4
; CHECK-NOV-NEXT: .LBB30_13: # %entry ; CHECK-NOV-NEXT: .LBB30_13: # %entry
; CHECK-NOV-NEXT: mv a5, a6 ; CHECK-NOV-NEXT: mv a5, a6
; CHECK-NOV-NEXT: blt a3, a5, .LBB30_5 ; CHECK-NOV-NEXT: blt a3, a6, .LBB30_5
; CHECK-NOV-NEXT: .LBB30_14: # %entry ; CHECK-NOV-NEXT: .LBB30_14: # %entry
; CHECK-NOV-NEXT: lui a5, 524288 ; CHECK-NOV-NEXT: lui a5, 524288
; CHECK-NOV-NEXT: blt a3, a4, .LBB30_6 ; CHECK-NOV-NEXT: blt a3, a4, .LBB30_6
; CHECK-NOV-NEXT: .LBB30_15: # %entry ; CHECK-NOV-NEXT: .LBB30_15: # %entry
; CHECK-NOV-NEXT: lui a4, 524288 ; CHECK-NOV-NEXT: lui a4, 524288
; CHECK-NOV-NEXT: blt a3, a2, .LBB30_7 ; CHECK-NOV-NEXT: blt a3, a2, .LBB30_7
; CHECK-NOV-NEXT: .LBB30_16: # %entry ; CHECK-NOV-NEXT: .LBB30_16: # %entry
; CHECK-NOV-NEXT: lui a2, 524288 ; CHECK-NOV-NEXT: lui a2, 524288
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; CHECK-NOV-NEXT: mv s2, a4 ; CHECK-NOV-NEXT: mv s2, a4
; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz ; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz
; CHECK-NOV-NEXT: blt a2, a4, .LBB33_3 ; CHECK-NOV-NEXT: blt a2, a4, .LBB33_3
; CHECK-NOV-NEXT: .LBB33_12: # %entry ; CHECK-NOV-NEXT: .LBB33_12: # %entry
; CHECK-NOV-NEXT: mv a2, a4 ; CHECK-NOV-NEXT: mv a2, a4
; CHECK-NOV-NEXT: blt a3, a4, .LBB33_4 ; CHECK-NOV-NEXT: blt a3, a4, .LBB33_4
; CHECK-NOV-NEXT: .LBB33_13: # %entry ; CHECK-NOV-NEXT: .LBB33_13: # %entry
; CHECK-NOV-NEXT: mv a3, a4 ; CHECK-NOV-NEXT: mv a3, a4
; CHECK-NOV-NEXT: blt a1, a3, .LBB33_5 ; CHECK-NOV-NEXT: blt a1, a4, .LBB33_5
; CHECK-NOV-NEXT: .LBB33_14: # %entry ; CHECK-NOV-NEXT: .LBB33_14: # %entry
; CHECK-NOV-NEXT: lui a3, 524288 ; CHECK-NOV-NEXT: lui a3, 524288
; CHECK-NOV-NEXT: blt a1, a2, .LBB33_6 ; CHECK-NOV-NEXT: blt a1, a2, .LBB33_6
; CHECK-NOV-NEXT: .LBB33_15: # %entry ; CHECK-NOV-NEXT: .LBB33_15: # %entry
; CHECK-NOV-NEXT: lui a2, 524288 ; CHECK-NOV-NEXT: lui a2, 524288
; CHECK-NOV-NEXT: blt a1, s2, .LBB33_7 ; CHECK-NOV-NEXT: blt a1, s2, .LBB33_7
; CHECK-NOV-NEXT: .LBB33_16: # %entry ; CHECK-NOV-NEXT: .LBB33_16: # %entry
; CHECK-NOV-NEXT: lui s2, 524288 ; CHECK-NOV-NEXT: lui s2, 524288
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

Show First 20 Lines • Show All 1,182 Lines • ▼ Show 20 Lines
} }
; A rather pathological test case in which we exhaust all vector registers and ; A rather pathological test case in which we exhaust all vector registers and
; all scalar registers, forcing %z and %8 to go through the stack. ; all scalar registers, forcing %z and %8 to go through the stack.
define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8) { define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8) {
; LMULMAX8-LABEL: vector_arg_via_stack: ; LMULMAX8-LABEL: vector_arg_via_stack:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: mv a1, sp
; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; LMULMAX8-NEXT: vle32.v v16, (a1) ; LMULMAX8-NEXT: vle32.v v16, (sp)
; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v16
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: vector_arg_via_stack: ; LMULMAX4-LABEL: vector_arg_via_stack:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: mv a0, sp ; LMULMAX4-NEXT: vle32.v v16, (sp)
; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: addi a0, sp, 64 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vle32.v v20, (a0) ; LMULMAX4-NEXT: vle32.v v20, (a0)
; LMULMAX4-NEXT: vadd.vv v8, v8, v16 ; LMULMAX4-NEXT: vadd.vv v8, v8, v16
; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
; ;
; LMULMAX2-LABEL: vector_arg_via_stack: ; LMULMAX2-LABEL: vector_arg_via_stack:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: addi a0, sp, 64 ; LMULMAX2-NEXT: addi a0, sp, 64
; LMULMAX2-NEXT: vle32.v v16, (a0) ; LMULMAX2-NEXT: vle32.v v16, (a0)
; LMULMAX2-NEXT: mv a0, sp ; LMULMAX2-NEXT: vle32.v v18, (sp)
; LMULMAX2-NEXT: vle32.v v18, (a0)
; LMULMAX2-NEXT: addi a0, sp, 32 ; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vle32.v v20, (a0) ; LMULMAX2-NEXT: vle32.v v20, (a0)
; LMULMAX2-NEXT: addi a0, sp, 96 ; LMULMAX2-NEXT: addi a0, sp, 96
; LMULMAX2-NEXT: vle32.v v22, (a0) ; LMULMAX2-NEXT: vle32.v v22, (a0)
; LMULMAX2-NEXT: vadd.vv v8, v8, v18 ; LMULMAX2-NEXT: vadd.vv v8, v8, v18
; LMULMAX2-NEXT: vadd.vv v10, v10, v20 ; LMULMAX2-NEXT: vadd.vv v10, v10, v20
; LMULMAX2-NEXT: vadd.vv v12, v12, v16 ; LMULMAX2-NEXT: vadd.vv v12, v12, v16
; LMULMAX2-NEXT: vadd.vv v14, v14, v22 ; LMULMAX2-NEXT: vadd.vv v14, v14, v22
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: vector_arg_via_stack: ; LMULMAX1-LABEL: vector_arg_via_stack:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, sp, 112 ; LMULMAX1-NEXT: addi a0, sp, 112
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, sp, 96 ; LMULMAX1-NEXT: addi a0, sp, 96
; LMULMAX1-NEXT: vle32.v v17, (a0) ; LMULMAX1-NEXT: vle32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, sp, 80 ; LMULMAX1-NEXT: addi a0, sp, 80
; LMULMAX1-NEXT: vle32.v v18, (a0) ; LMULMAX1-NEXT: vle32.v v18, (a0)
; LMULMAX1-NEXT: addi a0, sp, 64 ; LMULMAX1-NEXT: addi a0, sp, 64
; LMULMAX1-NEXT: vle32.v v19, (a0) ; LMULMAX1-NEXT: vle32.v v19, (a0)
; LMULMAX1-NEXT: addi a0, sp, 32 ; LMULMAX1-NEXT: addi a0, sp, 32
; LMULMAX1-NEXT: vle32.v v20, (a0) ; LMULMAX1-NEXT: vle32.v v20, (a0)
; LMULMAX1-NEXT: mv a0, sp ; LMULMAX1-NEXT: vle32.v v21, (sp)
; LMULMAX1-NEXT: vle32.v v21, (a0)
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vle32.v v22, (a0) ; LMULMAX1-NEXT: vle32.v v22, (a0)
; LMULMAX1-NEXT: addi a0, sp, 48 ; LMULMAX1-NEXT: addi a0, sp, 48
; LMULMAX1-NEXT: vle32.v v23, (a0) ; LMULMAX1-NEXT: vle32.v v23, (a0)
; LMULMAX1-NEXT: vadd.vv v8, v8, v21 ; LMULMAX1-NEXT: vadd.vv v8, v8, v21
; LMULMAX1-NEXT: vadd.vv v9, v9, v22 ; LMULMAX1-NEXT: vadd.vv v9, v9, v22
; LMULMAX1-NEXT: vadd.vv v10, v10, v20 ; LMULMAX1-NEXT: vadd.vv v10, v10, v20
; LMULMAX1-NEXT: vadd.vv v11, v11, v23 ; LMULMAX1-NEXT: vadd.vv v11, v11, v23
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llvm/test/CodeGen/RISCV/sadd_sat.ll

Show All 31 Lines
; RV64I-NEXT: addiw a2, a1, -1 ; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: bge a0, a2, .LBB0_3 ; RV64I-NEXT: bge a0, a2, .LBB0_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bge a1, a0, .LBB0_4 ; RV64I-NEXT: bge a1, a0, .LBB0_4
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_3: ; RV64I-NEXT: .LBB0_3:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: blt a1, a0, .LBB0_2 ; RV64I-NEXT: blt a1, a2, .LBB0_2
; RV64I-NEXT: .LBB0_4: ; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lui a0, 524288 ; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZbb-LABEL: func: ; RV64IZbb-LABEL: func:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: add a0, a0, a1 ; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: lui a1, 524288 ; RV64IZbb-NEXT: lui a1, 524288
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llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

Show All 34 Lines
; RV64I-NEXT: addiw a2, a1, -1 ; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: bge a0, a2, .LBB0_3 ; RV64I-NEXT: bge a0, a2, .LBB0_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bge a1, a0, .LBB0_4 ; RV64I-NEXT: bge a1, a0, .LBB0_4
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_3: ; RV64I-NEXT: .LBB0_3:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: blt a1, a0, .LBB0_2 ; RV64I-NEXT: blt a1, a2, .LBB0_2
; RV64I-NEXT: .LBB0_4: ; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lui a0, 524288 ; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZbb-LABEL: func32: ; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.w a0, a0 ; RV64IZbb-NEXT: sext.w a0, a0
; RV64IZbb-NEXT: mulw a1, a1, a2 ; RV64IZbb-NEXT: mulw a1, a1, a2
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llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bne a0, a4, .LBB6_4 ; RV32I-NEXT: bne a0, a4, .LBB6_4
; RV32I-NEXT: .LBB6_2: # %entry ; RV32I-NEXT: .LBB6_2: # %entry
; RV32I-NEXT: add a0, a1, a2 ; RV32I-NEXT: add a0, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB6_3: # %entry ; RV32I-NEXT: .LBB6_3: # %entry
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: beq a0, a4, .LBB6_2 ; RV32I-NEXT: beq a0, a4, .LBB6_2
; RV32I-NEXT: .LBB6_4: # %entry ; RV32I-NEXT: .LBB6_4: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: add a0, a1, a3
; RV32I-NEXT: add a0, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmovccdep: ; RV64I-LABEL: cmovccdep:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a4, 123 ; RV64I-NEXT: li a4, 123
; RV64I-NEXT: bne a0, a4, .LBB6_3 ; RV64I-NEXT: bne a0, a4, .LBB6_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bne a0, a4, .LBB6_4 ; RV64I-NEXT: bne a0, a4, .LBB6_4
; RV64I-NEXT: .LBB6_2: # %entry ; RV64I-NEXT: .LBB6_2: # %entry
; RV64I-NEXT: addw a0, a1, a2 ; RV64I-NEXT: addw a0, a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_3: # %entry ; RV64I-NEXT: .LBB6_3: # %entry
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: beq a0, a4, .LBB6_2 ; RV64I-NEXT: beq a0, a4, .LBB6_2
; RV64I-NEXT: .LBB6_4: # %entry ; RV64I-NEXT: .LBB6_4: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: addw a0, a1, a3
; RV64I-NEXT: addw a0, a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cmp = icmp eq i32 %a, 123 %cmp = icmp eq i32 %a, 123
%cond1 = select i1 %cmp, i32 %b, i32 %c %cond1 = select i1 %cmp, i32 %b, i32 %c
%cond2 = select i1 %cmp, i32 %cond1, i32 %d %cond2 = select i1 %cmp, i32 %cond1, i32 %d
%ret = add i32 %cond1, %cond2 %ret = add i32 %cond1, %cond2
ret i32 %ret ret i32 %ret
} }
Show All 10 Lines
; RV32I-NEXT: beqz a1, .LBB7_4 ; RV32I-NEXT: beqz a1, .LBB7_4
; RV32I-NEXT: .LBB7_2: # %entry ; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_3: # %entry ; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2 ; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry ; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5 ; RV32I-NEXT: add a0, a2, a5
; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: cmovdiffcc: ; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: andi a1, a1, 1 ; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: beqz a0, .LBB7_3 ; RV64I-NEXT: beqz a0, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: beqz a1, .LBB7_4 ; RV64I-NEXT: beqz a1, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry ; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry ; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2 ; RV64I-NEXT: bnez a1, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry ; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5 ; RV64I-NEXT: addw a0, a2, a5
; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%cond1 = select i1 %a, i32 %c, i32 %d %cond1 = select i1 %a, i32 %c, i32 %d
%cond2 = select i1 %b, i32 %e, i32 %f %cond2 = select i1 %b, i32 %e, i32 %f
%ret = add i32 %cond1, %cond2 %ret = add i32 %cond1, %cond2
ret i32 %ret ret i32 %ret
} }
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llvm/test/CodeGen/RISCV/split-offsets.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32I-LABEL: test2: ; RV32I-LABEL: test2:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lui a4, 20 ; RV32I-NEXT: lui a4, 20
; RV32I-NEXT: addi a4, a4, -1920 ; RV32I-NEXT: addi a4, a4, -1920
; RV32I-NEXT: add a1, a1, a4 ; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: add a0, a0, a4
; RV32I-NEXT: bge a3, a2, .LBB1_2 ; RV32I-NEXT: blez a2, .LBB1_2
; RV32I-NEXT: .LBB1_1: # %while_body ; RV32I-NEXT: .LBB1_1: # %while_body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: addi a4, a3, 1 ; RV32I-NEXT: addi a4, a3, 1
; RV32I-NEXT: sw a4, 0(a0) ; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0) ; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a4, 0(a1) ; RV32I-NEXT: sw a4, 0(a1)
; RV32I-NEXT: sw a3, 4(a1) ; RV32I-NEXT: sw a3, 4(a1)
; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: blt a3, a2, .LBB1_1 ; RV32I-NEXT: blt a4, a2, .LBB1_1
; RV32I-NEXT: .LBB1_2: # %while_end ; RV32I-NEXT: .LBB1_2: # %while_end
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test2: ; RV64I-LABEL: test2:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: ld a0, 0(a0) ; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: lui a4, 20 ; RV64I-NEXT: lui a4, 20
; RV64I-NEXT: addiw a4, a4, -1920 ; RV64I-NEXT: addiw a4, a4, -1920
; RV64I-NEXT: add a1, a1, a4 ; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: add a0, a0, a4 ; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: sext.w a2, a2 ; RV64I-NEXT: sext.w a2, a2
; RV64I-NEXT: bge a3, a2, .LBB1_2 ; RV64I-NEXT: blez a2, .LBB1_2
; RV64I-NEXT: .LBB1_1: # %while_body ; RV64I-NEXT: .LBB1_1: # %while_body
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: addiw a4, a3, 1 ; RV64I-NEXT: addiw a4, a3, 1
; RV64I-NEXT: sw a4, 0(a0) ; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: sw a3, 4(a0) ; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: sw a4, 0(a1) ; RV64I-NEXT: sw a4, 0(a1)
; RV64I-NEXT: sw a3, 4(a1) ; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: mv a3, a4 ; RV64I-NEXT: mv a3, a4
; RV64I-NEXT: blt a3, a2, .LBB1_1 ; RV64I-NEXT: blt a4, a2, .LBB1_1
; RV64I-NEXT: .LBB1_2: # %while_end ; RV64I-NEXT: .LBB1_2: # %while_end
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%s = load ptr, ptr %sp %s = load ptr, ptr %sp
br label %while_cond br label %while_cond
while_cond: while_cond:
%phi = phi i32 [ 0, %entry ], [ %i, %while_body ] %phi = phi i32 [ 0, %entry ], [ %i, %while_body ]
%gep0 = getelementptr [65536 x i32], ptr %s, i64 0, i32 20000 %gep0 = getelementptr [65536 x i32], ptr %s, i64 0, i32 20000
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llvm/test/CodeGen/RISCV/ssub_sat.ll

Show All 31 Lines
; RV64I-NEXT: addiw a2, a1, -1 ; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: bge a0, a2, .LBB0_3 ; RV64I-NEXT: bge a0, a2, .LBB0_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bge a1, a0, .LBB0_4 ; RV64I-NEXT: bge a1, a0, .LBB0_4
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_3: ; RV64I-NEXT: .LBB0_3:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: blt a1, a0, .LBB0_2 ; RV64I-NEXT: blt a1, a2, .LBB0_2
; RV64I-NEXT: .LBB0_4: ; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lui a0, 524288 ; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZbb-LABEL: func: ; RV64IZbb-LABEL: func:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sub a0, a0, a1 ; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: lui a1, 524288 ; RV64IZbb-NEXT: lui a1, 524288
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

Show All 34 Lines
; RV64I-NEXT: addiw a2, a1, -1 ; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: bge a0, a2, .LBB0_3 ; RV64I-NEXT: bge a0, a2, .LBB0_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bge a1, a0, .LBB0_4 ; RV64I-NEXT: bge a1, a0, .LBB0_4
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_3: ; RV64I-NEXT: .LBB0_3:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: blt a1, a0, .LBB0_2 ; RV64I-NEXT: blt a1, a2, .LBB0_2
; RV64I-NEXT: .LBB0_4: ; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lui a0, 524288 ; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZbb-LABEL: func32: ; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.w a0, a0 ; RV64IZbb-NEXT: sext.w a0, a0
; RV64IZbb-NEXT: mulw a1, a1, a2 ; RV64IZbb-NEXT: mulw a1, a1, a2
▲ Show 20 Lines • Show All 282 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O3 -mattr=+v -lsr-drop-solution | FileCheck --check-prefix=CHECK %s ; RUN: llc < %s -O3 -mattr=+v -lsr-drop-solution | FileCheck --check-prefix=CHECK %s
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64-unknown-linux-gnu" target triple = "riscv64-unknown-linux-gnu"
define ptr @foo(ptr %a0, ptr %a1, i64 %a2) { define ptr @foo(ptr %a0, ptr %a1, i64 %a2) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, ma
; CHECK-NEXT: bne a4, a2, .LBB0_2 ; CHECK-NEXT: bne a4, a2, .LBB0_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a0
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %if.then ; CHECK-NEXT: .LBB0_2: # %if.then
; CHECK-NEXT: add a2, a0, a2 ; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: sub a5, a2, a4 ; CHECK-NEXT: sub a5, a2, a4
; CHECK-NEXT: mv a3, a0 ; CHECK-NEXT: mv a3, a0
; CHECK-NEXT: .LBB0_3: # %do.body ; CHECK-NEXT: .LBB0_3: # %do.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines