[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation

[asb]

Summary

D144535 enabled machine copy propagation for RISC-V and added it to the pass pipeline in addPreEmitPass2 (after the MachineOutliner). Unfortunately, the MachineCopyPropagation pass is unable to correctly analyse outlined functions, and will delete copy instructions where a register is set that is intended to be live-out. RISCVInstrInfo::buildOutlinedFrame will directly insert a JALR, while a similar function going through the normal codegen path would have a PseudoRet with operands indicating registers that are live-out.

This patch does the simplest fix, which is to run MachineCopyPropagation before the MachineOutliner. I think it would make sense to land something like this quickly, but I'd also be interested in discussing thoughts on a "better" follow-up fix that might allow MCP to run later in the pipeline.

[craig.topper]

LGTM

[• pcwang-thead]

Thanks for the fix!

I posted two patches that may be approach to fix this issue:

• D146191: [MachineOutliner][MCP][RISCV] Don't run MCP on outlined functions.
• D146192: [RISCV] Add an empty block after outlined MBB.

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

bool RISCVPassConfig::addGlobalInstructionSelect() {
   return false;
 }
 
 void RISCVPassConfig::addPreSched2() {}
 
 void RISCVPassConfig::addPreEmitPass() {
   addPass(&BranchRelaxationPassID);
   addPass(createRISCVMakeCompressibleOptPass());
+
+  // TODO: It would potentially be better to schedule copy propagation after
+  // expanding pseudos (in addPreEmitPass2). However, performing copy
+  // propagation after the machine outliner (which runs after addPreEmitPass)
+  // currently leads to incorrect code-gen, where copies to registers within
+  // outlined functions are removed erroneously.
+  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
+    addPass(createMachineCopyPropagationPass(true));
 }
 
 void RISCVPassConfig::addPreEmitPass2() {
   addPass(createRISCVExpandPseudoPass());
 
-  // Do the copy propagation after expanding pseudos because we may produce some
-  // MVs when expanding.
-  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
-    addPass(createMachineCopyPropagationPass(true));
-
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.
   addPass(createRISCVExpandAtomicPseudoPass());
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();

llvm/test/CodeGen/RISCV/O3-pipeline.ll

 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement
 ; CHECK-NEXT:       Insert fentry calls
 ; CHECK-NEXT:       Insert XRay ops
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       Branch relaxation pass
 ; CHECK-NEXT:       RISCV Make Compressible
+; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       Contiguously Lay Out Funclets
 ; CHECK-NEXT:       StackMap Liveness Analysis
 ; CHECK-NEXT:       Live DEBUG_VALUE analysis
 ; CHECK-NEXT:       Machine Sanitizer Binary Metadata
 ; CHECK-NEXT:     Machine Outliner
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       Stack Frame Layout Analysis
 ; CHECK-NEXT:       RISCV pseudo instruction expansion pass
-; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       RISCV atomic pseudo instruction expansion pass
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       RISCV Assembly Printer
 ; CHECK-NEXT:       Free MachineFunction

llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs --version 2
 ; RUN: llc -mtriple=riscv64 -riscv-enable-copy-propagation -enable-machine-outliner -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 
 ; The outlined function produced by this test case contains a register to
 ; register copy, which is at risk of being removed by MachineCopyPropagation
 ; if it can't see that the copy is used. At the time of writing this test
 ; case, MCP will remove the copy if it is run after the machine outliner.
-; FIXME: Ensure machine copy propagation is run before the machine outliner so
-; the copy in the outlined function isn't erroneously removed.
 
 define signext i32 @nge(i32 signext %a, i32 signext %b) nounwind {
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv.neg = sext i1 %cmp to i32
   ret i32 %conv.neg
 }
 

 ; RV64I-NEXT:  .LBB4_9: # %if.then
 ; RV64I-NEXT:    call abort@plt
 ;
 ; RV64I-LABEL: OUTLINED_FUNCTION_0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui s0, 524288
 ; RV64I-NEXT:    addiw s0, s0, -1
 ; RV64I-NEXT:    lui a0, 524288
+; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    jr t0