[RFC][X86][MemFold] Upgrade the mechanism of auto-generated Memory Folding Table

[yubing]

Summary

1. Align ManualMapSet with X86MemoryFoldTableEntry instead of using UnfoldStrategy
2. ManualMapSet able to update the existing record in auto-generated MemFold table

[yubing]

PLAN:

1. Move MemoryFoldTable2Addr MemoryFoldTable0~4 into X86InstrFoldTables.def from llvm/lib/Target/X86/X86InstrFoldTables.cpp https://reviews.llvm.org/D142083
2. Update llvm/lib/Target/X86/X86InstrFoldTables.def with adding records, mainly for avx512fp16 https://reviews.llvm.org/D143149
3. Upgrade mechanism of auto-generated memfolding table https://reviews.llvm.org/D142084
4. Update ManualMapSet in X86FoldTablesEmitter.cpp to make x86-auto-memfold.td pass
5. small modification for remaining different ~30 records

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

33

Where is NO_STRATEGY define? It looks like it was deleted from the left hand of this diff.

[skan]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

61

Don't duplicate the definitions in llvm/lib/Target/X86/X86InstrFoldTables.h, try finding a common place

82

See my comments in https://reviews.llvm.org/D142083, we can change thing to print here

[yubing]

give 0 to default Strategy of ManualMapEntry

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

33

changed to 0

[skan]

llvm/test/TableGen/x86-auto-memfold.td

3

Drop "-asmwriternum=1" "-write-if-changed"

4

Drop this line by using pipleline in the previous line.

5

We should remove all the \t or space in INC file, don't use "tr" for it.

8

Drop the XFAIL, this patch should be merged after fp16 records are added.

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

45–46

Move this into a .inc as a whitelist

[pengfei]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

30

Remove.

50

1?

122

Should be a space here.

124

Add assert to make sure LHS and RHS not null?

389

How about !!(S & TB_NO_REVERSE)?

[yubing]

address all the comments

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

50

i copy the enum's definition from llvm/lib/Target/X86/X86InstrFoldTables.h

122

clang-format can't do this. i observed

[skan]

llvm/test/TableGen/x86-auto-memfold.td

3

Question: what do we skip here?

[skan]

llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

2

This comment does not applies to all the entries in the table, I think we should move it to a suitable place. in this file.
And we need a clarification for each group in this table.

[yubing]

llvm/test/TableGen/x86-auto-memfold.td

3

the first 568 bytes are:

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* X86 fold tables                                                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

[skan]

Reverse ping @yubing

[yubing]

squash D143149

[RKSimon]

llvm/lib/Target/X86/X86MemFoldTables.inc

261

It would be good to get some/all of these diffs committed first to minimize any changes in codegen due to this patch - the patch should only be about the build process.

[skan]

llvm/lib/Target/X86/X86MemFoldTables.inc

261

Both methods are okay to me. I suggested the author to merge the table change into this PR b/c we are not confident the update in the table is correct. The new table needs a careful review.

And if the reviewer doubted an entry was incorrect, the author could point out which rule used in the X86FoldTablesEmitter.cpp was "guilty" and get suggestion/feedback from reviewers.

A separate diff would be the best way if we could check the correctness of the table just by looking at the entry themselves.

[yubing]

llvm/lib/Target/X86/X86MemFoldTables.inc

508–509

should remove one of them otherwise leads to duplicate entry in unfolding table.
i will remove {X86::MMX_MOVQ64rr, X86::MMX_MOVQ64rm, 0}, and write "{X86::MMX_MOVQ64rr, X86::MMX_MOVQ64rm, noforward || noreverse}," in llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

[craig.topper]

llvm/lib/Target/X86/X86MemFoldTables.inc

612

These aren't real load instructions. It doesn't really make sense for them to be in the table. Folding the load would make the load not happen. That would be incorrect for volatile.

4009

Would this allow unfolding a VMOVAPDZ128rmk to VMOVAPDZ128rrk + VMOVAPDZ128rm? That would be a bug.

[yubing]

llvm/lib/Target/X86/X86MemFoldTables.inc

4009

@craig.topper
https://discourse.llvm.org/t/auto-generate-the-memory-folding-tables/61100/19
i remember we always fold whole load intrinsics into masked arithmetic. does it happen to masked movereg instruction as well?(only wholeload+ movereg => mask.load)

besides, do we need to add TB_NO_REVERSE for {X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16}?

[craig.topper]

llvm/lib/Target/X86/X86MemFoldTables.inc

4009

What I said previously applied to arithmetic that has loads folded into them.

VMOVAPDZ128rmk is created from a masked load with an isel pattern.

VMOVAPDZ128rm will never be unfolded. We unfold to separate a loop invariant load from arithmetic. There’s no arithmetic folded in to it.. the only operands are address operands. They would all need to be loop invariant to hoist so the whole instruction is hoistable.

For VMOVAPDZ128rmk there is a mask operand and address operands. Without TB_NO_REVERSE we would try to unfold it if the address was loop invariant but the mask wasn’t. This would be incorrect. The mask may be masking off elements that will fault.

[yubing]

llvm/lib/Target/X86/X86MemFoldTables.inc

4009

thanks for explanation. i also check the code in llvm/lib/CodeGen/MachineLICM.cpp

// First check whether we should hoist this instruction.
if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
  // If not, try unfolding a hoistable load.
  MI = ExtractHoistableLoad(MI);
  if (!MI) return false;
}

since VMOVAPDZ128rmk((the address isloop invariant but the mask is not)) is not IsLoopInvariantInst, we can extract a wholeload from it if it is Without TB_NO_REVERSE. so what you said about VMOVAPDZ128rmk and VMOVAPDZ128rm makes sense to me.

[yubing]

make X86::VMOVAPDZ128rrk, X86::VMOVAPDZ128rmk TB_NO_REVERSE

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

429

Is there better way to check no-kz version's isMoveReg?

[yubing]

remove {"MMX_MOVQ64rr", "MMX_MOVQ64mr"}

[yubing]

disable {"MMX_MOVQ64rr", "MMX_MOVQ64rm"} as well

[yubing]

add comments for removing {"MMX_MOVQ64rr", "MMX_MOVQ64rm"}

[yubing]

the patch can let internal testcase pass. no regression was found in benchmark.

[yubing]

small rebase

[yubing]

ping? @skan

[skan]

LGTM in general

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

19

What's header file Error.h used for?

87

Drop the comment?

110

Is this operator never used?

127

Why do we need to compare isPseudo?

432

Do we need to assert the result of getDef is not NULL?

439

Why do we need Result.IsStore here?

[skan]

llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

78

unfoldingtable -> unfolding table

81

ditto

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

load such as VMOVAPDZ128rm will never be unfolded.
if VMOVAPDZ128rm 's memoperand is invariant, then VMOVAPDZ128rm will be hoisted directly and won't be unfolded into rm+rr
if VMOVAPDZ128rm 's memoperand is not invariant, we stop doing unfolding since compiler find it is a simple load.

// First check whether we should hoist this instruction.
if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
  // If not, try unfolding a hoistable load.
  MI = ExtractHoistableLoad(MI);
  if (!MI) return false;
}

MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
  // Don't unfold simple loads.
  if (MI->canFoldAsLoad())
    return nullptr;

@craig.topper , does line429~439 make sense to you as well?

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

127

I copy the code from "bool operator<(const X86FoldTableEntry &RHS) const {",
@craig.topper , i saw the author of "bool operator<(const X86FoldTableEntry &RHS) const {" is you. do you still remember why we need to compare isPseudo here?

[skan]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

127

I think it's a NFC change from me. If we remove this comparison, will any test fail?

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

127

It's the sort order for the enum in X86GenInstrInfo.inc. Instructions with isPseudo set are ordered before other instructions.

[yubing]

does unfolding only happen in LICM?

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

@craig.topper i think my analysis of VMOVAPDZ128rm is only for LICM. but for other passes in codegen, is it possible for VMOVAPDZ128rm to be unfolded?

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

The other 2 places I know that unfold are TwoAddressInstructionPass and SelectionDAG->MachineIR

TwoAddressInstuctionPass should only happen for instructions with tied source and dest. That doesn't apply to moveReg.

I think SelectionDAG->MachineIR case happens if we need to duplicate an instruction that has an EFLAGS def. If the EFLAGS are used by two instructions and EFLAGS is clobbered in between them. We need to duplicate the flag producing instruction to satisfy the second user. But we can't duplicate the folded load so we have to unfold. That doesn't apply to moveReg.

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

i saw two kinds of unfoldMemoryOperand, one of which is for MIR and another is for DAG. Our folding table can't affect unfoldMemoryOperand for DAG, right?
and unfoldMemoryOperand for MIR only happens in LICM, TwoAddress, X86CMOVConversion, X86KCFI, and X86SpeculativeLoadHardening.
i checked VMOVAPDZ128rm won't be handled in those Pasess. so we don't worry if we need to set TB_NO_REVERSE for VMOVAPDZ128rm.

[yubing]

address skan's comments

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

I think the DAG unfoldMemoryOperand uses the same table.

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

The DAG unfold occurs after the isel portion of SelectionDAG. So it's MachineOpcodes

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

oh, you're right. unfoldMemoryOperand is trying to find the MIR according to DAGNode's Machinecode, and then lookupUnfoldTable

bool
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
                                  SmallVectorImpl<SDNode*> &NewNodes) const {
  if (!N->isMachineOpcode())
    return false;

  const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());

@craig.topper , but where can i find the code of DAG unfold which occurs after the isel portion of SelectionDAG?
i saw unfoldMemoryOperand(for DAG) in llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

439

ScheduleDAGRRList.cpp is the code. The DAG needs to be scheduled into linear basic block for MachineIR.

[yubing]

llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

31

for myself, why " { "TAILJMPr", "TAILJMPm", TB_FOLDED_LOAD }," listed here.

[steven_wu]

llvm/test/TableGen/x86-auto-memfold.td

3

From the manpage of cmp, it should be like:

cmp [OPTIONS] file1 file2

There are some implementation that cannot take --ignore-initial after the files. Can you move it to the front?

[smeenai]

llvm/test/TableGen/x86-auto-memfold.td

3

This was breaking our tests on macOS as well, so I pushed rG7e271c2a8552 to fix.

[vitalybuka]

Breaks this bot https://lab.llvm.org/buildbot/#/builders/5/builds/32220/steps/16/logs/stdio

[yubing]

In D142084#4201278, @vitalybuka wrote:

Breaks this bot https://lab.llvm.org/buildbot/#/builders/5/builds/32220/steps/16/logs/stdio

@vitalybuka , do you know how to reproduce the issue by buildbot_fast.sh?
i tried https://github.com/google/sanitizers/wiki/SanitizerBotReproduceBuild#try-local-changes
but it set HEAD wrongly at

commit 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a
Author: Nikolas Klauser <[e-mail]>
Date:   Thu Nov 17 21:34:29 2022 +0100

    [libc++] Fix memory leaks when throwing inside std::vector constructors

    Fixes #58392

    Reviewed By: ldionne, #libc

    Spies: alexfh, hans, joanahalili, dblaikie, libcxx-commits

    Differential Revision: https://reviews.llvm.org/D138601

[yubing]

@hctim do you know how to reproduce the ubsan issue elegantly. after i spend some time modify buildbot_functions.sh, i still can't reproduce it locally. https://lab.llvm.org/buildbot/#/builders/5/builds/32220/steps/16/logs/stdio

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

394

Is it possible for S & TB_ALIGN_MASK to be 0? That would cause 1<< -1 which would match the ubsan error

[yubing]

address ubsan issue and ignore-initial issue

[craig.topper]

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

395

Use a variable instead of repeating the same code twice?

[yubing]

address Craig's comments

[fdeazeve]

This commit may be breaking this bot:
https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/52590/console

llvm-project/llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc:4:48: error: use of undeclared identifier 'TB_NO_REVERSE'
    { "ADD16ri_DB",         "ADD16mi",         TB_NO_REVERSE  },

[fdeazeve]

Also note that the pre-merge checks failed to clang format these files:

llvm/include/llvm/Support/X86FoldTablesUtils.h
llvm/lib/Target/X86/X86InstrFoldTables.h
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

[fdeazeve]

llvm/include/llvm/Support/X86FoldTablesUtils.h

12

The anon namespace is causing the bot failure, was a there a particular reason for this change? If not, I'll submit a patch

[skan]

llvm/include/llvm/Support/X86FoldTablesUtils.h

12

I think it's a typo by the author of this patch.

[abhina.sreeskantharajan]

Hi, this is also causing a failure on the clang-ppc64-aix bot https://lab.llvm.org/buildbot/#/builders/214/builds/6519

+ : 'RUN: at line 1'
+ /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/bin/llvm-tblgen -gen-x86-fold-tables -asmwriternum=1 /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/X86.td -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../include -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/ -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../include/ -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/ --write-if-changed -o /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/test/TableGen/Output/x86-auto-memfold.td.tmp1
+ : 'RUN: at line 2'
+ cmp --ignore-initial=0:568 /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/X86MemFoldTables.inc /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/test/TableGen/Output/x86-auto-memfold.td.tmp1
cmp: illegal option -- -
usage: cmp [-l | -s] file1 file2

[yubing]

llvm/include/llvm/Support/X86FoldTablesUtils.h

12

thanks for fixing it.

[yubing]

In D142084#4206765, @abhina.sreeskantharajan wrote:

Hi, this is also causing a failure on the clang-ppc64-aix bot https://lab.llvm.org/buildbot/#/builders/214/builds/6519

+ : 'RUN: at line 1'
+ /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/bin/llvm-tblgen -gen-x86-fold-tables -asmwriternum=1 /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/X86.td -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../include -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/ -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../include/ -I /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/ --write-if-changed -o /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/test/TableGen/Output/x86-auto-memfold.td.tmp1
+ : 'RUN: at line 2'
+ cmp --ignore-initial=0:568 /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/llvm-project/llvm/test/TableGen/../../lib/Target/X86/X86MemFoldTables.inc /scratch/powerllvm/powerllvm_env/aix-ppc64/clang-ppc64-aix/build/test/TableGen/Output/x86-auto-memfold.td.tmp1
cmp: illegal option -- -
usage: cmp [-l | -s] file1 file2

@abhina.sreeskantharajan
seems "--ignore-initial=0:568" doesn't support ppc64? will https://reviews.llvm.org/D146498 works for you?

[dblaikie]

llvm/test/TableGen/x86-auto-memfold.td

2

Could you update/fix this test to not depend on the real .td file - all the other tblgen tests include a small snippet/test case/example instead? (though the test was renamed in 35aeb321c005ed77ef5e5fb4f8dea69a81c81253)

[skan]

llvm/test/TableGen/x86-auto-memfold.td

2

@dblaikie Thank you for the suggestion! The test itself aims to expose the vulnerable rules in X86FoldTablesEmitter.cpp. Due to the complexity of X86ISA, even the folding rules are already complicated, it is hard to predict whether exceptions will occur when new ISAs are introduced. So unfortunately, we need the real .td file as input. I illustrated the usage of the test file in D147527

llvm/include/llvm/Support/X86FoldTablesUtils.h

-//===-- X86InstrFoldTables.h - X86 Instruction Folding Tables ---*- C++ -*-===//
+//===-- X86FoldTablesUtils.h ------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
-//
-// This file contains the interface to query the X86 memory folding tables.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H
-#define LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H
 
-#include <cstdint>
-
-namespace llvm {
+#ifndef LLVM_SUPPORT_X86FOLDTABLESUTILS_H
+#define LLVM_SUPPORT_X86FOLDTABLESUTILS_H
 
+namespace {
 enum {
   // Select which memory operand is being unfolded.
   // (stored in bits 0 - 2)
   TB_INDEX_0    = 0,
   TB_INDEX_1    = 1,
   TB_INDEX_2    = 2,
   TB_INDEX_3    = 3,
   TB_INDEX_4    = 4,
enum {
   TB_BCAST_D    =   0 << TB_BCAST_TYPE_SHIFT,
   TB_BCAST_Q    =   1 << TB_BCAST_TYPE_SHIFT,
   TB_BCAST_SS   =   2 << TB_BCAST_TYPE_SHIFT,
   TB_BCAST_SD   =   3 << TB_BCAST_TYPE_SHIFT,
   TB_BCAST_MASK = 0x3 << TB_BCAST_TYPE_SHIFT,
 
   // Unused bits 14-15
 };
-
-// This struct is used for both the folding and unfold tables. They KeyOp
-// is used to determine the sorting order.
-struct X86MemoryFoldTableEntry {
-  uint16_t KeyOp;
-  uint16_t DstOp;
-  uint16_t Flags;
-
-  bool operator<(const X86MemoryFoldTableEntry &RHS) const {
-    return KeyOp < RHS.KeyOp;
-  }
-  bool operator==(const X86MemoryFoldTableEntry &RHS) const {
-    return KeyOp == RHS.KeyOp;
-  }
-  friend bool operator<(const X86MemoryFoldTableEntry &TE, unsigned Opcode) {
-    return TE.KeyOp < Opcode;
-  }
-};
-
-// Look up the memory folding table entry for folding a load and a store into
-// operand 0.
-const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
-
-// Look up the memory folding table entry for folding a load or store with
-// operand OpNum.
-const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
-
-// Look up the memory unfolding table entry for this instruction.
-const X86MemoryFoldTableEntry *lookupUnfoldTable(unsigned MemOp);
-
-} // namespace llvm
-
-#endif
+#endif // LLVM_SUPPORT_X86FOLDTABLESUTILS_H

llvm/lib/Target/X86/X86InstrFoldTables.h

 //===-- X86InstrFoldTables.h - X86 Instruction Folding Tables ---*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the interface to query the X86 memory folding tables.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H
 #define LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H
 
 #include <cstdint>
+#include "llvm/Support/X86FoldTablesUtils.h"
 
 namespace llvm {
 
-enum {
-  // Select which memory operand is being unfolded.
-  // (stored in bits 0 - 2)
-  TB_INDEX_0    = 0,
-  TB_INDEX_1    = 1,
-  TB_INDEX_2    = 2,
-  TB_INDEX_3    = 3,
-  TB_INDEX_4    = 4,
-  TB_INDEX_MASK = 0x7,
-
-  // Do not insert the reverse map (MemOp -> RegOp) into the table.
-  // This may be needed because there is a many -> one mapping.
-  TB_NO_REVERSE   = 1 << 3,
-
-  // Do not insert the forward map (RegOp -> MemOp) into the table.
-  // This is needed for Native Client, which prohibits branch
-  // instructions from using a memory operand.
-  TB_NO_FORWARD   = 1 << 4,
-
-  TB_FOLDED_LOAD  = 1 << 5,
-  TB_FOLDED_STORE = 1 << 6,
-  TB_FOLDED_BCAST = 1 << 7,
-
-  // Minimum alignment required for load/store.
-  // Used for RegOp->MemOp conversion. Encoded as Log2(Align) + 1 to allow 0
-  // to mean align of 0.
-  // (stored in bits 8 - 11)
-  TB_ALIGN_SHIFT = 8,
-  TB_ALIGN_NONE  =   0 << TB_ALIGN_SHIFT,
-  TB_ALIGN_16    =   5 << TB_ALIGN_SHIFT,
-  TB_ALIGN_32    =   6 << TB_ALIGN_SHIFT,
-  TB_ALIGN_64    =   7 << TB_ALIGN_SHIFT,
-  TB_ALIGN_MASK  = 0xf << TB_ALIGN_SHIFT,
-
-  // Broadcast type.
-  // (stored in bits 12 - 13)
-  TB_BCAST_TYPE_SHIFT = 12,
-  TB_BCAST_D    =   0 << TB_BCAST_TYPE_SHIFT,
-  TB_BCAST_Q    =   1 << TB_BCAST_TYPE_SHIFT,
-  TB_BCAST_SS   =   2 << TB_BCAST_TYPE_SHIFT,
-  TB_BCAST_SD   =   3 << TB_BCAST_TYPE_SHIFT,
-  TB_BCAST_MASK = 0x3 << TB_BCAST_TYPE_SHIFT,
-
-  // Unused bits 14-15
-};
-
 // This struct is used for both the folding and unfold tables. They KeyOp
 // is used to determine the sorting order.
 struct X86MemoryFoldTableEntry {
   uint16_t KeyOp;
   uint16_t DstOp;
   uint16_t Flags;
 
   bool operator<(const X86MemoryFoldTableEntry &RHS) const {

llvm/lib/Target/X86/X86MemFoldTables.inc

static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
   {X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD},
   {X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD},
   {X86::JMP16r, X86::JMP16m, TB_FOLDED_LOAD},
   {X86::JMP16r_NT, X86::JMP16m_NT, TB_FOLDED_LOAD},
   {X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD},
   {X86::JMP32r_NT, X86::JMP32m_NT, TB_FOLDED_LOAD},
   {X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD},
   {X86::JMP64r_NT, X86::JMP64m_NT, TB_FOLDED_LOAD},
+  {X86::JMP64r_REX, X86::JMP64m_REX, TB_FOLDED_LOAD},
   {X86::MMX_MOVD64from64rr, X86::MMX_MOVQ64mr, TB_FOLDED_STORE},
   {X86::MMX_MOVD64grr, X86::MMX_MOVD64mr, TB_FOLDED_STORE},
   {X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE},
-  {X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE},
+  {X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE},
-  {X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE},
+  {X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE},
-  {X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE},
+  {X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOV64toSDrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE},
-  {X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE},
-  {X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE},
-  {X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE|TB_ALIGN_16},
+  {X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
   {X86::MOVDI2SSrr, X86::MOV32mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE|TB_ALIGN_16},
   {X86::MOVDQUrr, X86::MOVDQUmr, TB_FOLDED_STORE},
   {X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE},
   {X86::MOVPQIto64rr, X86::MOVPQI2QImr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOVSDto64rr, X86::MOVSDmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MOVSS2DIrr, X86::MOVSSmr, TB_FOLDED_STORE},
-  {X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE},
-  {X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE},
+  {X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD},
   {X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD},
   {X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD},
   {X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD},
   {X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE},
   {X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE},
   {X86::PTWRITE64r, X86::PTWRITE64m, TB_FOLDED_LOAD},
   {X86::PTWRITEr, X86::PTWRITEm, TB_FOLDED_LOAD},
static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
   {X86::VEXTRACTI32x8Zrr, X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE},
   {X86::VEXTRACTI64x2Z256rr, X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE},
   {X86::VEXTRACTI64x2Zrr, X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE},
   {X86::VEXTRACTI64x4Zrr, X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE},
   {X86::VEXTRACTPSZrr, X86::VEXTRACTPSZmr, TB_FOLDED_STORE},
   {X86::VEXTRACTPSrr, X86::VEXTRACTPSmr, TB_FOLDED_STORE},
   {X86::VMOV64toSDZrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOV64toSDrr, X86::MOV64mr, TB_FOLDED_STORE|TB_NO_REVERSE},
-  {X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE|TB_ALIGN_64},
-  {X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE|TB_ALIGN_64},
-  {X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE|TB_ALIGN_16},
+  {X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_64},
+  {X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_64},
+  {X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
   {X86::VMOVDI2SSZrr, X86::MOV32mr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVDI2SSrr, X86::MOV32mr, TB_FOLDED_STORE|TB_NO_REVERSE},
-  {X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE|TB_ALIGN_64},
-  {X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE|TB_ALIGN_32},
-  {X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE|TB_ALIGN_64},
+  {X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_64},
+  {X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_16},
+  {X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_32},
+  {X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE|TB_NO_REVERSE|TB_ALIGN_64},
   {X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE|TB_ALIGN_32},
   {X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE|TB_ALIGN_16},
-  {X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE},
-  {X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE},
-  {X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE},
-  {X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE},
-  {X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE},
+  {X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVDQUYrr, X86::VMOVDQUYmr, TB_FOLDED_STORE},
   {X86::VMOVDQUrr, X86::VMOVDQUmr, TB_FOLDED_STORE},
   {X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE},
   {X86::VMOVPDI2DIrr, X86::VMOVPDI2DImr, TB_FOLDED_STORE},
   {X86::VMOVPQIto64Zrr, X86::VMOVPQI2QIZmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVPQIto64rr, X86::VMOVPQI2QImr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVSDto64Zrr, X86::VMOVSDZmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVSDto64rr, X86::VMOVSDmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VMOVSS2DIZrr, X86::VMOVSSZmr, TB_FOLDED_STORE},
   {X86::VMOVSS2DIrr, X86::VMOVSSmr, TB_FOLDED_STORE},
-  {X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE},
-  {X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE},
-  {X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE},
-  {X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE},
-  {X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE},
-  {X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE},
-  {X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE},
-  {X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE},
-  {X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE},
-  {X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE},
+  {X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE|TB_NO_REVERSE},
+  {X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE|TB_NO_REVERSE},
   {X86::VPEXTRDZrr, X86::VPEXTRDZmr, TB_FOLDED_STORE},
   {X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE},
   {X86::VPEXTRQZrr, X86::VPEXTRQZmr, TB_FOLDED_STORE},
   {X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE},
   {X86::VPMOVDBZrr, X86::VPMOVDBZmr, TB_FOLDED_STORE},
   {X86::VPMOVDWZ256rr, X86::VPMOVDWZ256mr, TB_FOLDED_STORE},
   {X86::VPMOVDWZrr, X86::VPMOVDWZmr, TB_FOLDED_STORE},
   {X86::VPMOVQDZ256rr, X86::VPMOVQDZ256mr, TB_FOLDED_STORE},
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
   {X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0},
   {X86::CVTTSS2SIrr_Int, X86::CVTTSS2SIrm_Int, TB_NO_REVERSE},
   {X86::IMUL16rri, X86::IMUL16rmi, 0},
   {X86::IMUL16rri8, X86::IMUL16rmi8, 0},
   {X86::IMUL32rri, X86::IMUL32rmi, 0},
   {X86::IMUL32rri8, X86::IMUL32rmi8, 0},
   {X86::IMUL64rri32, X86::IMUL64rmi32, 0},
   {X86::IMUL64rri8, X86::IMUL64rmi8, 0},
+  {X86::KMOVBkk, X86::KMOVBkm, TB_NO_REVERSE},
+  {X86::KMOVDkk, X86::KMOVDkm, 0},
+  {X86::KMOVQkk, X86::KMOVQkm, 0},
+  {X86::KMOVWkk, X86::KMOVWkm, 0},
   {X86::LWPINS32rri, X86::LWPINS32rmi, 0},
   {X86::LWPINS64rri, X86::LWPINS64rmi, 0},
   {X86::LWPVAL32rri, X86::LWPVAL32rmi, 0},
   {X86::LWPVAL64rri, X86::LWPVAL64rmi, 0},
   {X86::LZCNT16rr, X86::LZCNT16rm, 0},
   {X86::LZCNT32rr, X86::LZCNT32rm, 0},
   {X86::LZCNT64rr, X86::LZCNT64rm, 0},
   {X86::MMX_CVTPD2PIrr, X86::MMX_CVTPD2PIrm, TB_ALIGN_16},
   {X86::MMX_CVTPI2PDrr, X86::MMX_CVTPI2PDrm, 0},
   {X86::MMX_CVTPS2PIrr, X86::MMX_CVTPS2PIrm, TB_NO_REVERSE},
   {X86::MMX_CVTTPD2PIrr, X86::MMX_CVTTPD2PIrm, TB_ALIGN_16},
   {X86::MMX_CVTTPS2PIrr, X86::MMX_CVTTPS2PIrm, TB_NO_REVERSE},
+  {X86::MMX_MOVD64rr, X86::MMX_MOVD64rm, 0},
   {X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0},
   {X86::MMX_PABSBrr, X86::MMX_PABSBrm, 0},
   {X86::MMX_PABSDrr, X86::MMX_PABSDrm, 0},
   {X86::MMX_PABSWrr, X86::MMX_PABSWrm, 0},
   {X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0},
   {X86::MOV16rr, X86::MOV16rm, 0},
   {X86::MOV32rr, X86::MOV32rm, 0},
   {X86::MOV64rr, X86::MOV64rm, 0},
   {X86::MOV64toPQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE},
   {X86::MOV64toSDrr, X86::MOVSDrm_alt, TB_NO_REVERSE},
   {X86::MOV8rr, X86::MOV8rm, 0},
   {X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16},
   {X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16},
   {X86::MOVDDUPrr, X86::MOVDDUPrm, TB_NO_REVERSE},
   {X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0},
   {X86::MOVDI2SSrr, X86::MOVSSrm_alt, 0},
   {X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16},
   {X86::MOVDQUrr, X86::MOVDQUrm, 0},
   {X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16},
   {X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16},
+  {X86::MOVSX16rr32, X86::MOVSX16rm32, 0},
   {X86::MOVSX16rr8, X86::MOVSX16rm8, 0},
   {X86::MOVSX32rr16, X86::MOVSX32rm16, 0},
+  {X86::MOVSX32rr32, X86::MOVSX32rm32, 0},
   {X86::MOVSX32rr8, X86::MOVSX32rm8, 0},
   {X86::MOVSX32rr8_NOREX, X86::MOVSX32rm8_NOREX, 0},
   {X86::MOVSX64rr16, X86::MOVSX64rm16, 0},
   {X86::MOVSX64rr32, X86::MOVSX64rm32, 0},
   {X86::MOVSX64rr8, X86::MOVSX64rm8, 0},
   {X86::MOVUPDrr, X86::MOVUPDrm, 0},
   {X86::MOVUPSrr, X86::MOVUPSrm, 0},
   {X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE},
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
   {X86::TZCNT32rr, X86::TZCNT32rm, 0},
   {X86::TZCNT64rr, X86::TZCNT64rm, 0},
   {X86::TZMSK32rr, X86::TZMSK32rm, 0},
   {X86::TZMSK64rr, X86::TZMSK64rm, 0},
   {X86::UCOMISDrr, X86::UCOMISDrm, 0},
   {X86::UCOMISDrr_Int, X86::UCOMISDrm_Int, TB_NO_REVERSE},
   {X86::UCOMISSrr, X86::UCOMISSrm, 0},
   {X86::UCOMISSrr_Int, X86::UCOMISSrm_Int, TB_NO_REVERSE},
   {X86::VAESIMCrr, X86::VAESIMCrm, 0},
   {X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0},
   {X86::VBROADCASTF32X2Z256rr, X86::VBROADCASTF32X2Z256rm, TB_NO_REVERSE},
   {X86::VBROADCASTF32X2Zrr, X86::VBROADCASTF32X2Zrm, TB_NO_REVERSE},
   {X86::VBROADCASTI32X2Z128rr, X86::VBROADCASTI32X2Z128rm, TB_NO_REVERSE},
   {X86::VBROADCASTI32X2Z256rr, X86::VBROADCASTI32X2Z256rm, TB_NO_REVERSE},
   {X86::VBROADCASTI32X2Zrr, X86::VBROADCASTI32X2Zrm, TB_NO_REVERSE},
   {X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE},
   {X86::VBROADCASTSDZ256rr, X86::VBROADCASTSDZ256rm, TB_NO_REVERSE},
   {X86::VBROADCASTSDZrr, X86::VBROADCASTSDZrm, TB_NO_REVERSE},
   {X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE},
   {X86::VBROADCASTSSZ128rr, X86::VBROADCASTSSZ128rm, TB_NO_REVERSE},
   {X86::VBROADCASTSSZ256rr, X86::VBROADCASTSSZ256rm, TB_NO_REVERSE},
   {X86::VBROADCASTSSZrr, X86::VBROADCASTSSZrm, TB_NO_REVERSE},
   {X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE},
   {X86::VCOMISDZrr, X86::VCOMISDZrm, 0},
   {X86::VCOMISDZrr_Int, X86::VCOMISDZrm_Int, TB_NO_REVERSE},
   {X86::VCOMISDrr, X86::VCOMISDrm, 0},
   {X86::VCOMISDrr_Int, X86::VCOMISDrm_Int, TB_NO_REVERSE},
+  {X86::VCOMISHZrr, X86::VCOMISHZrm, 0},
+  {X86::VCOMISHZrr_Int, X86::VCOMISHZrm_Int, TB_NO_REVERSE},
   {X86::VCOMISSZrr, X86::VCOMISSZrm, 0},
   {X86::VCOMISSZrr_Int, X86::VCOMISSZrm_Int, TB_NO_REVERSE},
   {X86::VCOMISSrr, X86::VCOMISSrm, 0},
   {X86::VCOMISSrr_Int, X86::VCOMISSrm_Int, TB_NO_REVERSE},
   {X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0},
   {X86::VCVTDQ2PDZ128rr, X86::VCVTDQ2PDZ128rm, TB_NO_REVERSE},
   {X86::VCVTDQ2PDZ256rr, X86::VCVTDQ2PDZ256rm, 0},
   {X86::VCVTDQ2PDZrr, X86::VCVTDQ2PDZrm, 0},
   {X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, TB_NO_REVERSE},
+  {X86::VCVTDQ2PHZ128rr, X86::VCVTDQ2PHZ128rm, 0},
+  {X86::VCVTDQ2PHZ256rr, X86::VCVTDQ2PHZ256rm, 0},
+  {X86::VCVTDQ2PHZrr, X86::VCVTDQ2PHZrm, 0},
   {X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0},
   {X86::VCVTDQ2PSZ128rr, X86::VCVTDQ2PSZ128rm, 0},
   {X86::VCVTDQ2PSZ256rr, X86::VCVTDQ2PSZ256rm, 0},
   {X86::VCVTDQ2PSZrr, X86::VCVTDQ2PSZrm, 0},
   {X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0},
+  {X86::VCVTNEPS2BF16Yrr, X86::VCVTNEPS2BF16Yrm, 0},
   {X86::VCVTNEPS2BF16Z128rr, X86::VCVTNEPS2BF16Z128rm, 0},
   {X86::VCVTNEPS2BF16Z256rr, X86::VCVTNEPS2BF16Z256rm, 0},
   {X86::VCVTNEPS2BF16Zrr, X86::VCVTNEPS2BF16Zrm, 0},
+  {X86::VCVTNEPS2BF16rr, X86::VCVTNEPS2BF16rm, 0},
   {X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0},
   {X86::VCVTPD2DQZ128rr, X86::VCVTPD2DQZ128rm, 0},
   {X86::VCVTPD2DQZ256rr, X86::VCVTPD2DQZ256rm, 0},
   {X86::VCVTPD2DQZrr, X86::VCVTPD2DQZrm, 0},
   {X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0},
+  {X86::VCVTPD2PHZ128rr, X86::VCVTPD2PHZ128rm, 0},
+  {X86::VCVTPD2PHZ256rr, X86::VCVTPD2PHZ256rm, 0},
+  {X86::VCVTPD2PHZrr, X86::VCVTPD2PHZrm, 0},
   {X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0},
   {X86::VCVTPD2PSZ128rr, X86::VCVTPD2PSZ128rm, 0},
   {X86::VCVTPD2PSZ256rr, X86::VCVTPD2PSZ256rm, 0},
   {X86::VCVTPD2PSZrr, X86::VCVTPD2PSZrm, 0},
   {X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0},
   {X86::VCVTPD2QQZ128rr, X86::VCVTPD2QQZ128rm, 0},
   {X86::VCVTPD2QQZ256rr, X86::VCVTPD2QQZ256rm, 0},
   {X86::VCVTPD2QQZrr, X86::VCVTPD2QQZrm, 0},
   {X86::VCVTPD2UDQZ128rr, X86::VCVTPD2UDQZ128rm, 0},
   {X86::VCVTPD2UDQZ256rr, X86::VCVTPD2UDQZ256rm, 0},
   {X86::VCVTPD2UDQZrr, X86::VCVTPD2UDQZrm, 0},
   {X86::VCVTPD2UQQZ128rr, X86::VCVTPD2UQQZ128rm, 0},
   {X86::VCVTPD2UQQZ256rr, X86::VCVTPD2UQQZ256rm, 0},
   {X86::VCVTPD2UQQZrr, X86::VCVTPD2UQQZrm, 0},
+  {X86::VCVTPH2DQZ128rr, X86::VCVTPH2DQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2DQZ256rr, X86::VCVTPH2DQZ256rm, 0},
+  {X86::VCVTPH2DQZrr, X86::VCVTPH2DQZrm, 0},
+  {X86::VCVTPH2PDZ128rr, X86::VCVTPH2PDZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZ256rr, X86::VCVTPH2PDZ256rm, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZrr, X86::VCVTPH2PDZrm, 0},
+  {X86::VCVTPH2PSXZ128rr, X86::VCVTPH2PSXZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2PSXZ256rr, X86::VCVTPH2PSXZ256rm, 0},
+  {X86::VCVTPH2PSXZrr, X86::VCVTPH2PSXZrm, 0},
   {X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0},
   {X86::VCVTPH2PSZ128rr, X86::VCVTPH2PSZ128rm, TB_NO_REVERSE},
   {X86::VCVTPH2PSZ256rr, X86::VCVTPH2PSZ256rm, 0},
   {X86::VCVTPH2PSZrr, X86::VCVTPH2PSZrm, 0},
   {X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZ128rr, X86::VCVTPH2QQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZ256rr, X86::VCVTPH2QQZ256rm, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZrr, X86::VCVTPH2QQZrm, 0},
+  {X86::VCVTPH2UDQZ128rr, X86::VCVTPH2UDQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2UDQZ256rr, X86::VCVTPH2UDQZ256rm, 0},
+  {X86::VCVTPH2UDQZrr, X86::VCVTPH2UDQZrm, 0},
+  {X86::VCVTPH2UQQZ128rr, X86::VCVTPH2UQQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZ256rr, X86::VCVTPH2UQQZ256rm, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZrr, X86::VCVTPH2UQQZrm, 0},
+  {X86::VCVTPH2UWZ128rr, X86::VCVTPH2UWZ128rm, 0},
+  {X86::VCVTPH2UWZ256rr, X86::VCVTPH2UWZ256rm, 0},
+  {X86::VCVTPH2UWZrr, X86::VCVTPH2UWZrm, 0},
+  {X86::VCVTPH2WZ128rr, X86::VCVTPH2WZ128rm, 0},
+  {X86::VCVTPH2WZ256rr, X86::VCVTPH2WZ256rm, 0},
+  {X86::VCVTPH2WZrr, X86::VCVTPH2WZrm, 0},
   {X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0},
   {X86::VCVTPS2DQZ128rr, X86::VCVTPS2DQZ128rm, 0},
   {X86::VCVTPS2DQZ256rr, X86::VCVTPS2DQZ256rm, 0},
   {X86::VCVTPS2DQZrr, X86::VCVTPS2DQZrm, 0},
   {X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0},
   {X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0},
   {X86::VCVTPS2PDZ128rr, X86::VCVTPS2PDZ128rm, TB_NO_REVERSE},
   {X86::VCVTPS2PDZ256rr, X86::VCVTPS2PDZ256rm, 0},
   {X86::VCVTPS2PDZrr, X86::VCVTPS2PDZrm, 0},
   {X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, TB_NO_REVERSE},
+  {X86::VCVTPS2PHXZ128rr, X86::VCVTPS2PHXZ128rm, 0},
+  {X86::VCVTPS2PHXZ256rr, X86::VCVTPS2PHXZ256rm, 0},
+  {X86::VCVTPS2PHXZrr, X86::VCVTPS2PHXZrm, 0},
   {X86::VCVTPS2QQZ128rr, X86::VCVTPS2QQZ128rm, TB_NO_REVERSE},
   {X86::VCVTPS2QQZ256rr, X86::VCVTPS2QQZ256rm, 0},
   {X86::VCVTPS2QQZrr, X86::VCVTPS2QQZrm, 0},
   {X86::VCVTPS2UDQZ128rr, X86::VCVTPS2UDQZ128rm, 0},
   {X86::VCVTPS2UDQZ256rr, X86::VCVTPS2UDQZ256rm, 0},
   {X86::VCVTPS2UDQZrr, X86::VCVTPS2UDQZrm, 0},
   {X86::VCVTPS2UQQZ128rr, X86::VCVTPS2UQQZ128rm, TB_NO_REVERSE},
   {X86::VCVTPS2UQQZ256rr, X86::VCVTPS2UQQZ256rm, 0},
   {X86::VCVTPS2UQQZrr, X86::VCVTPS2UQQZrm, 0},
   {X86::VCVTQQ2PDZ128rr, X86::VCVTQQ2PDZ128rm, 0},
   {X86::VCVTQQ2PDZ256rr, X86::VCVTQQ2PDZ256rm, 0},
   {X86::VCVTQQ2PDZrr, X86::VCVTQQ2PDZrm, 0},
+  {X86::VCVTQQ2PHZ128rr, X86::VCVTQQ2PHZ128rm, 0},
+  {X86::VCVTQQ2PHZ256rr, X86::VCVTQQ2PHZ256rm, 0},
+  {X86::VCVTQQ2PHZrr, X86::VCVTQQ2PHZrm, 0},
   {X86::VCVTQQ2PSZ128rr, X86::VCVTQQ2PSZ128rm, 0},
   {X86::VCVTQQ2PSZ256rr, X86::VCVTQQ2PSZ256rm, 0},
   {X86::VCVTQQ2PSZrr, X86::VCVTQQ2PSZrm, 0},
   {X86::VCVTSD2SI64Zrr, X86::VCVTSD2SI64Zrm, 0},
   {X86::VCVTSD2SI64Zrr_Int, X86::VCVTSD2SI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0},
   {X86::VCVTSD2SI64rr_Int, X86::VCVTSD2SI64rm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2SIZrr, X86::VCVTSD2SIZrm, 0},
   {X86::VCVTSD2SIZrr_Int, X86::VCVTSD2SIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0},
   {X86::VCVTSD2SIrr_Int, X86::VCVTSD2SIrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2USI64Zrr_Int, X86::VCVTSD2USI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2USIZrr_Int, X86::VCVTSD2USIZrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2SI64Zrr_Int, X86::VCVTSH2SI64Zrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2SIZrr_Int, X86::VCVTSH2SIZrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2USI64Zrr_Int, X86::VCVTSH2USI64Zrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2USIZrr_Int, X86::VCVTSH2USIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2SI64Zrr, X86::VCVTSS2SI64Zrm, 0},
   {X86::VCVTSS2SI64Zrr_Int, X86::VCVTSS2SI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0},
   {X86::VCVTSS2SI64rr_Int, X86::VCVTSS2SI64rm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2SIZrr, X86::VCVTSS2SIZrm, 0},
   {X86::VCVTSS2SIZrr_Int, X86::VCVTSS2SIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0},
   {X86::VCVTSS2SIrr_Int, X86::VCVTSS2SIrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2USI64Zrr_Int, X86::VCVTSS2USI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2USIZrr_Int, X86::VCVTSS2USIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0},
   {X86::VCVTTPD2DQZ128rr, X86::VCVTTPD2DQZ128rm, 0},
   {X86::VCVTTPD2DQZ256rr, X86::VCVTTPD2DQZ256rm, 0},
   {X86::VCVTTPD2DQZrr, X86::VCVTTPD2DQZrm, 0},
   {X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0},
   {X86::VCVTTPD2QQZ128rr, X86::VCVTTPD2QQZ128rm, 0},
   {X86::VCVTTPD2QQZ256rr, X86::VCVTTPD2QQZ256rm, 0},
   {X86::VCVTTPD2QQZrr, X86::VCVTTPD2QQZrm, 0},
   {X86::VCVTTPD2UDQZ128rr, X86::VCVTTPD2UDQZ128rm, 0},
   {X86::VCVTTPD2UDQZ256rr, X86::VCVTTPD2UDQZ256rm, 0},
   {X86::VCVTTPD2UDQZrr, X86::VCVTTPD2UDQZrm, 0},
   {X86::VCVTTPD2UQQZ128rr, X86::VCVTTPD2UQQZ128rm, 0},
   {X86::VCVTTPD2UQQZ256rr, X86::VCVTTPD2UQQZ256rm, 0},
   {X86::VCVTTPD2UQQZrr, X86::VCVTTPD2UQQZrm, 0},
+  {X86::VCVTTPH2DQZ128rr, X86::VCVTTPH2DQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2DQZ256rr, X86::VCVTTPH2DQZ256rm, 0},
+  {X86::VCVTTPH2DQZrr, X86::VCVTTPH2DQZrm, 0},
+  {X86::VCVTTPH2QQZ128rr, X86::VCVTTPH2QQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZ256rr, X86::VCVTTPH2QQZ256rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZrr, X86::VCVTTPH2QQZrm, 0},
+  {X86::VCVTTPH2UDQZ128rr, X86::VCVTTPH2UDQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2UDQZ256rr, X86::VCVTTPH2UDQZ256rm, 0},
+  {X86::VCVTTPH2UDQZrr, X86::VCVTTPH2UDQZrm, 0},
+  {X86::VCVTTPH2UQQZ128rr, X86::VCVTTPH2UQQZ128rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZ256rr, X86::VCVTTPH2UQQZ256rm, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZrr, X86::VCVTTPH2UQQZrm, 0},
+  {X86::VCVTTPH2UWZ128rr, X86::VCVTTPH2UWZ128rm, 0},
+  {X86::VCVTTPH2UWZ256rr, X86::VCVTTPH2UWZ256rm, 0},
+  {X86::VCVTTPH2UWZrr, X86::VCVTTPH2UWZrm, 0},
+  {X86::VCVTTPH2WZ128rr, X86::VCVTTPH2WZ128rm, 0},
+  {X86::VCVTTPH2WZ256rr, X86::VCVTTPH2WZ256rm, 0},
+  {X86::VCVTTPH2WZrr, X86::VCVTTPH2WZrm, 0},
   {X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0},
   {X86::VCVTTPS2DQZ128rr, X86::VCVTTPS2DQZ128rm, 0},
   {X86::VCVTTPS2DQZ256rr, X86::VCVTTPS2DQZ256rm, 0},
   {X86::VCVTTPS2DQZrr, X86::VCVTTPS2DQZrm, 0},
   {X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0},
   {X86::VCVTTPS2QQZ128rr, X86::VCVTTPS2QQZ128rm, TB_NO_REVERSE},
   {X86::VCVTTPS2QQZ256rr, X86::VCVTTPS2QQZ256rm, 0},
   {X86::VCVTTPS2QQZrr, X86::VCVTTPS2QQZrm, 0},
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
   {X86::VCVTTSD2SIZrr, X86::VCVTTSD2SIZrm, 0},
   {X86::VCVTTSD2SIZrr_Int, X86::VCVTTSD2SIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0},
   {X86::VCVTTSD2SIrr_Int, X86::VCVTTSD2SIrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSD2USI64Zrr, X86::VCVTTSD2USI64Zrm, 0},
   {X86::VCVTTSD2USI64Zrr_Int, X86::VCVTTSD2USI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSD2USIZrr, X86::VCVTTSD2USIZrm, 0},
   {X86::VCVTTSD2USIZrr_Int, X86::VCVTTSD2USIZrm_Int, TB_NO_REVERSE},
+  {X86::VCVTTSH2SI64Zrr, X86::VCVTTSH2SI64Zrm, 0},
+  {X86::VCVTTSH2SI64Zrr_Int, X86::VCVTTSH2SI64Zrm_Int, TB_NO_REVERSE},
+  {X86::VCVTTSH2SIZrr, X86::VCVTTSH2SIZrm, 0},
+  {X86::VCVTTSH2SIZrr_Int, X86::VCVTTSH2SIZrm_Int, TB_NO_REVERSE},
+  {X86::VCVTTSH2USI64Zrr, X86::VCVTTSH2USI64Zrm, 0},
+  {X86::VCVTTSH2USI64Zrr_Int, X86::VCVTTSH2USI64Zrm_Int, TB_NO_REVERSE},
+  {X86::VCVTTSH2USIZrr, X86::VCVTTSH2USIZrm, 0},
+  {X86::VCVTTSH2USIZrr_Int, X86::VCVTTSH2USIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2SI64Zrr, X86::VCVTTSS2SI64Zrm, 0},
   {X86::VCVTTSS2SI64Zrr_Int, X86::VCVTTSS2SI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0},
   {X86::VCVTTSS2SI64rr_Int, X86::VCVTTSS2SI64rm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2SIZrr, X86::VCVTTSS2SIZrm, 0},
   {X86::VCVTTSS2SIZrr_Int, X86::VCVTTSS2SIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0},
   {X86::VCVTTSS2SIrr_Int, X86::VCVTTSS2SIrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2USI64Zrr, X86::VCVTTSS2USI64Zrm, 0},
   {X86::VCVTTSS2USI64Zrr_Int, X86::VCVTTSS2USI64Zrm_Int, TB_NO_REVERSE},
   {X86::VCVTTSS2USIZrr, X86::VCVTTSS2USIZrm, 0},
   {X86::VCVTTSS2USIZrr_Int, X86::VCVTTSS2USIZrm_Int, TB_NO_REVERSE},
   {X86::VCVTUDQ2PDZ128rr, X86::VCVTUDQ2PDZ128rm, TB_NO_REVERSE},
   {X86::VCVTUDQ2PDZ256rr, X86::VCVTUDQ2PDZ256rm, 0},
   {X86::VCVTUDQ2PDZrr, X86::VCVTUDQ2PDZrm, 0},
+  {X86::VCVTUDQ2PHZ128rr, X86::VCVTUDQ2PHZ128rm, 0},
+  {X86::VCVTUDQ2PHZ256rr, X86::VCVTUDQ2PHZ256rm, 0},
+  {X86::VCVTUDQ2PHZrr, X86::VCVTUDQ2PHZrm, 0},
   {X86::VCVTUDQ2PSZ128rr, X86::VCVTUDQ2PSZ128rm, 0},
   {X86::VCVTUDQ2PSZ256rr, X86::VCVTUDQ2PSZ256rm, 0},
   {X86::VCVTUDQ2PSZrr, X86::VCVTUDQ2PSZrm, 0},
   {X86::VCVTUQQ2PDZ128rr, X86::VCVTUQQ2PDZ128rm, 0},
   {X86::VCVTUQQ2PDZ256rr, X86::VCVTUQQ2PDZ256rm, 0},
   {X86::VCVTUQQ2PDZrr, X86::VCVTUQQ2PDZrm, 0},
+  {X86::VCVTUQQ2PHZ128rr, X86::VCVTUQQ2PHZ128rm, 0},
+  {X86::VCVTUQQ2PHZ256rr, X86::VCVTUQQ2PHZ256rm, 0},
+  {X86::VCVTUQQ2PHZrr, X86::VCVTUQQ2PHZrm, 0},
   {X86::VCVTUQQ2PSZ128rr, X86::VCVTUQQ2PSZ128rm, 0},
   {X86::VCVTUQQ2PSZ256rr, X86::VCVTUQQ2PSZ256rm, 0},
   {X86::VCVTUQQ2PSZrr, X86::VCVTUQQ2PSZrm, 0},
+  {X86::VCVTUW2PHZ128rr, X86::VCVTUW2PHZ128rm, 0},
+  {X86::VCVTUW2PHZ256rr, X86::VCVTUW2PHZ256rm, 0},
+  {X86::VCVTUW2PHZrr, X86::VCVTUW2PHZrm, 0},
+  {X86::VCVTW2PHZ128rr, X86::VCVTW2PHZ128rm, 0},
+  {X86::VCVTW2PHZ256rr, X86::VCVTW2PHZ256rm, 0},
+  {X86::VCVTW2PHZrr, X86::VCVTW2PHZrm, 0},
   {X86::VEXP2PDZr, X86::VEXP2PDZm, 0},
   {X86::VEXP2PSZr, X86::VEXP2PSZm, 0},
   {X86::VEXPANDPDZ128rr, X86::VEXPANDPDZ128rm, TB_NO_REVERSE},
   {X86::VEXPANDPDZ256rr, X86::VEXPANDPDZ256rm, TB_NO_REVERSE},
   {X86::VEXPANDPDZrr, X86::VEXPANDPDZrm, TB_NO_REVERSE},
   {X86::VEXPANDPSZ128rr, X86::VEXPANDPSZ128rm, TB_NO_REVERSE},
   {X86::VEXPANDPSZ256rr, X86::VEXPANDPSZ256rm, TB_NO_REVERSE},
   {X86::VEXPANDPSZrr, X86::VEXPANDPSZrm, TB_NO_REVERSE},
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
   {X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0},
   {X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0},
   {X86::VMOVUPDrr, X86::VMOVUPDrm, 0},
   {X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0},
   {X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0},
   {X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0},
   {X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0},
   {X86::VMOVUPSrr, X86::VMOVUPSrm, 0},
+  {X86::VMOVW2SHrr, X86::VMOVWrm, TB_NO_REVERSE},
   {X86::VMOVZPQILo2PQIZrr, X86::VMOVQI2PQIZrm, TB_NO_REVERSE},
   {X86::VMOVZPQILo2PQIrr, X86::VMOVQI2PQIrm, TB_NO_REVERSE},
   {X86::VPABSBYrr, X86::VPABSBYrm, 0},
   {X86::VPABSBZ128rr, X86::VPABSBZ128rm, 0},
   {X86::VPABSBZ256rr, X86::VPABSBZ256rm, 0},
   {X86::VPABSBZrr, X86::VPABSBZrm, 0},
   {X86::VPABSBrr, X86::VPABSBrm, 0},
   {X86::VPABSDYrr, X86::VPABSDYrm, 0},
static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
   {X86::VTESTPDYrr, X86::VTESTPDYrm, 0},
   {X86::VTESTPDrr, X86::VTESTPDrm, 0},
   {X86::VTESTPSYrr, X86::VTESTPSYrm, 0},
   {X86::VTESTPSrr, X86::VTESTPSrm, 0},
   {X86::VUCOMISDZrr, X86::VUCOMISDZrm, 0},
   {X86::VUCOMISDZrr_Int, X86::VUCOMISDZrm_Int, TB_NO_REVERSE},
   {X86::VUCOMISDrr, X86::VUCOMISDrm, 0},
   {X86::VUCOMISDrr_Int, X86::VUCOMISDrm_Int, TB_NO_REVERSE},
+  {X86::VUCOMISHZrr, X86::VUCOMISHZrm, 0},
+  {X86::VUCOMISHZrr_Int, X86::VUCOMISHZrm_Int, TB_NO_REVERSE},
   {X86::VUCOMISSZrr, X86::VUCOMISSZrm, 0},
   {X86::VUCOMISSZrr_Int, X86::VUCOMISSZrm_Int, TB_NO_REVERSE},
   {X86::VUCOMISSrr, X86::VUCOMISSrm, 0},
   {X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE},
 };
 
 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
   {X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE},
static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
   {X86::VCMPSHZrr_Int, X86::VCMPSHZrm_Int, TB_NO_REVERSE},
   {X86::VCMPSSZrr, X86::VCMPSSZrm, 0},
   {X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, TB_NO_REVERSE},
   {X86::VCMPSSrr, X86::VCMPSSrm, 0},
   {X86::VCMPSSrr_Int, X86::VCMPSSrm_Int, TB_NO_REVERSE},
   {X86::VCVTDQ2PDZ128rrkz, X86::VCVTDQ2PDZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTDQ2PDZ256rrkz, X86::VCVTDQ2PDZ256rmkz, 0},
   {X86::VCVTDQ2PDZrrkz, X86::VCVTDQ2PDZrmkz, 0},
+  {X86::VCVTDQ2PHZ128rrkz, X86::VCVTDQ2PHZ128rmkz, 0},
+  {X86::VCVTDQ2PHZ256rrkz, X86::VCVTDQ2PHZ256rmkz, 0},
+  {X86::VCVTDQ2PHZrrkz, X86::VCVTDQ2PHZrmkz, 0},
   {X86::VCVTDQ2PSZ128rrkz, X86::VCVTDQ2PSZ128rmkz, 0},
   {X86::VCVTDQ2PSZ256rrkz, X86::VCVTDQ2PSZ256rmkz, 0},
   {X86::VCVTDQ2PSZrrkz, X86::VCVTDQ2PSZrmkz, 0},
   {X86::VCVTNE2PS2BF16Z128rr, X86::VCVTNE2PS2BF16Z128rm, 0},
   {X86::VCVTNE2PS2BF16Z256rr, X86::VCVTNE2PS2BF16Z256rm, 0},
   {X86::VCVTNE2PS2BF16Zrr, X86::VCVTNE2PS2BF16Zrm, 0},
   {X86::VCVTNEPS2BF16Z128rrkz, X86::VCVTNEPS2BF16Z128rmkz, 0},
   {X86::VCVTNEPS2BF16Z256rrkz, X86::VCVTNEPS2BF16Z256rmkz, 0},
   {X86::VCVTNEPS2BF16Zrrkz, X86::VCVTNEPS2BF16Zrmkz, 0},
   {X86::VCVTPD2DQZ128rrkz, X86::VCVTPD2DQZ128rmkz, 0},
   {X86::VCVTPD2DQZ256rrkz, X86::VCVTPD2DQZ256rmkz, 0},
   {X86::VCVTPD2DQZrrkz, X86::VCVTPD2DQZrmkz, 0},
+  {X86::VCVTPD2PHZ128rrkz, X86::VCVTPD2PHZ128rmkz, 0},
+  {X86::VCVTPD2PHZ256rrkz, X86::VCVTPD2PHZ256rmkz, 0},
+  {X86::VCVTPD2PHZrrkz, X86::VCVTPD2PHZrmkz, 0},
   {X86::VCVTPD2PSZ128rrkz, X86::VCVTPD2PSZ128rmkz, 0},
   {X86::VCVTPD2PSZ256rrkz, X86::VCVTPD2PSZ256rmkz, 0},
   {X86::VCVTPD2PSZrrkz, X86::VCVTPD2PSZrmkz, 0},
   {X86::VCVTPD2QQZ128rrkz, X86::VCVTPD2QQZ128rmkz, 0},
   {X86::VCVTPD2QQZ256rrkz, X86::VCVTPD2QQZ256rmkz, 0},
   {X86::VCVTPD2QQZrrkz, X86::VCVTPD2QQZrmkz, 0},
   {X86::VCVTPD2UDQZ128rrkz, X86::VCVTPD2UDQZ128rmkz, 0},
   {X86::VCVTPD2UDQZ256rrkz, X86::VCVTPD2UDQZ256rmkz, 0},
   {X86::VCVTPD2UDQZrrkz, X86::VCVTPD2UDQZrmkz, 0},
   {X86::VCVTPD2UQQZ128rrkz, X86::VCVTPD2UQQZ128rmkz, 0},
   {X86::VCVTPD2UQQZ256rrkz, X86::VCVTPD2UQQZ256rmkz, 0},
   {X86::VCVTPD2UQQZrrkz, X86::VCVTPD2UQQZrmkz, 0},
+  {X86::VCVTPH2DQZ128rrkz, X86::VCVTPH2DQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2DQZ256rrkz, X86::VCVTPH2DQZ256rmkz, 0},
+  {X86::VCVTPH2DQZrrkz, X86::VCVTPH2DQZrmkz, 0},
+  {X86::VCVTPH2PDZ128rrkz, X86::VCVTPH2PDZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZ256rrkz, X86::VCVTPH2PDZ256rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZrrkz, X86::VCVTPH2PDZrmkz, 0},
+  {X86::VCVTPH2PSXZ128rrkz, X86::VCVTPH2PSXZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2PSXZ256rrkz, X86::VCVTPH2PSXZ256rmkz, 0},
+  {X86::VCVTPH2PSXZrrkz, X86::VCVTPH2PSXZrmkz, 0},
   {X86::VCVTPH2PSZ128rrkz, X86::VCVTPH2PSZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTPH2PSZ256rrkz, X86::VCVTPH2PSZ256rmkz, 0},
   {X86::VCVTPH2PSZrrkz, X86::VCVTPH2PSZrmkz, 0},
+  {X86::VCVTPH2QQZ128rrkz, X86::VCVTPH2QQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZ256rrkz, X86::VCVTPH2QQZ256rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZrrkz, X86::VCVTPH2QQZrmkz, 0},
+  {X86::VCVTPH2UDQZ128rrkz, X86::VCVTPH2UDQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2UDQZ256rrkz, X86::VCVTPH2UDQZ256rmkz, 0},
+  {X86::VCVTPH2UDQZrrkz, X86::VCVTPH2UDQZrmkz, 0},
+  {X86::VCVTPH2UQQZ128rrkz, X86::VCVTPH2UQQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZ256rrkz, X86::VCVTPH2UQQZ256rmkz, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZrrkz, X86::VCVTPH2UQQZrmkz, 0},
+  {X86::VCVTPH2UWZ128rrkz, X86::VCVTPH2UWZ128rmkz, 0},
+  {X86::VCVTPH2UWZ256rrkz, X86::VCVTPH2UWZ256rmkz, 0},
+  {X86::VCVTPH2UWZrrkz, X86::VCVTPH2UWZrmkz, 0},
+  {X86::VCVTPH2WZ128rrkz, X86::VCVTPH2WZ128rmkz, 0},
+  {X86::VCVTPH2WZ256rrkz, X86::VCVTPH2WZ256rmkz, 0},
+  {X86::VCVTPH2WZrrkz, X86::VCVTPH2WZrmkz, 0},
   {X86::VCVTPS2DQZ128rrkz, X86::VCVTPS2DQZ128rmkz, 0},
   {X86::VCVTPS2DQZ256rrkz, X86::VCVTPS2DQZ256rmkz, 0},
   {X86::VCVTPS2DQZrrkz, X86::VCVTPS2DQZrmkz, 0},
   {X86::VCVTPS2PDZ128rrkz, X86::VCVTPS2PDZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTPS2PDZ256rrkz, X86::VCVTPS2PDZ256rmkz, 0},
   {X86::VCVTPS2PDZrrkz, X86::VCVTPS2PDZrmkz, 0},
+  {X86::VCVTPS2PHXZ128rrkz, X86::VCVTPS2PHXZ128rmkz, 0},
+  {X86::VCVTPS2PHXZ256rrkz, X86::VCVTPS2PHXZ256rmkz, 0},
+  {X86::VCVTPS2PHXZrrkz, X86::VCVTPS2PHXZrmkz, 0},
   {X86::VCVTPS2QQZ128rrkz, X86::VCVTPS2QQZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTPS2QQZ256rrkz, X86::VCVTPS2QQZ256rmkz, 0},
   {X86::VCVTPS2QQZrrkz, X86::VCVTPS2QQZrmkz, 0},
   {X86::VCVTPS2UDQZ128rrkz, X86::VCVTPS2UDQZ128rmkz, 0},
   {X86::VCVTPS2UDQZ256rrkz, X86::VCVTPS2UDQZ256rmkz, 0},
   {X86::VCVTPS2UDQZrrkz, X86::VCVTPS2UDQZrmkz, 0},
   {X86::VCVTPS2UQQZ128rrkz, X86::VCVTPS2UQQZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTPS2UQQZ256rrkz, X86::VCVTPS2UQQZ256rmkz, 0},
   {X86::VCVTPS2UQQZrrkz, X86::VCVTPS2UQQZrmkz, 0},
   {X86::VCVTQQ2PDZ128rrkz, X86::VCVTQQ2PDZ128rmkz, 0},
   {X86::VCVTQQ2PDZ256rrkz, X86::VCVTQQ2PDZ256rmkz, 0},
   {X86::VCVTQQ2PDZrrkz, X86::VCVTQQ2PDZrmkz, 0},
+  {X86::VCVTQQ2PHZ128rrkz, X86::VCVTQQ2PHZ128rmkz, 0},
+  {X86::VCVTQQ2PHZ256rrkz, X86::VCVTQQ2PHZ256rmkz, 0},
+  {X86::VCVTQQ2PHZrrkz, X86::VCVTQQ2PHZrmkz, 0},
   {X86::VCVTQQ2PSZ128rrkz, X86::VCVTQQ2PSZ128rmkz, 0},
   {X86::VCVTQQ2PSZ256rrkz, X86::VCVTQQ2PSZ256rmkz, 0},
   {X86::VCVTQQ2PSZrrkz, X86::VCVTQQ2PSZrmkz, 0},
+  {X86::VCVTSD2SHZrr, X86::VCVTSD2SHZrm, 0},
+  {X86::VCVTSD2SHZrr_Int, X86::VCVTSD2SHZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2SSZrr, X86::VCVTSD2SSZrm, 0},
   {X86::VCVTSD2SSZrr_Int, X86::VCVTSD2SSZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0},
   {X86::VCVTSD2SSrr_Int, X86::VCVTSD2SSrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2SDZrr, X86::VCVTSH2SDZrm, 0},
+  {X86::VCVTSH2SDZrr_Int, X86::VCVTSH2SDZrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSH2SSZrr, X86::VCVTSH2SSZrm, 0},
+  {X86::VCVTSH2SSZrr_Int, X86::VCVTSH2SSZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSI2SDZrr, X86::VCVTSI2SDZrm, 0},
   {X86::VCVTSI2SDZrr_Int, X86::VCVTSI2SDZrm_Int, 0},
   {X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0},
   {X86::VCVTSI2SDrr_Int, X86::VCVTSI2SDrm_Int, 0},
+  {X86::VCVTSI2SHZrr, X86::VCVTSI2SHZrm, 0},
+  {X86::VCVTSI2SHZrr_Int, X86::VCVTSI2SHZrm_Int, 0},
   {X86::VCVTSI2SSZrr, X86::VCVTSI2SSZrm, 0},
   {X86::VCVTSI2SSZrr_Int, X86::VCVTSI2SSZrm_Int, 0},
   {X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0},
   {X86::VCVTSI2SSrr_Int, X86::VCVTSI2SSrm_Int, 0},
   {X86::VCVTSI642SDZrr, X86::VCVTSI642SDZrm, 0},
   {X86::VCVTSI642SDZrr_Int, X86::VCVTSI642SDZrm_Int, 0},
   {X86::VCVTSI642SDrr, X86::VCVTSI642SDrm, 0},
   {X86::VCVTSI642SDrr_Int, X86::VCVTSI642SDrm_Int, 0},
+  {X86::VCVTSI642SHZrr, X86::VCVTSI642SHZrm, 0},
+  {X86::VCVTSI642SHZrr_Int, X86::VCVTSI642SHZrm_Int, 0},
   {X86::VCVTSI642SSZrr, X86::VCVTSI642SSZrm, 0},
   {X86::VCVTSI642SSZrr_Int, X86::VCVTSI642SSZrm_Int, 0},
   {X86::VCVTSI642SSrr, X86::VCVTSI642SSrm, 0},
   {X86::VCVTSI642SSrr_Int, X86::VCVTSI642SSrm_Int, 0},
   {X86::VCVTSS2SDZrr, X86::VCVTSS2SDZrm, 0},
   {X86::VCVTSS2SDZrr_Int, X86::VCVTSS2SDZrm_Int, TB_NO_REVERSE},
   {X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0},
   {X86::VCVTSS2SDrr_Int, X86::VCVTSS2SDrm_Int, TB_NO_REVERSE},
+  {X86::VCVTSS2SHZrr, X86::VCVTSS2SHZrm, 0},
+  {X86::VCVTSS2SHZrr_Int, X86::VCVTSS2SHZrm_Int, TB_NO_REVERSE},
   {X86::VCVTTPD2DQZ128rrkz, X86::VCVTTPD2DQZ128rmkz, 0},
   {X86::VCVTTPD2DQZ256rrkz, X86::VCVTTPD2DQZ256rmkz, 0},
   {X86::VCVTTPD2DQZrrkz, X86::VCVTTPD2DQZrmkz, 0},
   {X86::VCVTTPD2QQZ128rrkz, X86::VCVTTPD2QQZ128rmkz, 0},
   {X86::VCVTTPD2QQZ256rrkz, X86::VCVTTPD2QQZ256rmkz, 0},
   {X86::VCVTTPD2QQZrrkz, X86::VCVTTPD2QQZrmkz, 0},
   {X86::VCVTTPD2UDQZ128rrkz, X86::VCVTTPD2UDQZ128rmkz, 0},
   {X86::VCVTTPD2UDQZ256rrkz, X86::VCVTTPD2UDQZ256rmkz, 0},
   {X86::VCVTTPD2UDQZrrkz, X86::VCVTTPD2UDQZrmkz, 0},
   {X86::VCVTTPD2UQQZ128rrkz, X86::VCVTTPD2UQQZ128rmkz, 0},
   {X86::VCVTTPD2UQQZ256rrkz, X86::VCVTTPD2UQQZ256rmkz, 0},
   {X86::VCVTTPD2UQQZrrkz, X86::VCVTTPD2UQQZrmkz, 0},
+  {X86::VCVTTPH2DQZ128rrkz, X86::VCVTTPH2DQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2DQZ256rrkz, X86::VCVTTPH2DQZ256rmkz, 0},
+  {X86::VCVTTPH2DQZrrkz, X86::VCVTTPH2DQZrmkz, 0},
+  {X86::VCVTTPH2QQZ128rrkz, X86::VCVTTPH2QQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZ256rrkz, X86::VCVTTPH2QQZ256rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZrrkz, X86::VCVTTPH2QQZrmkz, 0},
+  {X86::VCVTTPH2UDQZ128rrkz, X86::VCVTTPH2UDQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2UDQZ256rrkz, X86::VCVTTPH2UDQZ256rmkz, 0},
+  {X86::VCVTTPH2UDQZrrkz, X86::VCVTTPH2UDQZrmkz, 0},
+  {X86::VCVTTPH2UQQZ128rrkz, X86::VCVTTPH2UQQZ128rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZ256rrkz, X86::VCVTTPH2UQQZ256rmkz, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZrrkz, X86::VCVTTPH2UQQZrmkz, 0},
+  {X86::VCVTTPH2UWZ128rrkz, X86::VCVTTPH2UWZ128rmkz, 0},
+  {X86::VCVTTPH2UWZ256rrkz, X86::VCVTTPH2UWZ256rmkz, 0},
+  {X86::VCVTTPH2UWZrrkz, X86::VCVTTPH2UWZrmkz, 0},
+  {X86::VCVTTPH2WZ128rrkz, X86::VCVTTPH2WZ128rmkz, 0},
+  {X86::VCVTTPH2WZ256rrkz, X86::VCVTTPH2WZ256rmkz, 0},
+  {X86::VCVTTPH2WZrrkz, X86::VCVTTPH2WZrmkz, 0},
   {X86::VCVTTPS2DQZ128rrkz, X86::VCVTTPS2DQZ128rmkz, 0},
   {X86::VCVTTPS2DQZ256rrkz, X86::VCVTTPS2DQZ256rmkz, 0},
   {X86::VCVTTPS2DQZrrkz, X86::VCVTTPS2DQZrmkz, 0},
   {X86::VCVTTPS2QQZ128rrkz, X86::VCVTTPS2QQZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTTPS2QQZ256rrkz, X86::VCVTTPS2QQZ256rmkz, 0},
   {X86::VCVTTPS2QQZrrkz, X86::VCVTTPS2QQZrmkz, 0},
   {X86::VCVTTPS2UDQZ128rrkz, X86::VCVTTPS2UDQZ128rmkz, 0},
   {X86::VCVTTPS2UDQZ256rrkz, X86::VCVTTPS2UDQZ256rmkz, 0},
   {X86::VCVTTPS2UDQZrrkz, X86::VCVTTPS2UDQZrmkz, 0},
   {X86::VCVTTPS2UQQZ128rrkz, X86::VCVTTPS2UQQZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTTPS2UQQZ256rrkz, X86::VCVTTPS2UQQZ256rmkz, 0},
   {X86::VCVTTPS2UQQZrrkz, X86::VCVTTPS2UQQZrmkz, 0},
   {X86::VCVTUDQ2PDZ128rrkz, X86::VCVTUDQ2PDZ128rmkz, TB_NO_REVERSE},
   {X86::VCVTUDQ2PDZ256rrkz, X86::VCVTUDQ2PDZ256rmkz, 0},
   {X86::VCVTUDQ2PDZrrkz, X86::VCVTUDQ2PDZrmkz, 0},
+  {X86::VCVTUDQ2PHZ128rrkz, X86::VCVTUDQ2PHZ128rmkz, 0},
+  {X86::VCVTUDQ2PHZ256rrkz, X86::VCVTUDQ2PHZ256rmkz, 0},
+  {X86::VCVTUDQ2PHZrrkz, X86::VCVTUDQ2PHZrmkz, 0},
   {X86::VCVTUDQ2PSZ128rrkz, X86::VCVTUDQ2PSZ128rmkz, 0},
   {X86::VCVTUDQ2PSZ256rrkz, X86::VCVTUDQ2PSZ256rmkz, 0},
   {X86::VCVTUDQ2PSZrrkz, X86::VCVTUDQ2PSZrmkz, 0},
   {X86::VCVTUQQ2PDZ128rrkz, X86::VCVTUQQ2PDZ128rmkz, 0},
   {X86::VCVTUQQ2PDZ256rrkz, X86::VCVTUQQ2PDZ256rmkz, 0},
   {X86::VCVTUQQ2PDZrrkz, X86::VCVTUQQ2PDZrmkz, 0},
+  {X86::VCVTUQQ2PHZ128rrkz, X86::VCVTUQQ2PHZ128rmkz, 0},
+  {X86::VCVTUQQ2PHZ256rrkz, X86::VCVTUQQ2PHZ256rmkz, 0},
+  {X86::VCVTUQQ2PHZrrkz, X86::VCVTUQQ2PHZrmkz, 0},
   {X86::VCVTUQQ2PSZ128rrkz, X86::VCVTUQQ2PSZ128rmkz, 0},
   {X86::VCVTUQQ2PSZ256rrkz, X86::VCVTUQQ2PSZ256rmkz, 0},
   {X86::VCVTUQQ2PSZrrkz, X86::VCVTUQQ2PSZrmkz, 0},
   {X86::VCVTUSI2SDZrr, X86::VCVTUSI2SDZrm, 0},
   {X86::VCVTUSI2SDZrr_Int, X86::VCVTUSI2SDZrm_Int, 0},
+  {X86::VCVTUSI2SHZrr, X86::VCVTUSI2SHZrm, 0},
+  {X86::VCVTUSI2SHZrr_Int, X86::VCVTUSI2SHZrm_Int, 0},
   {X86::VCVTUSI2SSZrr, X86::VCVTUSI2SSZrm, 0},
   {X86::VCVTUSI2SSZrr_Int, X86::VCVTUSI2SSZrm_Int, 0},
   {X86::VCVTUSI642SDZrr, X86::VCVTUSI642SDZrm, 0},
   {X86::VCVTUSI642SDZrr_Int, X86::VCVTUSI642SDZrm_Int, 0},
+  {X86::VCVTUSI642SHZrr, X86::VCVTUSI642SHZrm, 0},
+  {X86::VCVTUSI642SHZrr_Int, X86::VCVTUSI642SHZrm_Int, 0},
   {X86::VCVTUSI642SSZrr, X86::VCVTUSI642SSZrm, 0},
   {X86::VCVTUSI642SSZrr_Int, X86::VCVTUSI642SSZrm_Int, 0},
+  {X86::VCVTUW2PHZ128rrkz, X86::VCVTUW2PHZ128rmkz, 0},
+  {X86::VCVTUW2PHZ256rrkz, X86::VCVTUW2PHZ256rmkz, 0},
+  {X86::VCVTUW2PHZrrkz, X86::VCVTUW2PHZrmkz, 0},
+  {X86::VCVTW2PHZ128rrkz, X86::VCVTW2PHZ128rmkz, 0},
+  {X86::VCVTW2PHZ256rrkz, X86::VCVTW2PHZ256rmkz, 0},
+  {X86::VCVTW2PHZrrkz, X86::VCVTW2PHZrmkz, 0},
   {X86::VDBPSADBWZ128rri, X86::VDBPSADBWZ128rmi, 0},
   {X86::VDBPSADBWZ256rri, X86::VDBPSADBWZ256rmi, 0},
   {X86::VDBPSADBWZrri, X86::VDBPSADBWZrmi, 0},
   {X86::VDIVPDYrr, X86::VDIVPDYrm, 0},
   {X86::VDIVPDZ128rr, X86::VDIVPDZ128rm, 0},
   {X86::VDIVPDZ256rr, X86::VDIVPDZ256rm, 0},
   {X86::VDIVPDZrr, X86::VDIVPDZrm, 0},
   {X86::VDIVPDrr, X86::VDIVPDrm, 0},
static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
   {X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrm, 0},
   {X86::VINSERTI128rr, X86::VINSERTI128rm, 0},
   {X86::VINSERTI32x4Z256rr, X86::VINSERTI32x4Z256rm, 0},
   {X86::VINSERTI32x4Zrr, X86::VINSERTI32x4Zrm, 0},
   {X86::VINSERTI32x8Zrr, X86::VINSERTI32x8Zrm, 0},
   {X86::VINSERTI64x2Z256rr, X86::VINSERTI64x2Z256rm, 0},
   {X86::VINSERTI64x2Zrr, X86::VINSERTI64x2Zrm, 0},
   {X86::VINSERTI64x4Zrr, X86::VINSERTI64x4Zrm, 0},
+  {X86::VINSERTPSZrr, X86::VINSERTPSZrm, TB_NO_REVERSE},
+  {X86::VINSERTPSrr, X86::VINSERTPSrm, TB_NO_REVERSE},
   {X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0},
   {X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0},
   {X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0},
   {X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0},
   {X86::VMAXCPDrr, X86::VMAXCPDrm, 0},
   {X86::VMAXCPHZ128rr, X86::VMAXCPHZ128rm, 0},
   {X86::VMAXCPHZ256rr, X86::VMAXCPHZ256rm, 0},
   {X86::VMAXCPHZrr, X86::VMAXCPHZrm, 0},
static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
   {X86::VCMPPSZ256rrik, X86::VCMPPSZ256rmik, 0},
   {X86::VCMPPSZrrik, X86::VCMPPSZrmik, 0},
   {X86::VCMPSDZrr_Intk, X86::VCMPSDZrm_Intk, TB_NO_REVERSE},
   {X86::VCMPSHZrr_Intk, X86::VCMPSHZrm_Intk, TB_NO_REVERSE},
   {X86::VCMPSSZrr_Intk, X86::VCMPSSZrm_Intk, TB_NO_REVERSE},
   {X86::VCVTDQ2PDZ128rrk, X86::VCVTDQ2PDZ128rmk, TB_NO_REVERSE},
   {X86::VCVTDQ2PDZ256rrk, X86::VCVTDQ2PDZ256rmk, 0},
   {X86::VCVTDQ2PDZrrk, X86::VCVTDQ2PDZrmk, 0},
+  {X86::VCVTDQ2PHZ128rrk, X86::VCVTDQ2PHZ128rmk, 0},
+  {X86::VCVTDQ2PHZ256rrk, X86::VCVTDQ2PHZ256rmk, 0},
+  {X86::VCVTDQ2PHZrrk, X86::VCVTDQ2PHZrmk, 0},
   {X86::VCVTDQ2PSZ128rrk, X86::VCVTDQ2PSZ128rmk, 0},
   {X86::VCVTDQ2PSZ256rrk, X86::VCVTDQ2PSZ256rmk, 0},
   {X86::VCVTDQ2PSZrrk, X86::VCVTDQ2PSZrmk, 0},
   {X86::VCVTNE2PS2BF16Z128rrkz, X86::VCVTNE2PS2BF16Z128rmkz, 0},
   {X86::VCVTNE2PS2BF16Z256rrkz, X86::VCVTNE2PS2BF16Z256rmkz, 0},
   {X86::VCVTNE2PS2BF16Zrrkz, X86::VCVTNE2PS2BF16Zrmkz, 0},
   {X86::VCVTNEPS2BF16Z128rrk, X86::VCVTNEPS2BF16Z128rmk, 0},
   {X86::VCVTNEPS2BF16Z256rrk, X86::VCVTNEPS2BF16Z256rmk, 0},
   {X86::VCVTNEPS2BF16Zrrk, X86::VCVTNEPS2BF16Zrmk, 0},
   {X86::VCVTPD2DQZ128rrk, X86::VCVTPD2DQZ128rmk, 0},
   {X86::VCVTPD2DQZ256rrk, X86::VCVTPD2DQZ256rmk, 0},
   {X86::VCVTPD2DQZrrk, X86::VCVTPD2DQZrmk, 0},
+  {X86::VCVTPD2PHZ128rrk, X86::VCVTPD2PHZ128rmk, 0},
+  {X86::VCVTPD2PHZ256rrk, X86::VCVTPD2PHZ256rmk, 0},
+  {X86::VCVTPD2PHZrrk, X86::VCVTPD2PHZrmk, 0},
   {X86::VCVTPD2PSZ128rrk, X86::VCVTPD2PSZ128rmk, 0},
   {X86::VCVTPD2PSZ256rrk, X86::VCVTPD2PSZ256rmk, 0},
   {X86::VCVTPD2PSZrrk, X86::VCVTPD2PSZrmk, 0},
   {X86::VCVTPD2QQZ128rrk, X86::VCVTPD2QQZ128rmk, 0},
   {X86::VCVTPD2QQZ256rrk, X86::VCVTPD2QQZ256rmk, 0},
   {X86::VCVTPD2QQZrrk, X86::VCVTPD2QQZrmk, 0},
   {X86::VCVTPD2UDQZ128rrk, X86::VCVTPD2UDQZ128rmk, 0},
   {X86::VCVTPD2UDQZ256rrk, X86::VCVTPD2UDQZ256rmk, 0},
   {X86::VCVTPD2UDQZrrk, X86::VCVTPD2UDQZrmk, 0},
   {X86::VCVTPD2UQQZ128rrk, X86::VCVTPD2UQQZ128rmk, 0},
   {X86::VCVTPD2UQQZ256rrk, X86::VCVTPD2UQQZ256rmk, 0},
   {X86::VCVTPD2UQQZrrk, X86::VCVTPD2UQQZrmk, 0},
+  {X86::VCVTPH2DQZ128rrk, X86::VCVTPH2DQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2DQZ256rrk, X86::VCVTPH2DQZ256rmk, 0},
+  {X86::VCVTPH2DQZrrk, X86::VCVTPH2DQZrmk, 0},
+  {X86::VCVTPH2PDZ128rrk, X86::VCVTPH2PDZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZ256rrk, X86::VCVTPH2PDZ256rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2PDZrrk, X86::VCVTPH2PDZrmk, 0},
+  {X86::VCVTPH2PSXZ128rrk, X86::VCVTPH2PSXZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2PSXZ256rrk, X86::VCVTPH2PSXZ256rmk, 0},
+  {X86::VCVTPH2PSXZrrk, X86::VCVTPH2PSXZrmk, 0},
   {X86::VCVTPH2PSZ128rrk, X86::VCVTPH2PSZ128rmk, TB_NO_REVERSE},
   {X86::VCVTPH2PSZ256rrk, X86::VCVTPH2PSZ256rmk, 0},
   {X86::VCVTPH2PSZrrk, X86::VCVTPH2PSZrmk, 0},
+  {X86::VCVTPH2QQZ128rrk, X86::VCVTPH2QQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZ256rrk, X86::VCVTPH2QQZ256rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2QQZrrk, X86::VCVTPH2QQZrmk, 0},
+  {X86::VCVTPH2UDQZ128rrk, X86::VCVTPH2UDQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2UDQZ256rrk, X86::VCVTPH2UDQZ256rmk, 0},
+  {X86::VCVTPH2UDQZrrk, X86::VCVTPH2UDQZrmk, 0},
+  {X86::VCVTPH2UQQZ128rrk, X86::VCVTPH2UQQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZ256rrk, X86::VCVTPH2UQQZ256rmk, TB_NO_REVERSE},
+  {X86::VCVTPH2UQQZrrk, X86::VCVTPH2UQQZrmk, 0},
+  {X86::VCVTPH2UWZ128rrk, X86::VCVTPH2UWZ128rmk, 0},
+  {X86::VCVTPH2UWZ256rrk, X86::VCVTPH2UWZ256rmk, 0},
+  {X86::VCVTPH2UWZrrk, X86::VCVTPH2UWZrmk, 0},
+  {X86::VCVTPH2WZ128rrk, X86::VCVTPH2WZ128rmk, 0},
+  {X86::VCVTPH2WZ256rrk, X86::VCVTPH2WZ256rmk, 0},
+  {X86::VCVTPH2WZrrk, X86::VCVTPH2WZrmk, 0},
   {X86::VCVTPS2DQZ128rrk, X86::VCVTPS2DQZ128rmk, 0},
   {X86::VCVTPS2DQZ256rrk, X86::VCVTPS2DQZ256rmk, 0},
   {X86::VCVTPS2DQZrrk, X86::VCVTPS2DQZrmk, 0},
   {X86::VCVTPS2PDZ128rrk, X86::VCVTPS2PDZ128rmk, TB_NO_REVERSE},
   {X86::VCVTPS2PDZ256rrk, X86::VCVTPS2PDZ256rmk, 0},
   {X86::VCVTPS2PDZrrk, X86::VCVTPS2PDZrmk, 0},
+  {X86::VCVTPS2PHXZ128rrk, X86::VCVTPS2PHXZ128rmk, 0},
+  {X86::VCVTPS2PHXZ256rrk, X86::VCVTPS2PHXZ256rmk, 0},
+  {X86::VCVTPS2PHXZrrk, X86::VCVTPS2PHXZrmk, 0},
   {X86::VCVTPS2QQZ128rrk, X86::VCVTPS2QQZ128rmk, TB_NO_REVERSE},
   {X86::VCVTPS2QQZ256rrk, X86::VCVTPS2QQZ256rmk, 0},
   {X86::VCVTPS2QQZrrk, X86::VCVTPS2QQZrmk, 0},
   {X86::VCVTPS2UDQZ128rrk, X86::VCVTPS2UDQZ128rmk, 0},
   {X86::VCVTPS2UDQZ256rrk, X86::VCVTPS2UDQZ256rmk, 0},
   {X86::VCVTPS2UDQZrrk, X86::VCVTPS2UDQZrmk, 0},
   {X86::VCVTPS2UQQZ128rrk, X86::VCVTPS2UQQZ128rmk, TB_NO_REVERSE},
   {X86::VCVTPS2UQQZ256rrk, X86::VCVTPS2UQQZ256rmk, 0},
   {X86::VCVTPS2UQQZrrk, X86::VCVTPS2UQQZrmk, 0},
   {X86::VCVTQQ2PDZ128rrk, X86::VCVTQQ2PDZ128rmk, 0},
   {X86::VCVTQQ2PDZ256rrk, X86::VCVTQQ2PDZ256rmk, 0},
   {X86::VCVTQQ2PDZrrk, X86::VCVTQQ2PDZrmk, 0},
+  {X86::VCVTQQ2PHZ128rrk, X86::VCVTQQ2PHZ128rmk, 0},
+  {X86::VCVTQQ2PHZ256rrk, X86::VCVTQQ2PHZ256rmk, 0},
+  {X86::VCVTQQ2PHZrrk, X86::VCVTQQ2PHZrmk, 0},
   {X86::VCVTQQ2PSZ128rrk, X86::VCVTQQ2PSZ128rmk, 0},
   {X86::VCVTQQ2PSZ256rrk, X86::VCVTQQ2PSZ256rmk, 0},
   {X86::VCVTQQ2PSZrrk, X86::VCVTQQ2PSZrmk, 0},
+  {X86::VCVTSD2SHZrr_Intkz, X86::VCVTSD2SHZrm_Intkz, TB_NO_REVERSE},
   {X86::VCVTSD2SSZrr_Intkz, X86::VCVTSD2SSZrm_Intkz, TB_NO_REVERSE},
+  {X86::VCVTSH2SDZrr_Intkz, X86::VCVTSH2SDZrm_Intkz, TB_NO_REVERSE},
+  {X86::VCVTSH2SSZrr_Intkz, X86::VCVTSH2SSZrm_Intkz, TB_NO_REVERSE},
   {X86::VCVTSS2SDZrr_Intkz, X86::VCVTSS2SDZrm_Intkz, TB_NO_REVERSE},
+  {X86::VCVTSS2SHZrr_Intkz, X86::VCVTSS2SHZrm_Intkz, TB_NO_REVERSE},
   {X86::VCVTTPD2DQZ128rrk, X86::VCVTTPD2DQZ128rmk, 0},
   {X86::VCVTTPD2DQZ256rrk, X86::VCVTTPD2DQZ256rmk, 0},
   {X86::VCVTTPD2DQZrrk, X86::VCVTTPD2DQZrmk, 0},
   {X86::VCVTTPD2QQZ128rrk, X86::VCVTTPD2QQZ128rmk, 0},
   {X86::VCVTTPD2QQZ256rrk, X86::VCVTTPD2QQZ256rmk, 0},
   {X86::VCVTTPD2QQZrrk, X86::VCVTTPD2QQZrmk, 0},
   {X86::VCVTTPD2UDQZ128rrk, X86::VCVTTPD2UDQZ128rmk, 0},
   {X86::VCVTTPD2UDQZ256rrk, X86::VCVTTPD2UDQZ256rmk, 0},
   {X86::VCVTTPD2UDQZrrk, X86::VCVTTPD2UDQZrmk, 0},
   {X86::VCVTTPD2UQQZ128rrk, X86::VCVTTPD2UQQZ128rmk, 0},
   {X86::VCVTTPD2UQQZ256rrk, X86::VCVTTPD2UQQZ256rmk, 0},
   {X86::VCVTTPD2UQQZrrk, X86::VCVTTPD2UQQZrmk, 0},
+  {X86::VCVTTPH2DQZ128rrk, X86::VCVTTPH2DQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2DQZ256rrk, X86::VCVTTPH2DQZ256rmk, 0},
+  {X86::VCVTTPH2DQZrrk, X86::VCVTTPH2DQZrmk, 0},
+  {X86::VCVTTPH2QQZ128rrk, X86::VCVTTPH2QQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZ256rrk, X86::VCVTTPH2QQZ256rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2QQZrrk, X86::VCVTTPH2QQZrmk, 0},
+  {X86::VCVTTPH2UDQZ128rrk, X86::VCVTTPH2UDQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2UDQZ256rrk, X86::VCVTTPH2UDQZ256rmk, 0},
+  {X86::VCVTTPH2UDQZrrk, X86::VCVTTPH2UDQZrmk, 0},
+  {X86::VCVTTPH2UQQZ128rrk, X86::VCVTTPH2UQQZ128rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZ256rrk, X86::VCVTTPH2UQQZ256rmk, TB_NO_REVERSE},
+  {X86::VCVTTPH2UQQZrrk, X86::VCVTTPH2UQQZrmk, 0},
+  {X86::VCVTTPH2UWZ128rrk, X86::VCVTTPH2UWZ128rmk, 0},
+  {X86::VCVTTPH2UWZ256rrk, X86::VCVTTPH2UWZ256rmk, 0},
+  {X86::VCVTTPH2UWZrrk, X86::VCVTTPH2UWZrmk, 0},
+  {X86::VCVTTPH2WZ128rrk, X86::VCVTTPH2WZ128rmk, 0},
+  {X86::VCVTTPH2WZ256rrk, X86::VCVTTPH2WZ256rmk, 0},
+  {X86::VCVTTPH2WZrrk, X86::VCVTTPH2WZrmk, 0},
   {X86::VCVTTPS2DQZ128rrk, X86::VCVTTPS2DQZ128rmk, 0},
   {X86::VCVTTPS2DQZ256rrk, X86::VCVTTPS2DQZ256rmk, 0},
   {X86::VCVTTPS2DQZrrk, X86::VCVTTPS2DQZrmk, 0},
   {X86::VCVTTPS2QQZ128rrk, X86::VCVTTPS2QQZ128rmk, TB_NO_REVERSE},
   {X86::VCVTTPS2QQZ256rrk, X86::VCVTTPS2QQZ256rmk, 0},
   {X86::VCVTTPS2QQZrrk, X86::VCVTTPS2QQZrmk, 0},
   {X86::VCVTTPS2UDQZ128rrk, X86::VCVTTPS2UDQZ128rmk, 0},
   {X86::VCVTTPS2UDQZ256rrk, X86::VCVTTPS2UDQZ256rmk, 0},
   {X86::VCVTTPS2UDQZrrk, X86::VCVTTPS2UDQZrmk, 0},
   {X86::VCVTTPS2UQQZ128rrk, X86::VCVTTPS2UQQZ128rmk, TB_NO_REVERSE},
   {X86::VCVTTPS2UQQZ256rrk, X86::VCVTTPS2UQQZ256rmk, 0},
   {X86::VCVTTPS2UQQZrrk, X86::VCVTTPS2UQQZrmk, 0},
   {X86::VCVTUDQ2PDZ128rrk, X86::VCVTUDQ2PDZ128rmk, TB_NO_REVERSE},
   {X86::VCVTUDQ2PDZ256rrk, X86::VCVTUDQ2PDZ256rmk, 0},
   {X86::VCVTUDQ2PDZrrk, X86::VCVTUDQ2PDZrmk, 0},
+  {X86::VCVTUDQ2PHZ128rrk, X86::VCVTUDQ2PHZ128rmk, 0},
+  {X86::VCVTUDQ2PHZ256rrk, X86::VCVTUDQ2PHZ256rmk, 0},
+  {X86::VCVTUDQ2PHZrrk, X86::VCVTUDQ2PHZrmk, 0},
   {X86::VCVTUDQ2PSZ128rrk, X86::VCVTUDQ2PSZ128rmk, 0},
   {X86::VCVTUDQ2PSZ256rrk, X86::VCVTUDQ2PSZ256rmk, 0},
   {X86::VCVTUDQ2PSZrrk, X86::VCVTUDQ2PSZrmk, 0},
   {X86::VCVTUQQ2PDZ128rrk, X86::VCVTUQQ2PDZ128rmk, 0},
   {X86::VCVTUQQ2PDZ256rrk, X86::VCVTUQQ2PDZ256rmk, 0},
   {X86::VCVTUQQ2PDZrrk, X86::VCVTUQQ2PDZrmk, 0},
+  {X86::VCVTUQQ2PHZ128rrk, X86::VCVTUQQ2PHZ128rmk, 0},
+  {X86::VCVTUQQ2PHZ256rrk, X86::VCVTUQQ2PHZ256rmk, 0},
+  {X86::VCVTUQQ2PHZrrk, X86::VCVTUQQ2PHZrmk, 0},
   {X86::VCVTUQQ2PSZ128rrk, X86::VCVTUQQ2PSZ128rmk, 0},
   {X86::VCVTUQQ2PSZ256rrk, X86::VCVTUQQ2PSZ256rmk, 0},
   {X86::VCVTUQQ2PSZrrk, X86::VCVTUQQ2PSZrmk, 0},
+  {X86::VCVTUW2PHZ128rrk, X86::VCVTUW2PHZ128rmk, 0},
+  {X86::VCVTUW2PHZ256rrk, X86::VCVTUW2PHZ256rmk, 0},
+  {X86::VCVTUW2PHZrrk, X86::VCVTUW2PHZrmk, 0},
+  {X86::VCVTW2PHZ128rrk, X86::VCVTW2PHZ128rmk, 0},
+  {X86::VCVTW2PHZ256rrk, X86::VCVTW2PHZ256rmk, 0},
+  {X86::VCVTW2PHZrrk, X86::VCVTW2PHZrmk, 0},
   {X86::VDBPSADBWZ128rrikz, X86::VDBPSADBWZ128rmikz, 0},
   {X86::VDBPSADBWZ256rrikz, X86::VDBPSADBWZ256rmikz, 0},
   {X86::VDBPSADBWZrrikz, X86::VDBPSADBWZrmikz, 0},
   {X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0},
   {X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0},
   {X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0},
   {X86::VDIVPHZ128rrkz, X86::VDIVPHZ128rmkz, 0},
   {X86::VDIVPHZ256rrkz, X86::VDIVPHZ256rmkz, 0},
static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
   {X86::VMINSDZrr_Intkz, X86::VMINSDZrm_Intkz, TB_NO_REVERSE},
   {X86::VMINSHZrr_Intkz, X86::VMINSHZrm_Intkz, TB_NO_REVERSE},
   {X86::VMINSSZrr_Intkz, X86::VMINSSZrm_Intkz, TB_NO_REVERSE},
   {X86::VMOVAPDZ128rrk, X86::VMOVAPDZ128rmk, TB_NO_REVERSE|TB_ALIGN_16},
   {X86::VMOVAPDZ256rrk, X86::VMOVAPDZ256rmk, TB_NO_REVERSE|TB_ALIGN_32},
   {X86::VMOVAPDZrrk, X86::VMOVAPDZrmk, TB_NO_REVERSE|TB_ALIGN_64},
   {X86::VMOVAPSZ128rrk, X86::VMOVAPSZ128rmk, TB_NO_REVERSE|TB_ALIGN_16},
   {X86::VMOVAPSZ256rrk, X86::VMOVAPSZ256rmk, TB_NO_REVERSE|TB_ALIGN_32},
   {X86::VMOVAPSZrrk, X86::VMOVAPSZrmk, TB_NO_REVERSE|TB_ALIGN_64},
   {X86::VMOVDDUPZ128rrk, X86::VMOVDDUPZ128rmk, TB_NO_REVERSE},
   {X86::VMOVDDUPZ256rrk, X86::VMOVDDUPZ256rmk, 0},
   {X86::VMOVDDUPZrrk, X86::VMOVDDUPZrmk, 0},
   {X86::VMOVDQA32Z128rrk, X86::VMOVDQA32Z128rmk, TB_NO_REVERSE|TB_ALIGN_16},
   {X86::VMOVDQA32Z256rrk, X86::VMOVDQA32Z256rmk, TB_NO_REVERSE|TB_ALIGN_32},
   {X86::VMOVDQA32Zrrk, X86::VMOVDQA32Zrmk, TB_NO_REVERSE|TB_ALIGN_64},
   {X86::VMOVDQA64Z128rrk, X86::VMOVDQA64Z128rmk, TB_NO_REVERSE|TB_ALIGN_16},
   {X86::VMOVDQA64Z256rrk, X86::VMOVDQA64Z256rmk, TB_NO_REVERSE|TB_ALIGN_32},

   {X86::VUNPCKLPSZrrk, X86::VUNPCKLPSZrmk, 0},
   {X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0},
   {X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0},
   {X86::VXORPDZrrk, X86::VXORPDZrmk, 0},
   {X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0},
   {X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0},
   {X86::VXORPSZrrk, X86::VXORPSZrmk, 0},
 };
+

llvm/test/TableGen/x86-auto-memfold.td

+// RUN: llvm-tblgen -gen-x86-fold-tables -asmwriternum=1 %p/../../lib/Target/X86/X86.td -I %p/../../include -I %p/../../lib/Target/X86/ -I %p/../../include/ -I %p/../../lib/Target/ --write-if-changed  -o %t1
+// RUN: cmp %p/../../lib/Target/X86/X86MemFoldTables.inc %t1 --ignore-initial=0:568

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

 //===- utils/TableGen/X86FoldTablesEmitter.cpp - X86 backend-*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting the memory fold tables of
 // the X86 backend instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenTarget.h"
 #include "X86RecognizableInstr.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/X86FoldTablesUtils.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/TableGenBackend.h"
 
 using namespace llvm;
 using namespace X86Disassembler;
 
 namespace {
-
-// 3 possible strategies for the unfolding flag (TB_NO_REVERSE) of the
-// manual added entries.
-enum UnfoldStrategy {
-  UNFOLD,     // Allow unfolding
-  NO_UNFOLD,  // Prevent unfolding
-  NO_STRATEGY // Make decision according to operands' sizes
-};
-
 // Represents an entry in the manual mapped instructions set.
 struct ManualMapEntry {
   const char *RegInstStr;
   const char *MemInstStr;
-  UnfoldStrategy Strategy;
+  uint16_t Strategy;
 
   ManualMapEntry(const char *RegInstStr, const char *MemInstStr,
-                 UnfoldStrategy Strategy = NO_STRATEGY)
+                 uint16_t Strategy = 0)
       : RegInstStr(RegInstStr), MemInstStr(MemInstStr), Strategy(Strategy) {}
 };
 
 // List of instructions requiring explicitly aligned memory.
 const char *ExplicitAlign[] = {"MOVDQA",  "MOVAPS",  "MOVAPD",  "MOVNTPS",
                                "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
 
 // List of instructions NOT requiring explicit memory alignment.
 const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",
                                  "PCMPESTRM", "PCMPESTRI",
                                  "PCMPISTRM", "PCMPISTRI" };
 
-// For manually mapping instructions that do not match by their encoding.
-const ManualMapEntry ManualMapSet[] = {
-    { "ADD16ri_DB",         "ADD16mi",         NO_UNFOLD  },
-    { "ADD16ri8_DB",        "ADD16mi8",        NO_UNFOLD  },
-    { "ADD16rr_DB",         "ADD16mr",         NO_UNFOLD  },
-    { "ADD32ri_DB",         "ADD32mi",         NO_UNFOLD  },
-    { "ADD32ri8_DB",        "ADD32mi8",        NO_UNFOLD  },
-    { "ADD32rr_DB",         "ADD32mr",         NO_UNFOLD  },
-    { "ADD64ri32_DB",       "ADD64mi32",       NO_UNFOLD  },
-    { "ADD64ri8_DB",        "ADD64mi8",        NO_UNFOLD  },
-    { "ADD64rr_DB",         "ADD64mr",         NO_UNFOLD  },
-    { "ADD8ri_DB",          "ADD8mi",          NO_UNFOLD  },
-    { "ADD8rr_DB",          "ADD8mr",          NO_UNFOLD  },
-    { "ADD16rr_DB",         "ADD16rm",         NO_UNFOLD  },
-    { "ADD32rr_DB",         "ADD32rm",         NO_UNFOLD  },
-    { "ADD64rr_DB",         "ADD64rm",         NO_UNFOLD  },
-    { "ADD8rr_DB",          "ADD8rm",          NO_UNFOLD  },
-    { "MMX_MOVD64from64rr", "MMX_MOVQ64mr",    UNFOLD },
-    { "MMX_MOVD64grr",      "MMX_MOVD64mr",    UNFOLD },
-    { "MOVLHPSrr",          "MOVHPSrm",        NO_UNFOLD  },
-    { "PUSH16r",            "PUSH16rmm",       UNFOLD },
-    { "PUSH32r",            "PUSH32rmm",       UNFOLD },
-    { "PUSH64r",            "PUSH64rmm",       UNFOLD },
-    { "TAILJMPr",           "TAILJMPm",        UNFOLD },
-    { "TAILJMPr64",         "TAILJMPm64",      UNFOLD },
-    { "TAILJMPr64_REX",     "TAILJMPm64_REX",  UNFOLD },
-    { "VMOVLHPSZrr",        "VMOVHPSZ128rm",   NO_UNFOLD  },
-    { "VMOVLHPSrr",         "VMOVHPSrm",       NO_UNFOLD  },
-};
-
-
+#include "X86FoldTablesEmitterManualMapSet.inc"
 static bool isExplicitAlign(const CodeGenInstruction *Inst) {
   return any_of(ExplicitAlign, [Inst](const char *InstStr) {
     return Inst->TheDef->getName().contains(InstStr);
   });
 }
 
 static bool isExplicitUnalign(const CodeGenInstruction *Inst) {
   return any_of(ExplicitUnalign, [Inst](const char *InstStr) {
     return Inst->TheDef->getName().contains(InstStr);
   });
 }
 
 class X86FoldTablesEmitter {
   RecordKeeper &Records;
   CodeGenTarget Target;
 
   // Represents an entry in the folding table
   class X86FoldTableEntry {
     const CodeGenInstruction *RegInst;
     const CodeGenInstruction *MemInst;
 
   public:
     bool CannotUnfold = false;
+    bool CannotFold = false;
     bool IsLoad = false;
     bool IsStore = false;
     bool IsAligned = false;
     unsigned int Alignment = 0;
 
+    X86FoldTableEntry() = default;
     X86FoldTableEntry(const CodeGenInstruction *RegInst,
                       const CodeGenInstruction *MemInst)
         : RegInst(RegInst), MemInst(MemInst) {}
 
     void print(formatted_raw_ostream &OS) const {
+      // Stop printing record if it can't fold and unfold.
+      if(CannotUnfold && CannotFold)
+        return;
       OS.indent(2);
-      OS << "{ X86::" << RegInst->TheDef->getName() << ",";
-      OS.PadToColumn(40);
-      OS  << "X86::" << MemInst->TheDef->getName() << ",";
-      OS.PadToColumn(75);
+      OS << "{X86::" << RegInst->TheDef->getName() << ", ";
+      //OS.PadToColumn(40);
+      OS  << "X86::" << MemInst->TheDef->getName() << ", ";
+      //OS.PadToColumn(75);
 
       std::string Attrs;
       if (IsLoad)
-        Attrs += "TB_FOLDED_LOAD | ";
+        Attrs += "TB_FOLDED_LOAD|";
       if (IsStore)
-        Attrs += "TB_FOLDED_STORE | ";
+        Attrs += "TB_FOLDED_STORE|";
       if (CannotUnfold)
-        Attrs += "TB_NO_REVERSE | ";
+        Attrs += "TB_NO_REVERSE|";
+      if (CannotFold)
+        Attrs += "TB_NO_FORWARD|";
       if (IsAligned)
-        Attrs += "TB_ALIGN_" + std::to_string(Alignment) + " | ";
+        Attrs += "TB_ALIGN_" + std::to_string(Alignment) + "|";
 
-      StringRef SimplifiedAttrs = StringRef(Attrs).rtrim("| ");
+      StringRef SimplifiedAttrs = StringRef(Attrs).rtrim("|");
       if (SimplifiedAttrs.empty())
         SimplifiedAttrs = "0";
 
-      OS << SimplifiedAttrs << " },\n";
+      OS << SimplifiedAttrs << "},\n";
     }
 
     bool operator<(const X86FoldTableEntry &RHS) const {
       bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo");
       bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo");
       if (LHSpseudo != RHSpseudo)
         return LHSpseudo;
 
       return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName();
     }
   };
 
-  typedef std::vector<X86FoldTableEntry> FoldTable;
+  struct CodeGenInstructionComparator {
+    // Comparator function
+    bool operator()(const CodeGenInstruction *LHS,
+                    const CodeGenInstruction *RHS) const {
+      assert(LHS && RHS && "LHS and RHS shouldn't be nullptr");
+      bool LHSpseudo = LHS->TheDef->getValueAsBit("isPseudo");
+      bool RHSpseudo = RHS->TheDef->getValueAsBit("isPseudo");
+      if (LHSpseudo != RHSpseudo)
+        return LHSpseudo;
+
+      return LHS->TheDef->getName() < RHS->TheDef->getName();
+    }
+  };
+
+  typedef std::map<const CodeGenInstruction *, X86FoldTableEntry,
+                   CodeGenInstructionComparator>
+      FoldTable;
   // std::vector for each folding table.
   // Table2Addr - Holds instructions which their memory form performs load+store
   // Table#i - Holds instructions which the their memory form perform a load OR
   //           a store,  and their #i'th operand is folded.
   FoldTable Table2Addr;
   FoldTable Table0;
   FoldTable Table1;
   FoldTable Table2;
   FoldTable Table3;
   FoldTable Table4;
 
 public:
   X86FoldTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
 
   // run - Generate the 6 X86 memory fold tables.
   void run(formatted_raw_ostream &OS);
 
 private:
   // Decides to which table to add the entry with the given instructions.
   // S sets the strategy of adding the TB_NO_REVERSE flag.
   void updateTables(const CodeGenInstruction *RegInstr,
-                    const CodeGenInstruction *MemInstr,
-                    const UnfoldStrategy S = NO_STRATEGY);
+                    const CodeGenInstruction *MemInstr, const uint16_t S = 0,
+                    bool IsManual = false);
 
   // Generates X86FoldTableEntry with the given instructions and fill it with
   // the appropriate flags - then adds it to Table.
   void addEntryWithFlags(FoldTable &Table, const CodeGenInstruction *RegInstr,
-                         const CodeGenInstruction *MemInstr,
-                         const UnfoldStrategy S, const unsigned int FoldedInd);
+                         const CodeGenInstruction *MemInstr, const uint16_t S,
+                         const unsigned int FoldedInd, bool isManual);
 
   // Print the given table as a static const C++ array of type
   // X86MemoryFoldTableEntry.
   void printTable(const FoldTable &Table, StringRef TableName,
                   formatted_raw_ostream &OS) {
     OS << "static const X86MemoryFoldTableEntry MemoryFold" << TableName
        << "[] = {\n";
 
-    for (const X86FoldTableEntry &E : Table)
-      E.print(OS);
+    for (auto &E : Table)
+      E.second.print(OS);
 
     OS << "};\n\n";
   }
 };
 
 // Return true if one of the instruction's operands is a RST register class
 static bool hasRSTRegClass(const CodeGenInstruction *Inst) {
   return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {
private:
   }
 };
 
 } // end anonymous namespace
 
 void X86FoldTablesEmitter::addEntryWithFlags(FoldTable &Table,
                                              const CodeGenInstruction *RegInstr,
                                              const CodeGenInstruction *MemInstr,
-                                             const UnfoldStrategy S,
-                                             const unsigned int FoldedInd) {
+                                             const uint16_t S,
+                                             const unsigned int FoldedInd,
+                                             bool isManual) {
 
   X86FoldTableEntry Result = X86FoldTableEntry(RegInstr, MemInstr);
   Record *RegRec = RegInstr->TheDef;
   Record *MemRec = MemInstr->TheDef;
 
+  if (isManual) {
+    Result.CannotUnfold = (S & TB_NO_REVERSE) != 0;
+    Result.CannotFold = (S & TB_NO_FORWARD) != 0;
+    Result.IsLoad = (S & TB_FOLDED_LOAD) != 0;
+    Result.IsStore = (S & TB_FOLDED_STORE) != 0;
+    Result.IsAligned = (S & TB_ALIGN_MASK) != 0;
+    Result.Alignment = 1 << (((S & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT) - 1);
+    Table[RegInstr] = Result;
+    return;
+  }
+
   // Only table0 entries should explicitly specify a load or store flag.
   if (&Table == &Table0) {
     unsigned MemInOpsNum = MemRec->getValueAsDag("InOperandList")->getNumArgs();
     unsigned RegInOpsNum = RegRec->getValueAsDag("InOperandList")->getNumArgs();
     // If the instruction writes to the folded operand, it will appear as an
     // output in the register form instruction and as an input in the memory
     // form instruction.
     // If the instruction reads from the folded operand, it well appear as in
     // input in both forms.
     if (MemInOpsNum == RegInOpsNum)
       Result.IsLoad = true;
     else
       Result.IsStore = true;
   }
 
   Record *RegOpRec = RegInstr->Operands[FoldedInd].Rec;
   Record *MemOpRec = MemInstr->Operands[FoldedInd].Rec;
 
   // Unfolding code generates a load/store instruction according to the size of
   // the register in the register form instruction.
   // If the register's size is greater than the memory's operand size, do not
   // allow unfolding.
-  if (S == UNFOLD)
-    Result.CannotUnfold = false;
-  else if (S == NO_UNFOLD)
+
+  // the unfolded load size will be based on the register size. If that’s bigger
+  // than the memory operand size, the unfolded load will load more memory and
+  // potentially cause a memory fault.
+  if (getRegOperandSize(RegOpRec) > getMemOperandSize(MemOpRec))
+    Result.CannotUnfold = true;
+
+  // Check no-kz version's isMoveReg
+  if (RegRec->getName().ends_with("rkz")) {
+    const CodeGenInstruction *BaseRegInst =
+        &Target.getInstruction(Records.getDef(
+            RegRec->getName().substr(0, RegRec->getName().size() - 2)));
+    Result.CannotUnfold = BaseRegInst->isMoveReg ? true : Result.CannotUnfold;
+  } else if (RegRec->getName().ends_with("rk")) {
+    const CodeGenInstruction *BaseRegInst =
+        &Target.getInstruction(Records.getDef(
+            RegRec->getName().substr(0, RegRec->getName().size() - 1)));
+    Result.CannotUnfold = BaseRegInst->isMoveReg ? true : Result.CannotUnfold;
+  } else if (RegInstr->isMoveReg && Result.IsStore)
     Result.CannotUnfold = true;
-  else if (getRegOperandSize(RegOpRec) > getMemOperandSize(MemOpRec))
-    Result.CannotUnfold = true; // S == NO_STRATEGY
 
   uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits"));
   if (isExplicitAlign(RegInstr)) {
     // The instruction require explicitly aligned memory.
     BitsInit *VectSize = RegRec->getValueAsBitsInit("VectSize");
     uint64_t Value = getValueFromBitsInit(VectSize);
     Result.IsAligned = true;
     Result.Alignment = Value;
   } else if (Enc != X86Local::XOP && Enc != X86Local::VEX &&
              Enc != X86Local::EVEX) {
     // Instructions with VEX encoding do not require alignment.
     if (!isExplicitUnalign(RegInstr) && getMemOperandSize(MemOpRec) > 64) {
       // SSE packed vector instructions require a 16 byte alignment.
       Result.IsAligned = true;
       Result.Alignment = 16;
     }
   }
+  // Expand is only ever created as a masked instruction. It is not safe to
+  // unfold a masked expand because we don't know if it came from an expand load
+  // intrinsic or folding a plain load. If it is from a expand load intrinsic,
+  // Unfolding to plain load would read more elements and could trigger a fault.
+  if (RegRec->getName().contains("EXPAND"))
+    Result.CannotUnfold = true;
 
-  Table.push_back(Result);
+  Table[RegInstr] = Result;
 }
 
 void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr,
                                         const CodeGenInstruction *MemInstr,
-                                        const UnfoldStrategy S) {
+                                        const uint16_t S, bool IsManual) {
 
   Record *RegRec = RegInstr->TheDef;
   Record *MemRec = MemInstr->TheDef;
   unsigned MemOutSize = MemRec->getValueAsDag("OutOperandList")->getNumArgs();
   unsigned RegOutSize = RegRec->getValueAsDag("OutOperandList")->getNumArgs();
   unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs();
   unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs();
 
   // Instructions which Read-Modify-Write should be added to Table2Addr.
   if (MemOutSize != RegOutSize && MemInSize == RegInSize) {
-    addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);
+    addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0, IsManual);
     return;
   }
 
   if (MemInSize == RegInSize && MemOutSize == RegOutSize) {
     // Load-Folding cases.
     // If the i'th register form operand is a register and the i'th memory form
     // operand is a memory operand, add instructions to Table#i.
     for (unsigned i = RegOutSize, e = RegInstr->Operands.size(); i < e; i++) {
       Record *RegOpRec = RegInstr->Operands[i].Rec;
       Record *MemOpRec = MemInstr->Operands[i].Rec;
       // PointerLikeRegClass: For instructions like TAILJMPr, TAILJMPr64, TAILJMPr64_REX
       if ((isRegisterOperand(RegOpRec) ||
            RegOpRec->isSubClassOf("PointerLikeRegClass")) &&
           isMemoryOperand(MemOpRec)) {
         switch (i) {
         case 0:
-          addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);
+          addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0, IsManual);
           return;
         case 1:
-          addEntryWithFlags(Table1, RegInstr, MemInstr, S, 1);
+          addEntryWithFlags(Table1, RegInstr, MemInstr, S, 1, IsManual);
           return;
         case 2:
-          addEntryWithFlags(Table2, RegInstr, MemInstr, S, 2);
+          addEntryWithFlags(Table2, RegInstr, MemInstr, S, 2, IsManual);
           return;
         case 3:
-          addEntryWithFlags(Table3, RegInstr, MemInstr, S, 3);
+          addEntryWithFlags(Table3, RegInstr, MemInstr, S, 3, IsManual);
           return;
         case 4:
-          addEntryWithFlags(Table4, RegInstr, MemInstr, S, 4);
+          addEntryWithFlags(Table4, RegInstr, MemInstr, S, 4, IsManual);
           return;
         }
       }
     }
   } else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) {
     // Store-Folding cases.
     // If the memory form instruction performs a store, the *output*
     // register of the register form instructions disappear and instead a
     // memory *input* operand appears in the memory form instruction.
     // For example:
     //   MOVAPSrr => (outs VR128:$dst), (ins VR128:$src)
     //   MOVAPSmr => (outs), (ins f128mem:$dst, VR128:$src)
     Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec;
     Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec;
     if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec) &&
         getRegOperandSize(RegOpRec) == getMemOperandSize(MemOpRec))
-      addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);
+      addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0, IsManual);
   }
 }
 
 void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
   emitSourceFileHeader("X86 fold tables", OS);
 
   // Holds all memory instructions
   std::vector<const CodeGenInstruction *> MemInsts;
void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
   }
 
   // Add the manually mapped instructions listed above.
   for (const ManualMapEntry &Entry : ManualMapSet) {
     Record *RegInstIter = Records.getDef(Entry.RegInstStr);
     Record *MemInstIter = Records.getDef(Entry.MemInstStr);
 
     updateTables(&(Target.getInstruction(RegInstIter)),
-                 &(Target.getInstruction(MemInstIter)), Entry.Strategy);
+                 &(Target.getInstruction(MemInstIter)), Entry.Strategy, true);
   }
 
-  // Sort the tables before printing.
-  llvm::sort(Table2Addr);
-  llvm::sort(Table0);
-  llvm::sort(Table1);
-  llvm::sort(Table2);
-  llvm::sort(Table3);
-  llvm::sort(Table4);
-
   // Print all tables.
   printTable(Table2Addr, "Table2Addr", OS);
   printTable(Table0, "Table0", OS);
   printTable(Table1, "Table1", OS);
   printTable(Table2, "Table2", OS);
   printTable(Table3, "Table3", OS);
   printTable(Table4, "Table4", OS);
 }
 
 namespace llvm {
 
 void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &o) {
   formatted_raw_ostream OS(o);
   X86FoldTablesEmitter(RK).run(OS);
 }
 } // namespace llvm

llvm/utils/TableGen/X86FoldTablesEmitterManualMapSet.inc

+const ManualMapEntry ManualMapSet[] = {
+    // Part1: These following records are for manually mapping instructions that
+    // do not match by their encoding.
+    { "ADD16ri_DB",         "ADD16mi",         TB_NO_REVERSE  },
+    { "ADD16ri8_DB",        "ADD16mi8",        TB_NO_REVERSE  },
+    { "ADD16rr_DB",         "ADD16mr",         TB_NO_REVERSE  },
+    { "ADD32ri_DB",         "ADD32mi",         TB_NO_REVERSE  },
+    { "ADD32ri8_DB",        "ADD32mi8",        TB_NO_REVERSE  },
+    { "ADD32rr_DB",         "ADD32mr",         TB_NO_REVERSE  },
+    { "ADD64ri32_DB",       "ADD64mi32",       TB_NO_REVERSE  },
+    { "ADD64ri8_DB",        "ADD64mi8",        TB_NO_REVERSE  },
+    { "ADD64rr_DB",         "ADD64mr",         TB_NO_REVERSE  },
+    { "ADD8ri_DB",          "ADD8mi",          TB_NO_REVERSE  },
+    { "ADD8rr_DB",          "ADD8mr",          TB_NO_REVERSE  },
+    { "ADD16rr_DB",         "ADD16rm",         TB_NO_REVERSE  },
+    { "ADD32rr_DB",         "ADD32rm",         TB_NO_REVERSE  },
+    { "ADD64rr_DB",         "ADD64rm",         TB_NO_REVERSE  },
+    { "ADD8rr_DB",          "ADD8rm",          TB_NO_REVERSE  },
+    { "MMX_MOVD64from64rr", "MMX_MOVQ64mr",    TB_FOLDED_STORE },
+    { "MMX_MOVD64grr",      "MMX_MOVD64mr",    TB_FOLDED_STORE },
+    { "MOV64toSDrr",        "MOV64mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "MOVDI2SSrr",         "MOV32mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "MOVPQIto64rr",       "MOVPQI2QImr",     TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "MOVSDto64rr",        "MOVSDmr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "MOVSS2DIrr",         "MOVSSmr",         TB_FOLDED_STORE },
+    { "MOVLHPSrr",          "MOVHPSrm",        TB_NO_REVERSE  },
+    { "PUSH16r",            "PUSH16rmm",       TB_FOLDED_LOAD },
+    { "PUSH32r",            "PUSH32rmm",       TB_FOLDED_LOAD },
+    { "PUSH64r",            "PUSH64rmm",       TB_FOLDED_LOAD },
+    { "TAILJMPr",           "TAILJMPm",        TB_FOLDED_LOAD },
+    { "TAILJMPr64",         "TAILJMPm64",      TB_FOLDED_LOAD },
+    { "TAILJMPr64_REX",     "TAILJMPm64_REX",  TB_FOLDED_LOAD },
+    { "TCRETURNri",         "TCRETURNmi",      TB_FOLDED_LOAD | TB_NO_FORWARD },
+    { "TCRETURNri64",       "TCRETURNmi64",    TB_FOLDED_LOAD | TB_NO_FORWARD },
+    { "VMOVLHPSZrr",        "VMOVHPSZ128rm",   TB_NO_REVERSE  },
+    { "VMOVLHPSrr",         "VMOVHPSrm",       TB_NO_REVERSE  },
+    { "VMOV64toSDZrr",      "MOV64mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOV64toSDrr",       "MOV64mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVDI2SSZrr",       "MOV32mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVDI2SSrr",        "MOV32mr",         TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVPQIto64Zrr",     "VMOVPQI2QIZmr",   TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVPQIto64rr",      "VMOVPQI2QImr",    TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVSDto64Zrr",      "VMOVSDZmr",       TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVSDto64rr",       "VMOVSDmr",        TB_FOLDED_STORE | TB_NO_REVERSE },
+    { "VMOVSS2DIZrr",       "VMOVSSZmr",       TB_FOLDED_STORE },
+    { "VMOVSS2DIrr",        "VMOVSSmr",        TB_FOLDED_STORE },
+    { "MMX_MOVD64to64rr",   "MMX_MOVQ64rm",    0 },
+    { "MOV64toPQIrr",       "MOVQI2PQIrm",     TB_NO_REVERSE },
+    { "MOV64toSDrr",        "MOVSDrm_alt",     TB_NO_REVERSE },
+    { "MOVDI2SSrr",         "MOVSSrm_alt",     0 },
+    { "VMOV64toPQIZrr",     "VMOVQI2PQIZrm",    TB_NO_REVERSE },
+    { "VMOV64toPQIrr",      "VMOVQI2PQIrm",     TB_NO_REVERSE },
+    { "VMOV64toSDZrr",      "VMOVSDZrm_alt",   TB_NO_REVERSE },
+    { "VMOV64toSDrr",       "VMOVSDrm_alt",    TB_NO_REVERSE },
+    { "VMOVDI2SSZrr",       "VMOVSSZrm_alt",   0 },
+    { "VMOVDI2SSrr",        "VMOVSSrm_alt",    0 },
+    { "MOVSDrr",            "MOVLPDrm",         TB_NO_REVERSE },
+    { "VMOVSDZrr",          "VMOVLPDZ128rm",    TB_NO_REVERSE },
+    { "VMOVSDrr",           "VMOVLPDrm",        TB_NO_REVERSE },
+
+    // Part2: These following records are for manually mapping instructions that
+    // have same opcode.
+    // INSERTPSrm has no count_s while INSERTPSrr has count_s.
+    // count_s is to indicate which element in dst vector is inserted.
+    // if count_s!=0, we can't fold INSERTPSrr into INSERTPSrm
+    //
+    // the following folding can happen when count_s==0
+    // load xmm0, m32
+    // insertpsrr xmm1, xmm0, imm
+    // =>
+    // insertpsrm xmm1, m32, imm
+    { "INSERTPSrr",         "INSERTPSrm",      TB_NO_REVERSE | TB_NO_FORWARD },
+    { "UD1Lr",              "UD1Lm",           TB_NO_REVERSE | TB_NO_FORWARD },
+    { "UD1Qr",              "UD1Qm",           TB_NO_REVERSE | TB_NO_FORWARD },
+    { "UD1Wr",              "UD1Wm",           TB_NO_REVERSE | TB_NO_FORWARD },
+    // Remove {"MMX_MOVQ64rr", "MMX_MOVQ64mr"} since it will create duplicate in
+    // unfoldingtable due to the {"MMX_MOVD64from64rr", "MMX_MOVQ64mr"}
+    { "MMX_MOVQ64rr",       "MMX_MOVQ64mr",    TB_NO_FORWARD | TB_NO_REVERSE },
+    { "MMX_MOVQ64rr",       "MMX_MOVQ64rm",    TB_NO_FORWARD | TB_NO_REVERSE },
+};
+