[RISCV] Reuse and generalize adjustReg from another spot in frame lowering [nfc]

[reames]

Summary

Change is straight forward. Posted for review for a second set of eyes on the generalization. In particularly, SrcReg being equal to DestReg is new with this caller. Already caught one bug due to that, anyone spot anything else?

[frasercrmck]

LGTM (with nit) - I couldn't find or think of any problems arising from this.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

351

We have RISCVFrameLowering::adjustReg (used elsewhere in this file) which wraps the call to RI.adjustReg. I think we should continue to use use adjustReg (for now) even though they're equivalent.

Personally I'm not a huge fan of having identically-named methods across multiple files/classes. So if you wanted to remove RISCVFrameLowering::adjustReg and make everyone call the RISCVRegisterInfo one directly, I'd support that.

[asb]

I don't see any issues either. I don't have a strong view about @frasercrmck's nit.

[reames]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

351

This is certainly the end goal, and after this patch and D132839
which just landed, I think I'm close to being able to do that. Might be one or two more cleanup changes first, but that's definitely where we're heading.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 
 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
                                            MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MBBI,
                                            const DebugLoc &DL, int64_t Amount,
                                            MachineInstr::MIFlag Flag) const {
   assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
 
-  const RISCVInstrInfo *TII = STI.getInstrInfo();
   const Register SPReg = getSPReg(STI);
 
   // Optimize compile time offset case
   if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
     // 1. Multiply the number of v-slots by the (constant) length of register
     const int64_t VLENB = STI.getRealMinVLen() / 8;
     assert(Amount % 8 == 0 &&
            "Reserve the stack by the multiple of one vector size.");
     const int64_t NumOfVReg = Amount / 8;
     const int64_t Offset = NumOfVReg * VLENB;
     if (!isInt<32>(Offset)) {
       report_fatal_error(
         "Frame size outside of the signed 32-bit range not supported");
     }
     adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, Flag);
     return;
   }
 
-  unsigned Opc = RISCV::ADD;
-  if (Amount < 0) {
-    Amount = -Amount;
-    Opc = RISCV::SUB;
-  }
-  // 1. Multiply the number of v-slots to the length of registers
-  Register FactorRegister =
-      MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
-  TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, FactorRegister, Amount, Flag);
-  // 2. SP = SP - RVV stack size
-  BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
-      .addReg(SPReg)
-      .addReg(FactorRegister, RegState::Kill)
-      .setMIFlag(Flag);
+  const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
+  RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getScalable(Amount),
+               Flag);
 }
 
 void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   const RISCVInstrInfo *TII = STI.getInstrInfo();

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   // assuming that source reg was.  KillSrcReg means that this is the
   // last use of SrcReg, and that the register can be killed internally.
   void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                  const DebugLoc &DL, Register DestReg, Register SrcReg,
                  int64_t Val, MachineInstr::MIFlag Flag,
                  MaybeAlign RequiredAlign, bool KillSrcReg) const;
 
   // Update DestReg to have the value of SrcReg plus an Offset.
-  void adjustReg(MachineBasicBlock::iterator II, Register DestReg,
-                 Register SrcReg, StackOffset Offset) const;
+  void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
+                 const DebugLoc &DL, Register DestReg, Register SrcReg,
+                 StackOffset Offset, MachineInstr::MIFlag Flag) const;
 
   bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
   TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
   BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrcReg))
       .addReg(ScratchReg, RegState::Kill)
       .setMIFlag(Flag);
 }
 
-void RISCVRegisterInfo::adjustReg(MachineBasicBlock::iterator II, Register DestReg,
-                                  Register SrcReg, StackOffset Offset) const {
+void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator II,
+                                  const DebugLoc &DL, Register DestReg,
+                                  Register SrcReg, StackOffset Offset,
+                                  MachineInstr::MIFlag Flag) const {
 
   if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
     return;
 
-  MachineInstr &MI = *II;
-  MachineFunction &MF = *MI.getParent()->getParent();
+  MachineFunction &MF = *MBB.getParent();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo *TII = ST.getInstrInfo();
-  DebugLoc DL = MI.getDebugLoc();
-  MachineBasicBlock &MBB = *MI.getParent();
 
   bool SrcRegIsKill = false;
 
   if (Offset.getScalable()) {
     unsigned ScalableAdjOpc = RISCV::ADD;
     int64_t ScalableValue = Offset.getScalable();
     if (ScalableValue < 0) {
       ScalableValue = -ScalableValue;
       ScalableAdjOpc = RISCV::SUB;
     }
     // Get vlenb and multiply vlen with the number of vector registers.
-    TII->getVLENFactoredAmount(MF, MBB, II, DL, DestReg, ScalableValue);
+    Register ScratchReg = DestReg;
+    if (DestReg == SrcReg)
+      ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    TII->getVLENFactoredAmount(MF, MBB, II, DL, ScratchReg, ScalableValue, Flag);
     BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
-      .addReg(SrcReg).addReg(DestReg, RegState::Kill);
+      .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
+      .setMIFlag(Flag);
     SrcReg = DestReg;
     SrcRegIsKill = true;
   }
 
   if (Offset.getFixed())
     adjustReg(MBB, II, DL, DestReg, SrcReg, Offset.getFixed(),
-              MachineInstr::NoFlags, None, SrcRegIsKill);
+              Flag, None, SrcRegIsKill);
 }
 
 
 bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                             int SPAdj, unsigned FIOperandNum,
                                             RegScavenger *RS) const {
   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
 
bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   if (Offset.getScalable() || Offset.getFixed()) {
     Register DestReg;
     if (MI.getOpcode() == RISCV::ADDI)
       DestReg = MI.getOperand(0).getReg();
     else
       DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    adjustReg(II, DestReg, FrameReg, Offset);
+    adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
+              MachineInstr::NoFlags);
     MI.getOperand(FIOperandNum).ChangeToRegister(DestReg, /*IsDef*/false,
                                                  /*IsImp*/false,
                                                  /*IsKill*/true);
   } else {
     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*IsDef*/false,
                                                  /*IsImp*/false,
                                                  /*IsKill*/false);
   }