[RISCV] Optimization for using compressed beqz and bnez PR#56391

[ita-sc]

Summary

Optimization for using compressed beqz and bnez

If there is pattern

br_cc val1 constval eq/neq place
select_cc val1 constval eq/neq trueval falseval

and constval does not fit in compressed imm format(6 bit), but fit in
imm format(12 bit), we can replace by non compress sub and compress
c.beqz/c.bneqz:

addi val val -constval
c.beqz val place

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1334

Please put the branch related code in the branch section of this file.

1341

When wouldn't we have a valid MF?

1346

Blank line before this comment.

[ita-sc]

put branch related code to branch part
adding spaces

[ita-sc]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1334

Done

1341

I guess It happens when we run LLVM IR pass that needs SubTargetImpl.
For example, pass Expand Atomic instructions tries to get SubTargetImpl.
It calls createRISCVInstructionSelector during initialization. In it there is an initialization of predicates for globalISel (see GET_GLOBALISEL_PREDICATES_INIT).
Internally it calls computeAvailableModuleFeatures, where all predicates initilized (usially they use subtarget, that is already initialized), but MF is uninitialized there so there will be error.

1346

Done

[liaolucy]

llvm/test/CodeGen/RISCV/compress-opt-branch.ll

6

The testcase should be updated with this script, https://github.com/llvm/llvm-project/blob/main/llvm/utils/update_llc_test_checks.py. ignore if already used

[ita-sc]

llvm/test/CodeGen/RISCV/compress-opt-branch.ll

6

Hi
Could you please add some information about it?
I tried to do it, but looks like this script doesn't support pattern:
llc | llvm-objdump | FileCheck
as expects llvm-objdump to be llc...

I tried to separate it, but pattern:
llc | llvm-objdump > file
cat file | FileCheck
failed too with message: "Skipping non-FileChecked RUN line".
But I need to update result with llvm-objdump to check for compressed instructions.

[liaolucy]

llvm/test/CodeGen/RISCV/compress-opt-branch.ll

6

llvm-project/llvm/test/CodeGen/RISCV/imm.ll as an example:
Command: /llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary=/llvm-project/build/bin/llc llvm-project/llvm/test/CodeGen/RISCV/imm.ll
If the relevant code is modified, the test case will be automatically updated.

But I see that the existing testcases of the c extension(compress-float.ll andcompress.ll) are not updated with the script, so I'm not sure if the testcase of c extension really need to be updated with the script now.

Sorry, please ignore this comment.

[ita-sc]

A gentle ping.

[ita-sc]

update patches

[craig.topper]

llvm/test/CodeGen/RISCV/compress-opt-branch.ll

36

COM isn't a general comment mechanism. It's supposed to be used to temporarily replace a CHECK prefix. Use a regular IR comment.

[ita-sc]

Update review

[craig.topper]

Have you measured the effect of this on any workloads?

[ita-sc]

In D132839#3832203, @craig.topper wrote:

Have you measured the effect of this on any workloads?

Checked on Coremark with/without -Os. Results almost the same. With compressed instructions it is ~1% slower, but size is slightly smaller( this pattern is rare, about 3-4 places where this pattern appears). That is why I added this pattern only when max optimization for size turned on.

[craig.topper]

I guess this is ok. I'm little unsure if this makes sense if the constant has multiple uses, but I also don't think we can reliably identify that in isel.

LGTM

[ita-sc]

Thanks @craig.topper . I don’t have commit access, can you land this patch for me? Please use “Ivan Tetyushkin [e-mail]” to commit the change.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<12>(Imm);
     return MCOp.isBareSymbolRef();
   }];
   let OperandType = "OPERAND_SIMM12";
   let OperandNamespace = "RISCVOp";
 }
 
+// A 12-bit signed immediate which cannot fit in 6-bit signed immediate,
+// but even negative value fit in 12-bit.
+def simm12_no6 : ImmLeaf<XLenVT, [{
+  return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
+
 // A 13-bit signed immediate where the least significant bit is zero.
 def simm13_lsb0 : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
   let PrintMethod = "printBranchOperand";
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
   let MCOperandPredicate = [{
     int64_t Imm;
multiclass SelectCC_GPR_rrirr<RegisterClass valty> {
   def : Pat<(riscv_selectcc_frag:$cc GPR:$lhs, 0, cond, valty:$truev,
                                      valty:$falsev),
             (!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, X0,
              (IntCCtoRISCVCC $cc), valty:$truev, valty:$falsev)>;
 }
 
 defm Select_GPR : SelectCC_GPR_rrirr<GPR>;
 
+class SelectCompressOpt<CondCode Cond>: Pat<(riscv_selectcc_frag:$select GPR:$lhs, simm12_no6:$Constant, Cond,
+                                                  GPR:$truev, GPR:$falsev),
+    (Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0,
+                          (IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
+
+def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
+
+let Predicates = [HasStdExtC, OptForMinSize] in {
+  def : SelectCompressOpt<SETEQ>;
+  def : SelectCompressOpt<SETNE>;
+}
+
 /// Branches and jumps
 
 // Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
 multiclass BccPat<CondCode Cond, RVInstB Inst> {
   def : Pat<(riscv_brcc GPR:$rs1, GPR:$rs2, Cond, bb:$imm12),
             (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
   // Explicitly select 0 to X0. The register coalescer doesn't always do it.
   def : Pat<(riscv_brcc GPR:$rs1, 0, Cond, bb:$imm12),
             (Inst GPR:$rs1, X0, simm13_lsb0:$imm12)>;
 }
 
+class BrccCompessOpt<CondCode Cond, RVInstB Inst> : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
+                              (Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0, bb:$place)>;
+
 defm : BccPat<SETEQ, BEQ>;
 defm : BccPat<SETNE, BNE>;
 defm : BccPat<SETLT, BLT>;
 defm : BccPat<SETGE, BGE>;
 defm : BccPat<SETULT, BLTU>;
 defm : BccPat<SETUGE, BGEU>;
 
+let Predicates = [HasStdExtC, OptForMinSize] in {
+  def : BrccCompessOpt<SETEQ, BEQ>;
+  def : BrccCompessOpt<SETNE, BNE>;
+}
+
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
                PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
 
 let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
 def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>,
                   PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
 

llvm/test/CodeGen/RISCV/compress-opt-branch.ll

+; This test is designed to run 4 times, once with function attribute +c,
+; once with function attribute -c for eq/ne in icmp
+; The optimization should appear only with +c, otherwise default isel should be
+; choosen.
+;
+; RUN: cat %s | sed 's/CMPCOND/eq/g' | sed 's/RESBRNORMAL/bne/g' | \
+; RUN: sed 's/RESBROPT/c.bnez/g' > %t.compress_eq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.compress_eq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %t.compress_eq
+;
+; RUN: cat %s | sed -e 's/CMPCOND/eq/g' | sed -e 's/RESBRNORMAL/bne/g'\
+; RUN:   | sed -e 's/RESBROPT/c.bnez/g' > %t.nocompr_eq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.nocompr_eq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFD %t.nocompr_eq
+;
+; RUN: cat %s | sed 's/CMPCOND/ne/g' | sed 's/RESBRNORMAL/beq/g' | \
+; RUN: sed 's/RESBROPT/c.beqz/g' > %t.compress_neq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.compress_neq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %t.compress_neq
+;
+; RUN: cat %s | sed -e 's/CMPCOND/ne/g' | sed -e 's/RESBRNORMAL/beq/g'\
+; RUN:   | sed -e 's/RESBROPT/c.beqz/g' > %t.nocompr_neq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.nocompr_neq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFD %t.nocompr_neq
+
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_pos>:
+; RV32IFDC: c.li [[REG:.*]], 20
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 20
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 20
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_neg>:
+; RV32IFDC: c.li [[REG:.*]], -20
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -20
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -20
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_pos>:
+; RV32IFDC: c.li [[REG:.*]], 31
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 31
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 31
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_neg>:
+; RV32IFDC: c.li [[REG:.*]], -32
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -32
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -32
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -32
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 32
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 32
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 33
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -33
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -33
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -63
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 63
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 63
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 63
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -63
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -63
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_bedge_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -2047
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 2047
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 2047
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm), negative value fit in 12 bit too.
+; RV32IFDC-LABEL: <f_medium_bedge_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 2047
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -2047
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -2047
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_pos>:
+; RV32IFDC-NOT: RESBROPT
+; --- no compress extension
+; nothing to check.
+define i32 @f_big_ledge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 2048
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_neg>:
+; RV32IFDC-NOT: c.beqz
+; --- no compress extension
+; nothing to check.
+define i32 @f_big_ledge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -2048
+  br i1 %cmp, label %if.then, label %if.else
+if.then:
+  %call = shl i32 %in0, 1
+  br label %if.end
+if.else:
+  %call2 = add i32 %in0, 42
+  br label %if.end
+
+if.end:
+  %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+  ret i32 %toRet
+}

llvm/test/CodeGen/RISCV/compress-opt-select.ll

+; This test is designed to run 4 times, once with function attribute +c,
+; once with function attribute -c for eq/ne in icmp
+; The optimization should appear only with +c, otherwise default isel should be
+; choosen.
+;
+; RUN: cat %s | sed 's/CMPCOND/eq/g' | sed 's/RESBRNORMAL/beq/g' | \
+; RUN: sed 's/RESBROPT/c.beqz/g' > %t.compress_eq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.compress_eq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %t.compress_eq
+;
+; RUN: cat %s | sed -e 's/CMPCOND/eq/g' | sed -e 's/RESBRNORMAL/beq/g'\
+; RUN:   | sed -e 's/RESBROPT/c.beqz/g' > %t.nocompr_eq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.nocompr_eq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFD %t.nocompr_eq
+;
+; RUN: cat %s | sed 's/CMPCOND/ne/g' | sed 's/RESBRNORMAL/bne/g' | \
+; RUN: sed 's/RESBROPT/c.bnez/g' > %t.compress_neq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.compress_neq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFDC %t.compress_neq
+;
+; RUN: cat %s | sed -e 's/CMPCOND/ne/g' | sed -e 's/RESBRNORMAL/bne/g'\
+; RUN:   | sed -e 's/RESBROPT/c.bnez/g' > %t.nocompr_neq
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
+; RUN:   -disable-block-placement < %t.nocompr_neq \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IFD %t.nocompr_neq
+
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_pos>:
+; RV32IFDC: c.li [[REG:.*]], 20
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 20
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 20
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_neg>:
+; RV32IFDC: c.li [[REG:.*]], -20
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -20
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -20
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_pos>:
+; RV32IFDC: c.li [[REG:.*]], 31
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 31
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 31
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_neg>:
+; RV32IFDC: c.li [[REG:.*]], -32
+; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -32
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -32
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -32
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 32
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 32
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 33
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -33
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -33
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -63
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 63
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 63
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 63
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -63
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -63
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_bedge_pos>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -2047
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_pos>:
+; RV32IFD: addi [[REG:.*]], zero, 2047
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 2047
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm), negative value fit in 12 bit too.
+; RV32IFDC-LABEL: <f_medium_bedge_neg>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 2047
+; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_neg>:
+; RV32IFD: addi [[REG:.*]], zero, -2047
+; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -2047
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_pos>:
+; RV32IFDC-NOT: RESBROPT
+; --- no compress extension
+; nothing to check.
+define i32 @f_big_ledge_pos(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, 2048
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_neg>:
+; RV32IFDC-NOT: c.beqz
+; --- no compress extension
+; nothing to check.
+define i32 @f_big_ledge_neg(i32 %in0) minsize {
+  %cmp = icmp CMPCOND i32 %in0, -2048
+  %toRet = select i1 %cmp, i32 0, i32 42
+  ret i32 %toRet
+}