[RISCV] Optimize scalable frame setup when VLEN is precisely known

[reames]

Summary

If we know the exact value of VLEN, the frame offset adjustment for scalable stack slots becomes a fixed constant. This avoids the need to read vlenb, and may allow the offset to be folded into the immediate field of an add/sub.

We could go further here, and fold the offset into a single larger frame adjustment - instead of having a separate scalable adjustment step - but that requires a bit more code reorganization. I may (or may not) return to that in a future patch.

[craig.topper]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

403

Move vreg creation to line 402?

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

90

This instruction doesn't exist. You need addi sp, sp, -512

107

addi sp, sp, 512

[reames]

Restructure to address @craig.topper's comments. Thanks for catching that bug.

[reames]

Realized I was duplicating logic which already existed. I also had the same off by a factor of 8 bug as the prior patch.

[reames]

Uploaded wrong patch version.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
                                            MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MBBI,
                                            const DebugLoc &DL, int64_t Amount,
                                            MachineInstr::MIFlag Flag) const {
   assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
-  Register SPReg = getSPReg(STI);
+  const Register SPReg = getSPReg(STI);
+
+  // Optimize compile time offset case
+  if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
+    // 1. Multiply the number of v-slots by the (constant) length of register
+    const int64_t VLENB = STI.getRealMinVLen() / 8;
+    assert(Amount % 8 == 0 &&
+           "Reserve the stack by the multiple of one vector size.");
+    const int64_t NumOfVReg = Amount / 8;
+    const int64_t Offset = NumOfVReg * VLENB;
+    if (!isInt<32>(Offset)) {
+      report_fatal_error(
+        "Frame size outside of the signed 32-bit range not supported");
+    }
+    adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, Flag);
+    return;
+  }
+
   unsigned Opc = RISCV::ADD;
   if (Amount < 0) {
     Amount = -Amount;
     Opc = RISCV::SUB;
   }
   // 1. Multiply the number of v-slots to the length of registers
   Register FactorRegister =
       MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
   TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, FactorRegister, Amount, Flag);
   // 2. SP = SP - RVV stack size
   BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
       .addReg(SPReg)
       .addReg(FactorRegister, RegState::Kill)
       .setMIFlag(Flag);
 }
 
 void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

 ; SPILL-O2-NEXT:    addi sp, sp, 32
 ; SPILL-O2-NEXT:    ret
 ;
 ; SPILL-O2-VLEN128-LABEL: foo:
 ; SPILL-O2-VLEN128:       # %bb.0:
 ; SPILL-O2-VLEN128-NEXT:    addi sp, sp, -32
 ; SPILL-O2-VLEN128-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; SPILL-O2-VLEN128-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; SPILL-O2-VLEN128-NEXT:    csrr a1, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a1, a1, 1
-; SPILL-O2-VLEN128-NEXT:    sub sp, sp, a1
+; SPILL-O2-VLEN128-NEXT:    addi sp, sp, -32
 ; SPILL-O2-VLEN128-NEXT:    mv s0, a0
 ; SPILL-O2-VLEN128-NEXT:    addi a1, sp, 16
 ; SPILL-O2-VLEN128-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
 ; SPILL-O2-VLEN128-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
 ; SPILL-O2-VLEN128-NEXT:    vfadd.vv v9, v8, v9
 ; SPILL-O2-VLEN128-NEXT:    addi a0, sp, 32
 ; SPILL-O2-VLEN128-NEXT:    vs1r.v v9, (a0) # Unknown-size Folded Spill
 ; SPILL-O2-VLEN128-NEXT:    lui a0, %hi(.L.str)
 ; SPILL-O2-VLEN128-NEXT:    addi a0, a0, %lo(.L.str)
 ; SPILL-O2-VLEN128-NEXT:    call puts@plt
 ; SPILL-O2-VLEN128-NEXT:    vsetvli zero, s0, e64, m1, ta, ma
 ; SPILL-O2-VLEN128-NEXT:    addi a0, sp, 32
 ; SPILL-O2-VLEN128-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    addi a0, sp, 16
 ; SPILL-O2-VLEN128-NEXT:    vl1r.v v9, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    vfadd.vv v8, v9, v8
-; SPILL-O2-VLEN128-NEXT:    csrr a0, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a0, a0, 1
-; SPILL-O2-VLEN128-NEXT:    add sp, sp, a0
+; SPILL-O2-VLEN128-NEXT:    addi sp, sp, 32
 ; SPILL-O2-VLEN128-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    addi sp, sp, 32
 ; SPILL-O2-VLEN128-NEXT:    ret
 {
    %x = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %gvl)
    %call = call signext i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
    %z = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %x, i64 %gvl)
    ret <vscale x 1 x double> %z
 }
 
 declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %passthru, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %gvl)
 declare i32 @puts(i8*);