[RISCV] Restructure eliminateFrameIndex to share more code. NFC

[craig.topper]

Summary

The old code took two different paths based on whether there is
a scalable offset, but these two paths had some code in common.

The main difference between the two code paths was whether we needed
to create a GPR or not for the ADDI that gets created for RVVSpill.
If we had a scalable offset, the same GPR was used as the destination
for adding the scalable offset and the ADDI. To manage this, we now
cache the scratch register and reuse it if it has already been created.

This is a pre-patch for D135009.

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (!isInt<12>(Offset.getFixed())) {
     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
         .addReg(FrameReg)
         .addReg(ScratchReg, RegState::Kill);
     Offset = StackOffset::get(0, Offset.getScalable());
     FrameReg = ScratchReg;
     FrameRegIsKill = true;
   }
 
-  if (!Offset.getScalable()) {
-    // Offset = (fixed offset, 0)
-    MI.getOperand(FIOperandNum)
-        .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
-    if (!IsRVVSpill)
-      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
-    else {
-      if (Offset.getFixed()) {
-        Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-        BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
-          .addReg(FrameReg, getKillRegState(FrameRegIsKill))
-          .addImm(Offset.getFixed());
-        MI.getOperand(FIOperandNum)
-          .ChangeToRegister(ScratchReg, false, false, true);
-      }
-    }
-  } else {
-    // Offset = (fixed offset, scalable offset)
-    // Step 1, the scalable offset, has already been computed.
+  Register ScratchReg;
+
+  // Add in the scalable offset which has already been computed in
+  // ScalableFactorRegister.
+  if (Offset.getScalable()) {
     assert(ScalableFactorRegister &&
            "Expected pre-computation of scalable factor in earlier step");
 
-    // 2. Calculate address: FrameReg + result of multiply
+    // Calculate address: FrameReg + ScalableFactorRegister.
     if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
       BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), MI.getOperand(0).getReg())
           .addReg(FrameReg, getKillRegState(FrameRegIsKill))
           .addReg(ScalableFactorRegister, RegState::Kill);
       MI.eraseFromParent();
       return;
     }
-    Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), VL)
+
+    assert(!ScratchReg && "Already populated ScratchReg?");
+    ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), ScratchReg)
         .addReg(FrameReg, getKillRegState(FrameRegIsKill))
         .addReg(ScalableFactorRegister, RegState::Kill);
+    FrameReg = ScratchReg;
+    FrameRegIsKill = true;
+  }
 
-    if (IsRVVSpill && Offset.getFixed()) {
-      // Scalable load/store has no immediate argument. We need to add the
-      // fixed part into the load/store base address.
-      BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)
-          .addReg(VL)
-          .addImm(Offset.getFixed());
+  // Handle the fixed offset which might be zero.
+  if (IsRVVSpill) {
+    // RVVSpills don't have an immediate. Add an ADDI if the fixed offset is
+    // needed.
+    if (Offset.getFixed()) {
+      // Reuse ScratchReg if it exists, otherwise create a new register.
+      if (!ScratchReg)
+        ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+      BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
+        .addReg(FrameReg, getKillRegState(FrameRegIsKill))
+      FrameReg = ScratchReg;
+      FrameRegIsKill = true;
     }
-
-    // 3. Replace address register with calculated address register
-    MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);
-    if (!IsRVVSpill)
-      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
+  } else {
+    // Otherwise we can replace the original immediate.
   }
 
+  // Finally, replace the frame index operand.
+  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false,
+                                               FrameRegIsKill);
+
   auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
   if (ZvlssegInfo) {
     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
     uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
     if (ShiftAmount != 0)
       BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
           .addReg(VL)