[RISCV] Refactor and improve eliminateFrameIndex.

[craig.topper]

Summary

There are few changes mixed in here.

-Try to reuse the destination register from ADDI instead of always
creating a virtual register. This way we lean on the register
scavenger in fewer case.
-Explicitly reuse the primary virtual register when possible. There's
still a case where both getVLENFactoredAmount and handling large
fixed offsets can both create a secondary virtual register.
-Combine similar BuildMI calls by manipulating the Register variables.

There are still a couple early outs for ADDI, but overall I tried to
arrange the code into steps.

[reames]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

187

I don't follow this logic. Why is knowing it's an add enough to know we can reuse/rewrite it? Actually, I see this part is not new in the code, it's just moved up from above. I'd still encourage you to improve the comment. :)

245

Can you land a pre-change which just does the change in code structure here? This diff is very hard to read. No separate review needed.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

187

It is new. The old code only reuses the ADDI destination for the last instruction in the sequence. The change is to use it as a scratch register for the whole sequence.

There are only 3 types of instructions that we can have here: ADDI, load, or store.

The only inputs to the ADDI are the frame index, and the immediate and we know it doesn't read it's own destination register. That means the destination register is dead before it is written. Thus we can use it as a scratch register. AArch64 does this from what I could tell in their code. I suppose we could do the same for loads, but not stores.

245

I'll try, but it is kind of related to the how the registers are managed in this patch. So I'm not sure it fits into the original code by itself.

[craig.topper]

Re-base after splitting to D135092.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

209

I wonder if there's any reason we can't add the scalable offset here instead of adding large fixed offset first.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

209

I think there is no strong reason to do so. eliminateFrameIndex will handle all kinds of FrameIndex operand. At the beginning, we only have fixed offset in the FrameIndex. Handle large offset is the existing code. When implementing RVV frame handling, I just put the RVV related code after the existing code at that time. I wonder if there is any benefit to put the scalable part earlier? If so, I think it makes sense to move it before handling large fixed offset.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

209

@craig.topper I agree that reordering looks legal to me. Would certainly simplify the code.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   if (!isInt<32>(Offset.getFixed())) {
     report_fatal_error(
         "Frame offsets outside of the signed 32-bit range not supported");
   }
 
   MachineBasicBlock &MBB = *MI.getParent();
   bool FrameRegIsKill = false;
 
+  // If the instruction is an ADDI, we can use it's destination as a scratch
+  // register. Load instructions might have an FP or vector destination and
+  // stores don't have a destination register.
+  Register DestReg;
+  if (MI.getOpcode() == RISCV::ADDI)
+    DestReg = MI.getOperand(0).getReg();
+
   // If required, pre-compute the scalable factor amount which will be used in
   // later offset computation. Since this sequence requires up to two scratch
   // registers -- after which one is made free -- this grants us better
   // scavenging of scratch registers as only up to two are live at one time,
   // rather than three.
-  Register ScalableFactorRegister;
   unsigned ScalableAdjOpc = RISCV::ADD;
   if (Offset.getScalable()) {
     int64_t ScalableValue = Offset.getScalable();
     if (ScalableValue < 0) {
       ScalableValue = -ScalableValue;
       ScalableAdjOpc = RISCV::SUB;
     }
-    // 1. Get vlenb && multiply vlen with the number of vector registers.
-    ScalableFactorRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    TII->getVLENFactoredAmount(MF, MBB, II, DL, ScalableFactorRegister,
-                               ScalableValue);
+    // Use DestReg if it exists, otherwise create a new register.
+    if (!DestReg)
+      DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    // Get vlenb and multiply vlen with the number of vector registers.
+    TII->getVLENFactoredAmount(MF, MBB, II, DL, DestReg, ScalableValue);
   }
 
   if (!isInt<12>(Offset.getFixed())) {
     // The offset won't fit in an immediate, so use a scratch register instead
-    // Modify Offset and FrameReg appropriately
-    Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    // Modify Offset and FrameReg appropriately.
+
+    // Reuse destination register if it exists and is not holding a scalable
+    // offset.
+    Register ScratchReg = DestReg;
+    if (!DestReg || Offset.getScalable()) {
+      ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+      // Also save to DestReg if it doesn't exist.
+      if (!DestReg)
+        DestReg = ScratchReg;
+    }
+
     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
-    if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
-      BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
-        .addReg(FrameReg)
+    BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
+        .addReg(FrameReg, getKillRegState(FrameRegIsKill))
         .addReg(ScratchReg, RegState::Kill);
+    // If this was an ADDI and there is no scalable offset, we can remove it.
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
+      assert(MI.getOperand(0).getReg() == ScratchReg &&
+             "Expected to have written ADDI destination register");
       MI.eraseFromParent();
       return;
     }
-    BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
-        .addReg(FrameReg)
-        .addReg(ScratchReg, RegState::Kill);
+
     Offset = StackOffset::get(0, Offset.getScalable());
     FrameReg = ScratchReg;
     FrameRegIsKill = true;
   }
 
-  Register ScratchReg;
-
-  // Add in the scalable offset which has already been computed in
-  // ScalableFactorRegister.
+  // Add in the scalable offset which has already been computed in DestReg.
   if (Offset.getScalable()) {
-    assert(ScalableFactorRegister &&
-           "Expected pre-computation of scalable factor in earlier step");
-
-    // Calculate address: FrameReg + ScalableFactorRegister.
-    if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
-      BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), MI.getOperand(0).getReg())
-          .addReg(FrameReg, getKillRegState(FrameRegIsKill))
-          .addReg(ScalableFactorRegister, RegState::Kill);
+    assert(DestReg && "DestReg should be valid");
+    BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
+        .addReg(DestReg, RegState::Kill);
+    // If this was an ADDI and there is no fixed offset, we can remove it.
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
+      assert(MI.getOperand(0).getReg() == DestReg &&
+             "Expected to have written ADDI destination register");
       MI.eraseFromParent();
       return;
     }
-
-    assert(!ScratchReg && "Already populated ScratchReg?");
-    ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), ScratchReg)
-        .addReg(FrameReg, getKillRegState(FrameRegIsKill))
-        .addReg(ScalableFactorRegister, RegState::Kill);
-    FrameReg = ScratchReg;
+    FrameReg = DestReg;
     FrameRegIsKill = true;
   }
 
   // Handle the fixed offset which might be zero.
   if (IsRVVSpill) {
     // RVVSpills don't have an immediate. Add an ADDI if the fixed offset is
     // needed.
     if (Offset.getFixed()) {
-      // Reuse ScratchReg if it exists, otherwise create a new register.
-      if (!ScratchReg)
-        ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-      BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
+      // Reuse DestReg if it exists, otherwise create a new register.
+      if (!DestReg)
+        DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+      BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
         .addReg(FrameReg, getKillRegState(FrameRegIsKill))
         .addImm(Offset.getFixed());
-      FrameReg = ScratchReg;
+      FrameReg = DestReg;
       FrameRegIsKill = true;
     }
   } else {
     // Otherwise we can replace the original immediate.
     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
   }
 
   // Finally, replace the frame index operand.

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

bb.0:
     ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
     ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -240
     ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
     ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 1
     ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
     ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
     ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
-    ; CHECK-NEXT: $x11 = PseudoReadVLENB
-    ; CHECK-NEXT: $x11 = SLLI killed $x11, 1
-    ; CHECK-NEXT: $x10 = LUI 1048575
-    ; CHECK-NEXT: $x10 = ADDIW killed $x10, 1824
-    ; CHECK-NEXT: $x10 = ADD $x8, killed $x10
-    ; CHECK-NEXT: $x10 = SUB killed $x10, killed $x11
+    ; CHECK-NEXT: $x10 = PseudoReadVLENB
+    ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
+    ; CHECK-NEXT: $x11 = LUI 1048575
+    ; CHECK-NEXT: $x11 = ADDIW killed $x11, 1824
+    ; CHECK-NEXT: $x11 = ADD $x8, killed $x11
+    ; CHECK-NEXT: $x10 = SUB killed $x11, killed $x10
     ; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
     ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
     ; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
     ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
     ; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
     ; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
     ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
     ; CHECK-NEXT: PseudoRET
     %1:gprnox0 = COPY $x11
     %0:gpr = COPY $x10
     %2:vr = PseudoVLE64_V_M1 %0, %1, 6 :: (load unknown-size from %ir.pa, align 8)
     %3:gpr = ADDI %stack.2, 0
     VS1R_V killed %2:vr, %3:gpr
     PseudoRET
 
 ...

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

 ; RV32-NEXT:    add a0, a2, a0
 ; RV32-NEXT:    li a1, 1
 ; RV32-NEXT:    li a2, 2
 ; RV32-NEXT:    li a3, 3
 ; RV32-NEXT:    li a4, 4
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    li a6, 6
 ; RV32-NEXT:    li a7, 7
-; RV32-NEXT:    csrr t0, vlenb
-; RV32-NEXT:    slli t0, t0, 4
-; RV32-NEXT:    add t0, sp, t0
-; RV32-NEXT:    addi t2, t0, 128
+; RV32-NEXT:    csrr t2, vlenb
+; RV32-NEXT:    slli t2, t2, 4
+; RV32-NEXT:    add t2, sp, t2
+; RV32-NEXT:    addi t2, t2, 128
 ; RV32-NEXT:    addi t4, sp, 128
 ; RV32-NEXT:    li t6, 8
 ; RV32-NEXT:    vs8r.v v8, (a0)
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    vmv.v.i v16, 0
 ; RV32-NEXT:    call vector_arg_indirect_stack@plt
 ; RV32-NEXT:    addi sp, s0, -144
 ; RV32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload

 ; RV64-NEXT:    add a0, a2, a0
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:    li a2, 2
 ; RV64-NEXT:    li a3, 3
 ; RV64-NEXT:    li a4, 4
 ; RV64-NEXT:    li a5, 5
 ; RV64-NEXT:    li a6, 6
 ; RV64-NEXT:    li a7, 7
-; RV64-NEXT:    csrr t0, vlenb
-; RV64-NEXT:    slli t0, t0, 4
-; RV64-NEXT:    add t0, sp, t0
-; RV64-NEXT:    addi t2, t0, 128
+; RV64-NEXT:    csrr t2, vlenb
+; RV64-NEXT:    slli t2, t2, 4
+; RV64-NEXT:    add t2, sp, t2
+; RV64-NEXT:    addi t2, t2, 128
 ; RV64-NEXT:    addi t4, sp, 128
 ; RV64-NEXT:    li t6, 8
 ; RV64-NEXT:    vs8r.v v8, (a0)
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    call vector_arg_indirect_stack@plt
 ; RV64-NEXT:    addi sp, s0, -144
 ; RV64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 144
 ; RV64-NEXT:    ret
   %s = call fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, i32 8)
   ret <vscale x 32 x i32> %s
 }

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

body:             |
   ; CHECK-NEXT:   $x2 = frame-setup ADDI $x2, -272
   ; CHECK-NEXT:   $x10 = frame-setup PseudoReadVLENB
   ; CHECK-NEXT:   $x11 = frame-setup ADDI killed $x0, 52
   ; CHECK-NEXT:   $x10 = frame-setup MUL killed $x10, killed $x11
   ; CHECK-NEXT:   $x2 = frame-setup SUB $x2, killed $x10
   ; CHECK-NEXT:   $x2 = frame-setup ANDI $x2, -128
   ; CHECK-NEXT:   dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
   ; CHECK-NEXT:   renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
-  ; CHECK-NEXT:   $x11 = PseudoReadVLENB
-  ; CHECK-NEXT:   $x10 = ADDI killed $x0, 50
-  ; CHECK-NEXT:   $x11 = MUL killed $x11, killed $x10
-  ; CHECK-NEXT:   $x10 = LUI 1
-  ; CHECK-NEXT:   $x10 = ADDIW killed $x10, -1888
-  ; CHECK-NEXT:   $x10 = ADD $x2, killed $x10
-  ; CHECK-NEXT:   $x10 = ADD killed $x10, killed $x11
+  ; CHECK-NEXT:   $x10 = PseudoReadVLENB
+  ; CHECK-NEXT:   $x11 = ADDI killed $x0, 50
+  ; CHECK-NEXT:   $x10 = MUL killed $x10, killed $x11
+  ; CHECK-NEXT:   $x11 = LUI 1
+  ; CHECK-NEXT:   $x11 = ADDIW killed $x11, -1888
+  ; CHECK-NEXT:   $x11 = ADD $x2, killed $x11
+  ; CHECK-NEXT:   $x10 = ADD killed $x11, killed $x10
   ; CHECK-NEXT:   PseudoVSPILL_M1 killed renamable $v25, killed $x10 :: (store unknown-size into %stack.1, align 8)
   ; CHECK-NEXT:   renamable $x1 = ADDI $x0, 255
   ; CHECK-NEXT:   renamable $x5 = nuw ADDI $x2, 384
   ; CHECK-NEXT:   renamable $x6 = ADDI $x2, 512
   ; CHECK-NEXT:   renamable $x7 = nuw ADDI $x2, 640
   ; CHECK-NEXT:   renamable $x10 = ADDI $x0, 128
   ; CHECK-NEXT:   renamable $x12 = nuw ADDI $x2, 256
   ; CHECK-NEXT:   renamable $x14 = COPY $x0
   ; CHECK-NEXT:   renamable $x17 = nuw ADDI $x2, 256
   ; CHECK-NEXT:   renamable $x18 = ADDI $x2, 1280
   ; CHECK-NEXT:   renamable $x19 = ADDI $x2, 1408
   ; CHECK-NEXT:   renamable $x20 = ADDI $x2, 1536
   ; CHECK-NEXT:   renamable $x21 = ADDI $x2, 1664
   ; CHECK-NEXT:   renamable $x22 = ADDI $x2, 1792
   ; CHECK-NEXT:   renamable $x23 = ADDI $x2, 1920
-  ; CHECK-NEXT:   SD killed $x1, $x2, 8 :: (store (s64) into %stack.15)
-  ; CHECK-NEXT:   SD killed $x5, $x2, 0 :: (store (s64) into %stack.16)
-  ; CHECK-NEXT:   $x11 = LUI 1
-  ; CHECK-NEXT:   $x11 = ADDIW killed $x11, -2048
-  ; CHECK-NEXT:   $x24 = ADD $x2, killed $x11
+  ; CHECK-NEXT:   $x24 = LUI 1
+  ; CHECK-NEXT:   $x24 = ADDIW killed $x24, -2048
+  ; CHECK-NEXT:   $x24 = ADD $x2, killed $x24
   ; CHECK-NEXT:   renamable $x25 = ADDI $x2, 128
   ; CHECK-NEXT:   renamable $x26 = ADDI $x2, 128
   ; CHECK-NEXT:   renamable $x27 = ADDI $x0, 2
   ; CHECK-NEXT:   renamable $x28 = ADDI $x2, 768
   ; CHECK-NEXT:   renamable $x29 = ADDI $x2, 896
   ; CHECK-NEXT:   renamable $x30 = ADDI $x2, 1024
   ; CHECK-NEXT:   renamable $x31 = nuw ADDI $x2, 1152
   ; CHECK-NEXT:   renamable $x15 = ADDIW renamable $x14, 0
   ; CHECK-NEXT:   renamable $x11 = ANDI renamable $x15, 255
   ; CHECK-NEXT:   renamable $x13 = SLLI renamable $x11, 3
   ; CHECK-NEXT:   renamable $x13 = ADD renamable $x26, killed renamable $x13
   ; CHECK-NEXT:   renamable $x13 = LD killed renamable $x13, 0 :: (load (s64))
   ; CHECK-NEXT:   renamable $x16 = SUB killed renamable $x13, renamable $x13
   ; CHECK-NEXT:   dead renamable $x13 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
   ; CHECK-NEXT:   renamable $x13 = nsw ADDI renamable $x16, -2
-  ; CHECK-NEXT:   $x5 = PseudoReadVLENB
-  ; CHECK-NEXT:   $x1 = ADDI killed $x0, 50
-  ; CHECK-NEXT:   $x5 = MUL killed $x5, killed $x1
-  ; CHECK-NEXT:   $x1 = LUI 1
-  ; CHECK-NEXT:   $x1 = ADDIW killed $x1, -1888
-  ; CHECK-NEXT:   $x1 = ADD $x2, killed $x1
-  ; CHECK-NEXT:   $x1 = ADD killed $x1, killed $x5
-  ; CHECK-NEXT:   $x5 = LD $x2, 0 :: (load (s64) from %stack.16)
-  ; CHECK-NEXT:   renamable $v0 = PseudoVRELOAD_M1 killed $x1 :: (load unknown-size from %stack.1, align 8)
-  ; CHECK-NEXT:   $x1 = LD $x2, 8 :: (load (s64) from %stack.15)
+  ; CHECK-NEXT:   SD killed $x10, $x2, 8 :: (store (s64) into %stack.15)
+  ; CHECK-NEXT:   $x10 = PseudoReadVLENB
+  ; CHECK-NEXT:   SD killed $x12, $x2, 0 :: (store (s64) into %stack.16)
+  ; CHECK-NEXT:   $x12 = ADDI killed $x0, 50
+  ; CHECK-NEXT:   $x10 = MUL killed $x10, killed $x12
+  ; CHECK-NEXT:   $x12 = LUI 1
+  ; CHECK-NEXT:   $x12 = ADDIW killed $x12, -1888
+  ; CHECK-NEXT:   $x12 = ADD $x2, killed $x12
+  ; CHECK-NEXT:   $x10 = ADD killed $x12, killed $x10
+  ; CHECK-NEXT:   $x12 = LD $x2, 0 :: (load (s64) from %stack.16)
+  ; CHECK-NEXT:   renamable $v0 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.1, align 8)
+  ; CHECK-NEXT:   $x10 = LD $x2, 8 :: (load (s64) from %stack.15)
   ; CHECK-NEXT:   renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   BLT killed renamable $x16, renamable $x27, %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT:   liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
   ; CHECK-NEXT: {{  $}}

llvm/test/CodeGen/RISCV/rvv/localvar.ll

 ; RV64IV-NEXT:    addi a0, a0, 15
 ; RV64IV-NEXT:    andi a0, a0, -16
 ; RV64IV-NEXT:    sub a0, sp, a0
 ; RV64IV-NEXT:    mv sp, a0
 ; RV64IV-NEXT:    csrr a1, vlenb
 ; RV64IV-NEXT:    slli a1, a1, 1
 ; RV64IV-NEXT:    sub a1, s0, a1
 ; RV64IV-NEXT:    addi a1, a1, -32
-; RV64IV-NEXT:    csrr a2, vlenb
-; RV64IV-NEXT:    slli a2, a2, 1
-; RV64IV-NEXT:    sub a2, s0, a2
-; RV64IV-NEXT:    addi s1, a2, -32
+; RV64IV-NEXT:    csrr s1, vlenb
+; RV64IV-NEXT:    slli s1, s1, 1
+; RV64IV-NEXT:    sub s1, s0, s1
+; RV64IV-NEXT:    addi s1, s1, -32
 ; RV64IV-NEXT:    call notdead@plt
 ; RV64IV-NEXT:    vl2r.v v8, (s1)
 ; RV64IV-NEXT:    csrr a0, vlenb
 ; RV64IV-NEXT:    slli a0, a0, 2
 ; RV64IV-NEXT:    sub a0, s0, a0
 ; RV64IV-NEXT:    addi a0, a0, -32
 ; RV64IV-NEXT:    vl2r.v v8, (a0)
 ; RV64IV-NEXT:    addi sp, s0, -32

 ; RV64IV-NEXT:    andi a0, a0, -16
 ; RV64IV-NEXT:    sub a0, sp, a0
 ; RV64IV-NEXT:    mv sp, a0
 ; RV64IV-NEXT:    addi a1, s1, 128
 ; RV64IV-NEXT:    csrr a2, vlenb
 ; RV64IV-NEXT:    slli a2, a2, 1
 ; RV64IV-NEXT:    add a2, s1, a2
 ; RV64IV-NEXT:    addi a2, a2, 224
-; RV64IV-NEXT:    csrr a3, vlenb
-; RV64IV-NEXT:    slli a3, a3, 1
-; RV64IV-NEXT:    add a3, s1, a3
-; RV64IV-NEXT:    addi s2, a3, 224
+; RV64IV-NEXT:    csrr s2, vlenb
+; RV64IV-NEXT:    slli s2, s2, 1
+; RV64IV-NEXT:    add s2, s1, s2
+; RV64IV-NEXT:    addi s2, s2, 224
 ; RV64IV-NEXT:    call notdead2@plt
 ; RV64IV-NEXT:    lw a0, 124(s1)
 ; RV64IV-NEXT:    vl2r.v v8, (s2)
 ; RV64IV-NEXT:    addi a0, s1, 224
 ; RV64IV-NEXT:    vl2r.v v8, (a0)
 ; RV64IV-NEXT:    lw a0, 120(s1)
 ; RV64IV-NEXT:    addi sp, s0, -256
 ; RV64IV-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

 ; CHECK-NEXT:    sd zero, -48(s0)
 ; CHECK-NEXT:    sd zero, -56(s0)
 ; CHECK-NEXT:    vsetivli a0, 4, e32, m8, ta, mu
 ; CHECK-NEXT:    sd a0, -64(s0)
 ; CHECK-NEXT:    ld a0, -64(s0)
 ; CHECK-NEXT:    addi a1, s0, -56
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a1)
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
-; CHECK-NEXT:    sub a0, s0, a0
-; CHECK-NEXT:    addi s1, a0, -112
+; CHECK-NEXT:    csrr s1, vlenb
+; CHECK-NEXT:    slli s1, s1, 3
+; CHECK-NEXT:    sub s1, s0, s1
+; CHECK-NEXT:    addi s1, s1, -112
 ; CHECK-NEXT:    vs8r.v v8, (s1)
 ; CHECK-NEXT:    li a0, 1
 ; CHECK-NEXT:    sw a0, -68(s0)
 ; CHECK-NEXT:    sw a0, -72(s0)
 ; CHECK-NEXT:    sw a0, -76(s0)
 ; CHECK-NEXT:    sw a0, -80(s0)
 ; CHECK-NEXT:    sw a0, -84(s0)
 ; CHECK-NEXT:    sw a0, -88(s0)