Add all constant physical registers to callee preserved masks

[arichardson]

Summary

This allows MachineCopyPropagation to eliminate copies of constant registers
such as zero registers. They were previously not being eliminated as the
check for MO.clobbersPhysReg(AvailSrc) would return true for constant
registers such as MIPS $zero.

To avoid having to manually add the zero registers to all CalleeSavedRegs
instantiations in tablegen, I instead added a new isConstant bit to the
Register and set this for MIPS, RISC-V, and AArch64 zero registers.
RegisterInfoEmitter.cpp looks at this flag and adds all constant registers
to the preserved register mask.

This may also benefit other passes but so far I have only seen differences
in MachineCopyPropagation. In the future it might make sense to generate
isConstantPhysReg() from this information.

Original source: https://github.com/CTSRD-CHERI/llvm-project/commit/8588d8b81458ed6d87b674893e7752e6a6915574

[luismarques]

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

Redundant move

[arichardson]

Add constant registers for the remaining architectures

[arichardson]

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

The previous one is in the delay-slot, so it's actually setting the argument register a0.

[luismarques]

Makes sense to me but somebody else should give it a more thorough review.

To avoid having to manually add the zero registers to all CalleeSavedRegs instantiations in tablegen,

It seems wise to avoid that approach, even if that also would have worked.

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

Oops, ignore this.

[arichardson]

Add missing RISCV::VLENB

[jrtc27]

llvm/include/llvm/Target/Target.td

192 ↗

(On Diff #452969)

One could follow up with a way to TableGen the implementation of isConstantPhysReg

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

240 ↗

(On Diff #452969)

let ... in would avoid the need to mess with the multiclasses but that's a matter of taste for AMDGPU maintainers

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

80 ↗

(On Diff #452969)

I don't know about other architectures, but RISCV style would be to use let ... in (like CostPerUse below). It'd be good to make sure your change it style-consistent for each backend.

llvm/utils/TableGen/CodeGenRegisters.cpp

159 ↗

(On Diff #452969)

I would expect Constant and Artificial to be handled the same way but I don't know why this is here...

llvm/utils/TableGen/RegisterInfoEmitter.cpp

1667

New line before the comment like above

[luismarques]

In D131958#3725972, @arichardson wrote:

Add missing RISCV::VLENB

Is this actually useful in the context of CSRs?

[arichardson]

llvm/include/llvm/Target/Target.td

192 ↗

(On Diff #452969)

D131962

[arichardson]

In D131958#3726007, @luismarques wrote:

In D131958#3725972, @arichardson wrote:

Add missing RISCV::VLENB

Is this actually useful in the context of CSRs?

There are no test diffs, but it is listed by ::isConstantPhysReg, so I added it here as well.

[arichardson]

Will move the tablegen changes into the commit that generates isConstantPhysReg() so that it's easier to verify that none were missed.

[arichardson]

rebase on top of D131962

[arichardson]

fix coding style

[arichardson]

llvm/test/CodeGen/RISCV/double-convert.ll

643

Still got a load of zero into a saved register here, not quite sure why. blt s2, s4, .LBB12_4 should be able to use the zero register.

[asb]

llvm/test/CodeGen/RISCV/double-convert.ll

643

Yes, there's something weird going on in general with selection of the zero register. See D130809 and the bug tracking this issue. I'm not sure if it's a general problem with register coalescer or if there's some hook that's not set properly somewhere.

[arsenm]

LGTM although this does feel a bit magical

llvm/test/CodeGen/AArch64/avoid-zero-copy.mir

 # Check that we can remove the redundant save of constant registers such as $wzr
 # RUN: llc -mtriple=aarch64-unknown-linux %s -verify-machineinstrs -start-before=machine-cp -o - | FileCheck %s --check-prefix ASM
 # RUN: llc -mtriple=aarch64-unknown-linux %s -verify-machineinstrs -run-pass=machine-cp -o - | FileCheck %s
 --- |
   target triple = "aarch64-unknown-linux"
   declare i32 @bar(i32) nounwind
   define i32 @foo() nounwind {
   ; ASM-LABEL: foo:
   ; ASM:       // %bb.0:
-  ; ASM-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+  ; ASM-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
   ; ASM-NEXT:    mov w0, wzr
-  ; ASM-NEXT:    mov w19, wzr
   ; ASM-NEXT:    bl bar
-  ; ASM-NEXT:    mov w0, w19
-  ; ASM-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+  ; ASM-NEXT:    mov w0, wzr
+  ; ASM-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
   ; ASM-NEXT:    ret
     call i32 @bar(i32 0)
     ret i32 0
   }
 ...
 ---
 name: foo
 body: |
   bb.0 (%ir-block.0):
     ; CHECK-LABEL: name: foo
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $w19 = COPY $wzr
     ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $w0 = COPY killed renamable $w19
+    ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $w19 = COPY $wzr
     $w0 = COPY renamable $w19
     BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
     ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
     $w0 = COPY killed renamable $w19
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

 # Check that we can remove the redundant save of constant registers such as $zero
 # RUN: llc -mtriple=mips64-unknown-freebsd %s -start-before=machine-cp -o - | FileCheck %s --check-prefix ASM
 # RUN: llc -mtriple=mips64-unknown-freebsd %s -verify-machineinstrs -run-pass=machine-cp -o - | FileCheck %s
 --- |
   target triple = "mips64-unknown-freebsd"
   define i32 @a() nounwind {
   ; ASM-LABEL: a:
   ; ASM:       # %bb.0:
   ; ASM-NEXT:    daddiu $sp, $sp, -16
   ; ASM-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    sd $16, 0($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    move $16, $zero
   ; ASM-NEXT:    jalr $25
   ; ASM-NEXT:    move $4, $zero
-  ; ASM-NEXT:    move $4, $16
-  ; ASM-NEXT:    ld $16, 0($sp) # 8-byte Folded Reload
+  ; ASM-NEXT:    move $4, $zero
   ; ASM-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
   ; ASM-NEXT:    jr $ra
   ; ASM-NEXT:    daddiu $sp, $sp, 16
     ret i32 0
   }
 ...
 ---
 name:            a
 body:             |
   bb.0 (%ir-block.0):
     liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
     ; CHECK-LABEL: name: a
     ; CHECK: liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $s0_64 = COPY $zero_64
     ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $a0_64 = COPY killed renamable $s0_64
+    ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $s0_64 = COPY $zero_64
     $a0_64 = COPY renamable $s0_64
     JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
     ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
     $a0_64 = COPY killed renamable $s0_64
     PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
 ...

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32I-NEXT:    lui a0, 278016
 ; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:    li a2, -1
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a3, s3
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    li s2, 0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s6, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfdi@plt
 ; RV32I-NEXT:    mv s5, a1
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    bltz s6, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:  .LBB12_2: # %start
 ; RV32I-NEXT:    li s6, -1
 ; RV32I-NEXT:    blt s2, s4, .LBB12_4
 ; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    mv s6, a1

 ; RV32I-NEXT:    li s0, 0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a3, 790016
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    lui s5, 1048568
 ; RV32I-NEXT:    bltz s4, .LBB26_2
 ; RV32I-NEXT:  # %bb.1: # %start

 ; RV32I-NEXT:    lui a3, 263676
 ; RV32I-NEXT:    li s0, 0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a3, 787968
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    li a1, -128
 ; RV32I-NEXT:    bltz s4, .LBB30_2
 ; RV32I-NEXT:  # %bb.1: # %start

llvm/utils/TableGen/RegisterInfoEmitter.cpp

for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
     // Add those registers to RegMask, but not to SaveList.
     if (DagInit *OPDag =
         dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
       SetTheory::RecSet OPSet;
       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
       Covered |= RegBank.computeCoveredRegisters(
         ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
     }
 
+    // Add all constant physical registers to the preserved mask:
+    SetTheory::RecSet ConstantSet;
+    for (auto &Reg : RegBank.getRegisters()) {
+      if (Reg.Constant)
+        ConstantSet.insert(Reg.TheDef);
+    }
+    Covered |= RegBank.computeCoveredRegisters(
+        ArrayRef<Record *>(ConstantSet.begin(), ConstantSet.end()));
+
     OS << "static const uint32_t " << CSRSet->getName()
        << "_RegMask[] = { ";
     printBitVectorAsHex(OS, Covered, 32);
     OS << "};\n";
   }
   OS << "\n\n";
 
   OS << "ArrayRef<const uint32_t *> " << ClassName