[RISCV] Explicitly select second operand of branch condition to X0.

[craig.topper]

Summary

At least based on the lit tests, the coalescer sometimes fail to
propagate the copy from X0 into the branch instruction. This patch
does it manually during isel. The majority of the changes are from
the select patterns.

Some of the changes are just register allocation changes. Only
the Select change affects the whether a b*z instruction is generated
in the tests. I changed the branch pattern for consistency.

[asb]

I'm obviously a big fan of the codegen improvements resulting from this patch...but it always feels unpleasant to add a target-specific workaround for what seems to be a bug/limitation elsewhere. I think it does make sense to land this workaround as it's not clear how feasible improving the coalescer would be, but perhaps you could file an issue to track this problem?

[reames]

LGTM as well. I think this is worth taking, but as noted, I think we may have more oddities to dig into here.

llvm/test/CodeGen/RISCV/fpclamptosat.ll

3493

I think there's still a problem with this code. This initialization of a1 appears to never be clobbered, and yet we have multiple register copies below instead of zero initialization. It's less immediate problematic than the branch interaction, but something odd is still going on here.

[asb]

I've filed https://github.com/llvm/llvm-project/issues/56872 to at least track this, as it would be great if target-independent improvements meant we could remove these patterns again.