Add all constant physical registers to callee preserved masks

[arichardson]

Summary

This allows MachineCopyPropagation to eliminate copies of constant registers
such as zero registers. They were previously not being eliminated as the
check for MO.clobbersPhysReg(AvailSrc) would return true for constant
registers such as MIPS $zero.

To avoid having to manually add the zero registers to all CalleeSavedRegs
instantiations in tablegen, I instead added a new isConstant bit to the
Register and set this for MIPS, RISC-V, and AArch64 zero registers.
RegisterInfoEmitter.cpp looks at this flag and adds all constant registers
to the preserved register mask.

This may also benefit other passes but so far I have only seen differences
in MachineCopyPropagation. In the future it might make sense to generate
isConstantPhysReg() from this information.

Original source: https://github.com/CTSRD-CHERI/llvm-project/commit/8588d8b81458ed6d87b674893e7752e6a6915574

[luismarques]

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

Redundant move

[arichardson]

Add constant registers for the remaining architectures

[arichardson]

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

The previous one is in the delay-slot, so it's actually setting the argument register a0.

[luismarques]

Makes sense to me but somebody else should give it a more thorough review.

To avoid having to manually add the zero registers to all CalleeSavedRegs instantiations in tablegen,

It seems wise to avoid that approach, even if that also would have worked.

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

12–13

Oops, ignore this.

[arichardson]

Add missing RISCV::VLENB

[jrtc27]

llvm/include/llvm/Target/Target.td

192

One could follow up with a way to TableGen the implementation of isConstantPhysReg

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

240–243

let ... in would avoid the need to mess with the multiclasses but that's a matter of taste for AMDGPU maintainers

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

80

I don't know about other architectures, but RISCV style would be to use let ... in (like CostPerUse below). It'd be good to make sure your change it style-consistent for each backend.

llvm/utils/TableGen/CodeGenRegisters.cpp

159

I would expect Constant and Artificial to be handled the same way but I don't know why this is here...

llvm/utils/TableGen/RegisterInfoEmitter.cpp

1616

New line before the comment like above

[luismarques]

In D131958#3725972, @arichardson wrote:

Add missing RISCV::VLENB

Is this actually useful in the context of CSRs?

[arichardson]

llvm/include/llvm/Target/Target.td

192

D131962

[arichardson]

In D131958#3726007, @luismarques wrote:

In D131958#3725972, @arichardson wrote:

Add missing RISCV::VLENB

Is this actually useful in the context of CSRs?

There are no test diffs, but it is listed by ::isConstantPhysReg, so I added it here as well.

[arichardson]

Will move the tablegen changes into the commit that generates isConstantPhysReg() so that it's easier to verify that none were missed.

[arichardson]

rebase on top of D131962

[arichardson]

fix coding style

[arichardson]

llvm/test/CodeGen/RISCV/double-convert.ll

632

Still got a load of zero into a saved register here, not quite sure why. blt s2, s4, .LBB12_4 should be able to use the zero register.

[asb]

llvm/test/CodeGen/RISCV/double-convert.ll

632

Yes, there's something weird going on in general with selection of the zero register. See D130809 and the bug tracking this issue. I'm not sure if it's a general problem with register coalescer or if there's some hook that's not set properly somewhere.

[arsenm]

LGTM although this does feel a bit magical

llvm/include/llvm/Target/Target.td

class Register<string n, list<string> altNames = []> {
   // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
   // covered by its sub-register AX.
   bit CoveredBySubRegs = false;
 
   // HWEncoding - The target specific hardware encoding for this register.
   bits<16> HWEncoding = 0;
 
   bit isArtificial = false;
+
+  // isConstant - This register always holds a constant value (e.g. the zero
+  // register in architectures such as MIPS)
+  bit isConstant = false;
 }
 
 // RegisterWithSubRegs - This can be used to define instances of Register which
 // need to specify sub-registers.
 // List "subregs" specifies which registers are sub-registers to this one. This
 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
 // This allows the code generator to be careful not to put two values with
 // overlapping live ranges into registers which alias.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 def W24   : AArch64Reg<24, "w24">, DwarfRegNum<[24]>;
 def W25   : AArch64Reg<25, "w25">, DwarfRegNum<[25]>;
 def W26   : AArch64Reg<26, "w26">, DwarfRegNum<[26]>;
 def W27   : AArch64Reg<27, "w27">, DwarfRegNum<[27]>;
 def W28   : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;
 def W29   : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;
 def W30   : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;
 def WSP   : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
-def WZR   : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>;
+def WZR   : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP> { let isConstant = true; }
 
 let SubRegIndices = [sub_32] in {
 def X0    : AArch64Reg<0,   "x0",  [W0]>, DwarfRegAlias<W0>;
 def X1    : AArch64Reg<1,   "x1",  [W1]>, DwarfRegAlias<W1>;
 def X2    : AArch64Reg<2,   "x2",  [W2]>, DwarfRegAlias<W2>;
 def X3    : AArch64Reg<3,   "x3",  [W3]>, DwarfRegAlias<W3>;
 def X4    : AArch64Reg<4,   "x4",  [W4]>, DwarfRegAlias<W4>;
 def X5    : AArch64Reg<5,   "x5",  [W5]>, DwarfRegAlias<W5>;

 def X24   : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
 def X25   : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
 def X26   : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
 def X27   : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
 def X28   : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
 def FP    : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
 def LR    : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
 def SP    : AArch64Reg<31, "sp",  [WSP]>, DwarfRegAlias<WSP>;
-def XZR   : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
+def XZR   : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP> { let isConstant = true; }
 }
 
 // Condition code register.
 def NZCV  : AArch64Reg<0, "nzcv">;
 
 // First fault status register
 def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
 

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
 
   return RC;
 }
 
 bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
   switch (PhysReg) {
   case AMDGPU::SGPR_NULL:
   case AMDGPU::SGPR_NULL64:
+  case AMDGPU::SGPR_NULL_HI:
   case AMDGPU::SRC_SHARED_BASE:
   case AMDGPU::SRC_PRIVATE_BASE:
   case AMDGPU::SRC_SHARED_LIMIT:
   case AMDGPU::SRC_PRIVATE_LIMIT:
     return true;
   default:
     return false;
   }

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
 
   // These need to be kept in sync with the enum SIRCFlags.
   let TSFlags{0} = HasVGPR;
   let TSFlags{1} = HasAGPR;
   let TSFlags{2} = HasSGPR;
 }
 
 multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
-                        bit HWEncodingHigh = 0> {
+                        bit HWEncodingHigh = 0, bit Constant = false> {
   // There is no special encoding for 16 bit subregs, these are not real
   // registers but rather operands for instructions preserving other 16 bits
   // of the result or reading just 16 bits of a 32 bit VGPR.
   // It is encoded as a corresponding 32 bit register.
   // Non-VGPR register classes use it as we need to have matching subregisters
   // to move instructions and data between ALUs.
   def _LO16 : SIReg<n#".l", regIdx> {
     let HWEncoding{8} = HWEncodingHigh;
+    let isConstant = Constant;
   }
   def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> {
     let isArtificial = ArtificialHigh;
     let HWEncoding{8} = HWEncodingHigh;
+    let isConstant = Constant;
   }
   def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
                                    !cast<Register>(NAME#"_HI16")]> {
     let Namespace = "AMDGPU";
     let SubRegIndices = [lo16, hi16];
     let CoveredBySubRegs = !not(ArtificialHigh);
     let HWEncoding = regIdx;
     let HWEncoding{8} = HWEncodingHigh;
+    let isConstant = Constant;
   }
 }
 
+multiclass SIRegLoHi16Const<string n, bits<16> regIdx, bit ArtificialHigh = 1,
+                            bit HWEncodingHigh = 0>
+         : SIRegLoHi16<n, regIdx, ArtificialHigh, HWEncodingHigh, true>;
+
 // Special Registers
 defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
 defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
 
 // Pseudo-registers: Used as placeholders during isel and immediately
 // replaced, never seeing the verifier.
 def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;
 def FP_REG : SIReg<"fp", 0>;

 // Encoding changes between subtarget generations.
 // See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.
 defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;
 defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;
 defm M0 : SIRegLoHi16 <"m0", 0>;
 
 defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;
 defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;
-defm SGPR_NULL : SIRegLoHi16 <"null", 0>;
-defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;
+defm SGPR_NULL : SIRegLoHi16Const <"null", 0>;
+defm SGPR_NULL_HI : SIRegLoHi16Const <"", 0>;
 
 def SGPR_NULL64 :
     RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = SGPR_NULL.HWEncoding;
+  let isConstant = true;
 }
 
-defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>;
-defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>;
-defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>;
-defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;
+defm SRC_SHARED_BASE : SIRegLoHi16Const<"src_shared_base", 235>;
+defm SRC_SHARED_LIMIT : SIRegLoHi16Const<"src_shared_limit", 236>;
+defm SRC_PRIVATE_BASE : SIRegLoHi16Const<"src_private_base", 237>;
+defm SRC_PRIVATE_LIMIT : SIRegLoHi16Const<"src_private_limit", 238>;
 defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
 
 // Not addressable
 def MODE : SIReg <"mode", 0>;
 
 def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
   // There is no physical register corresponding to this. This is an
   // encoding value in a source field, which will ultimately trigger a

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td

 
 let FallbackRegAltNameIndex = NoRegAltName in
 def RegAliasName : RegAltNameIndex;
 } // Namespace = "LoongArch"
 
 // Integer registers
 
 let RegAltNameIndices = [RegAliasName] in {
-  def R0  : LoongArchReg<0,  "r0", ["zero"]>, DwarfRegNum<[0]>;
+  def R0  : LoongArchReg<0,  "r0", ["zero"]>, DwarfRegNum<[0]> { let isConstant = true; }
   def R1  : LoongArchReg<1,  "r1", ["ra"]>, DwarfRegNum<[1]>;
   def R2  : LoongArchReg<2,  "r2", ["tp"]>, DwarfRegNum<[2]>;
   def R3  : LoongArchReg<3,  "r3", ["sp"]>, DwarfRegNum<[3]>;
   def R4  : LoongArchReg<4,  "r4", ["a0"]>, DwarfRegNum<[4]>;
   def R5  : LoongArchReg<5,  "r5", ["a1"]>, DwarfRegNum<[5]>;
   def R6  : LoongArchReg<6,  "r6", ["a2"]>, DwarfRegNum<[6]>;
   def R7  : LoongArchReg<7,  "r7", ["a3"]>, DwarfRegNum<[7]>;
   def R8  : LoongArchReg<8,  "r8", ["a4"]>, DwarfRegNum<[8]>;

llvm/lib/Target/Mips/MipsRegisterInfo.td

 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 let Namespace = "Mips" in {
   // General Purpose Registers
-  def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
+  def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]> { let isConstant = true; }
   def AT   : MipsGPRReg< 1, "1">,    DwarfRegNum<[1]>;
   def V0   : MipsGPRReg< 2, "2">,    DwarfRegNum<[2]>;
   def V1   : MipsGPRReg< 3, "3">,    DwarfRegNum<[3]>;
   def A0   : MipsGPRReg< 4, "4">,    DwarfRegNum<[4]>;
   def A1   : MipsGPRReg< 5, "5">,    DwarfRegNum<[5]>;
   def A2   : MipsGPRReg< 6, "6">,    DwarfRegNum<[6]>;
   def A3   : MipsGPRReg< 7, "7">,    DwarfRegNum<[7]>;
   def T0   : MipsGPRReg< 8, "8">,    DwarfRegNum<[8]>;
let Namespace = "Mips" in {
   def K0   : MipsGPRReg< 26, "26">,  DwarfRegNum<[26]>;
   def K1   : MipsGPRReg< 27, "27">,  DwarfRegNum<[27]>;
   def GP   : MipsGPRReg< 28, "gp">,  DwarfRegNum<[28]>;
   def SP   : MipsGPRReg< 29, "sp">,  DwarfRegNum<[29]>;
   def FP   : MipsGPRReg< 30, "fp">,  DwarfRegNum<[30]>;
   def RA   : MipsGPRReg< 31, "ra">,  DwarfRegNum<[31]>;
 
   // General Purpose 64-bit Registers
-  def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
+  def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]> { let isConstant = true; }
   def AT_64   : Mips64GPRReg< 1, "1",    [AT]>, DwarfRegNum<[1]>;
   def V0_64   : Mips64GPRReg< 2, "2",    [V0]>, DwarfRegNum<[2]>;
   def V1_64   : Mips64GPRReg< 3, "3",    [V1]>, DwarfRegNum<[3]>;
   def A0_64   : Mips64GPRReg< 4, "4",    [A0]>, DwarfRegNum<[4]>;
   def A1_64   : Mips64GPRReg< 5, "5",    [A1]>, DwarfRegNum<[5]>;
   def A2_64   : Mips64GPRReg< 6, "6",    [A2]>, DwarfRegNum<[6]>;
   def A3_64   : Mips64GPRReg< 7, "7",    [A3]>, DwarfRegNum<[7]>;
   def T0_64   : Mips64GPRReg< 8, "8",    [T0]>, DwarfRegNum<[8]>;

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 }
 
 // 16 paired even-odd consecutive GP8s.
 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {
   def G8p#!srl(Index, 1) : GP8Pair<"r"#Index, Index>;
 }
 
 // The representation of r0 when treated as the constant 0.
-def ZERO  : GPR<0, "0">,    DwarfRegAlias<R0>;
-def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>;
+def ZERO  : GPR<0, "0">,    DwarfRegAlias<R0> { let isConstant = true; }
+def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0> { let isConstant = true; }
 
 // Representations of the frame pointer used by ISD::FRAMEADDR.
 def FP   : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
 def FP8  : GP8<FP, "**FRAME POINTER**">;
 
 // Representations of the base pointer used by setjmp.
 def BP   : GPR<0 /* arbitrary */, "**BASE POINTER**">;
 def BP8  : GP8<BP, "**BASE POINTER**">;

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 // Integer registers
 // CostPerUse is set higher for registers that may not be compressible as they
 // are not part of GPRC, the most restrictive register class used by the
 // compressed instruction set. This will influence the greedy register
 // allocator to reduce the use of registers that can't be encoded in 16 bit
 // instructions.
 
 let RegAltNameIndices = [ABIRegAltName] in {
-  def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
+  def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]> { let isConstant = true; }
   let CostPerUse = [0, 1] in {
   def X1  : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
   def X2  : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
   def X3  : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
   def X4  : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
   def X5  : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
   def X6  : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
   def X7  : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
foreach Index = [0, 8, 16, 24] in {
     }
   }
 
   def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
   def VL     : RISCVReg<0, "vl", ["vl"]>;
   def VXSAT  : RISCVReg<0, "vxsat", ["vxsat"]>;
   def VXRM   : RISCVReg<0, "vxrm", ["vxrm"]>;
   def VLENB  : RISCVReg<0, "vlenb", ["vlenb"]>,
-               DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
+               DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]> { let isConstant = true; }
 }
 
 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
                           (add VTYPE, VL, VLENB)> {
   let RegInfos = XLenRI;
 }
 
 

llvm/lib/Target/VE/VERegisterInfo.td

 // Vector registers - 64 bits wide 256 elements
 foreach I = 0-63 in
   def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>;
 
 // Vector Index Register
 def VIX : VEVecReg<255, "vix", [], ["vix"]>;
 
 // Vector mask registers - 256 bits wide
-foreach I = 0-15 in
+def VM0 : VEMaskReg<0, "vm0", [], ["vm0"]>, DwarfRegNum<[128]> { let isConstant = true; }
+foreach I = 1-15 in
   def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>;
 
 // Aliases of VMs to use as a pair of two VM for packed instructions
-def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>;
+def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]> { let isConstant = true; }
 
 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
 foreach I = 1-7 in
   def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I,
                         [!cast<VEMaskReg>("VM"#!shl(I,1)),
                          !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))],
                         ["vm"#!shl(I,1)]>;
 

llvm/test/CodeGen/AArch64/avoid-zero-copy.mir

 # Check that we can remove the redundant save of constant registers such as $wzr
 # RUN: llc -mtriple=aarch64-unknown-linux %s -start-before=machine-cp -o - | FileCheck %s --check-prefix ASM
 # RUN: llc -mtriple=aarch64-unknown-linux %s -run-pass=machine-cp -o - | FileCheck %s
 --- |
   target triple = "aarch64-unknown-linux"
   declare i32 @bar(i32) nounwind
   define i32 @foo() nounwind {
   ; ASM-LABEL: foo:
   ; ASM:       // %bb.0:
-  ; ASM-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+  ; ASM-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
   ; ASM-NEXT:    mov w0, wzr
-  ; ASM-NEXT:    mov w19, wzr
   ; ASM-NEXT:    bl bar
-  ; ASM-NEXT:    mov w0, w19
-  ; ASM-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+  ; ASM-NEXT:    mov w0, wzr
+  ; ASM-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
   ; ASM-NEXT:    ret
     call i32 @bar(i32 0)
     ret i32 0
   }
 ...
 ---
 name: foo
 body: |
   bb.0 (%ir-block.0):
     ; CHECK-LABEL: name: foo
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $w19 = COPY $wzr
     ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $w0 = COPY killed renamable $w19
+    ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $w19 = COPY $wzr
     $w0 = COPY renamable $w19
     BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
     ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
     $w0 = COPY killed renamable $w19
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/Mips/avoid-zero-copy.mir

 # Check that we can remove the redundant save of constant registers such as $zero
 # RUN: llc -mtriple=mips64-unknown-freebsd %s -start-before=machine-cp -o - | FileCheck %s --check-prefix ASM
 # RUN: llc -mtriple=mips64-unknown-freebsd %s -verify-machineinstrs -run-pass=machine-cp -o - | FileCheck %s
 --- |
   target triple = "mips64-unknown-freebsd"
   define i32 @a() nounwind {
   ; ASM-LABEL: a:
   ; ASM:       # %bb.0:
   ; ASM-NEXT:    daddiu $sp, $sp, -16
   ; ASM-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    sd $16, 0($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    move $16, $zero
   ; ASM-NEXT:    jalr $25
   ; ASM-NEXT:    move $4, $zero
-  ; ASM-NEXT:    move $4, $16
-  ; ASM-NEXT:    ld $16, 0($sp) # 8-byte Folded Reload
+  ; ASM-NEXT:    move $4, $zero
   ; ASM-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
   ; ASM-NEXT:    jr $ra
   ; ASM-NEXT:    daddiu $sp, $sp, 16
     ret i32 0
   }
 ...
 ---
 name:            a
 body:             |
   bb.0 (%ir-block.0):
     liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
     ; CHECK-LABEL: name: a
     ; CHECK: liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $s0_64 = COPY $zero_64
     ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $a0_64 = COPY killed renamable $s0_64
+    ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $s0_64 = COPY $zero_64
     $a0_64 = COPY renamable $s0_64
     JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
     ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
     $a0_64 = COPY killed renamable $s0_64
     PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
 ...

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32I-NEXT:    lui a0, 278016
 ; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:    li a2, -1
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a3, s3
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    li s2, 0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s6, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfdi@plt
 ; RV32I-NEXT:    mv s5, a1
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    bltz s6, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:  .LBB12_2: # %start
 ; RV32I-NEXT:    li s6, -1
 ; RV32I-NEXT:    blt s2, s4, .LBB12_4
 ; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    mv s6, a1

 ; RV32I-NEXT:    li s0, 0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a3, 790016
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    lui s5, 1048568
 ; RV32I-NEXT:    bltz s4, .LBB26_2
 ; RV32I-NEXT:  # %bb.1: # %start

 ; RV32I-NEXT:    lui a3, 263676
 ; RV32I-NEXT:    li s0, 0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a3, 787968
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    li a1, -128
 ; RV32I-NEXT:    bltz s4, .LBB30_2
 ; RV32I-NEXT:  # %bb.1: # %start

llvm/utils/TableGen/CodeGenRegisters.h

namespace llvm {
   /// CodeGenRegister - Represents a register definition.
   struct CodeGenRegister {
     Record *TheDef;
     unsigned EnumValue;
     std::vector<int64_t> CostPerUse;
     bool CoveredBySubRegs;
     bool HasDisjunctSubRegs;
     bool Artificial;
+    bool Constant;
 
     // Map SubRegIndex -> Register.
     typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *,
                      deref<std::less<>>>
         SubRegMap;
 
     CodeGenRegister(Record *R, unsigned Enum);
 

llvm/utils/TableGen/CodeGenRegisters.cpp

 //===----------------------------------------------------------------------===//
 //                              CodeGenRegister
 //===----------------------------------------------------------------------===//
 
 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
     : TheDef(R), EnumValue(Enum),
       CostPerUse(R->getValueAsListOfInts("CostPerUse")),
       CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
-      HasDisjunctSubRegs(false), SubRegsComplete(false),
-      SuperRegsComplete(false), TopoSig(~0u) {
+      HasDisjunctSubRegs(false), Constant(R->getValueAsBit("isConstant")),
+      SubRegsComplete(false), SuperRegsComplete(false), TopoSig(~0u) {
   Artificial = R->getValueAsBit("isArtificial");
 }
 
 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
   std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
   std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
 
   if (SRIs.size() != SRs.size())
     PrintFatalError(TheDef->getLoc(),

llvm/utils/TableGen/RegisterInfoEmitter.cpp

for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
     // Add those registers to RegMask, but not to SaveList.
     if (DagInit *OPDag =
         dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
       SetTheory::RecSet OPSet;
       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
       Covered |= RegBank.computeCoveredRegisters(
         ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
     }
+    // Add all constant physical registers to the preserved mask:
+    SetTheory::RecSet ConstantSet;
+    for (auto& Reg : RegBank.getRegisters()) {
+      if (Reg.Constant)
+        ConstantSet.insert(Reg.TheDef);
+    }
+    Covered |= RegBank.computeCoveredRegisters(
+        ArrayRef<Record*>(ConstantSet.begin(), ConstantSet.end()));
 
     OS << "static const uint32_t " << CSRSet->getName()
        << "_RegMask[] = { ";
     printBitVectorAsHex(OS, Covered, 32);
     OS << "};\n";
   }
   OS << "\n\n";