[DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" to match only demanded bits

[RKSimon]

Summary

The "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" fold is currently limited to the XOR mask being a shifted all-bits mask, but we can relax this to only need to match under the demanded bits.

This helps expose more bit extraction/clearing patterns and fixes the PowerPC testCompares*.ll regressions from D127115

Alive2: https://alive2.llvm.org/ce/z/fl7T7K

[RKSimon]

llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

81 ↗

(On Diff #445229)

I don't think this will appear in DAG, and Instcombine will fold this to a xor-shift-mask pattern: https://gcc.godbolt.org/z/nMdqeaGYh

[RKSimon]

Do people think this is going to need a TLI callback ?

[RKSimon]

In D129933#3658367, @RKSimon wrote:

Do people think this is going to need a TLI callback ?

We might be able to adjust visitShiftByConstant + isDesirableToCommuteWithShift to handle this - I'll take a look.

[dmgreen]

We might be able to adjust visitShiftByConstant + isDesirableToCommuteWithShift to handle this - I'll take a look.

That might be best - this does seem to come up in practice. For example:

define i32 @test(i32 %conv73, i32 %i63.0) {
  %and74 = shl i32 %i63.0, 2
  %sub75 = and i32 %and74, 4
  %shl76 = xor i32 %sub75, 4
  ret i32 %shl76
}

movs    r0, #4               |   42         mvns    r0, r1            
bic.w   r0, r0, r1, lsl #2   |   43         movs    r1, #4            
-----------------------------|   44         and.w   r0, r1, r0, lsl #2

[RKSimon]

Hide the fold behind a isDesirableToCommuteXorWithShift TLI override (default - true)

[RKSimon]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

13633

I'm not totally happy that we have all this (duplicated) logic in the arm/aarch64 overrides - an alternative would be to add a 'bool IsPartialMatch' argument?

[dmgreen]

I think it looks OK. LGTM. Thanks for the changes

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   ///
   /// @param N the shift node
   /// @param Level the current DAGCombine legalization level.
   virtual bool isDesirableToCommuteWithShift(const SDNode *N,
                                              CombineLevel Level) const {
     return true;
   }
 
+  /// Return true if it is profitable to combine an XOR of a logical shift
+  /// to create a logical shift of NOT. This transformation may not be desirable
+  /// if it disrupts a particularly auspicious target-specific tree (e.g.
+  /// BIC on ARM/AArch64). By default, it returns true.
+  virtual bool isDesirableToCommuteXorWithShift(const SDNode *N) const {
+    return true;
+  }
+
   /// Return true if the target has native support for the specified value type
   /// and it is 'desirable' to use the type for the given node type. e.g. On x86
   /// i16 is legal, but undesirable since i16 instruction encodings are longer
   /// and some i16 instructions are slow.
   virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
     // By default, assume all legal types are desirable.
     return isTypeLegal(VT);
   }

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (C) {
                 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
           // Don't crash on an oversized shift. We can not guarantee that a
           // bogus shift has been simplified to undef.
           if (ShiftC->getAPIntValue().ult(BitWidth)) {
             uint64_t ShiftAmt = ShiftC->getZExtValue();
             APInt Ones = APInt::getAllOnes(BitWidth);
             Ones = Op0Opcode == ISD::SHL ? Ones.shl(ShiftAmt)
                                          : Ones.lshr(ShiftAmt);
-            if (C->getAPIntValue() == Ones) {
-              // If the xor constant is a shifted -1, do a 'not' before the
+            const TargetLowering &TLI = TLO.DAG.getTargetLoweringInfo();
+            if ((DemandedBits & C->getAPIntValue()) == (DemandedBits & Ones) &&
+                TLI.isDesirableToCommuteXorWithShift(Op.getNode())) {
+              // If the xor constant is a demanded mask, do a 'not' before the
               // shift:
               // xor (X << ShiftC), XorC --> (not X) << ShiftC
               // xor (X >> ShiftC), XorC --> (not X) >> ShiftC
               SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT);
               return TLO.CombineTo(Op, TLO.DAG.getNode(Op0Opcode, dl, VT, Not,
                                                        Op0.getOperand(1)));
             }
           }

llvm/lib/Target/AArch64/AArch64ISelLowering.h

bool generateFMAsInMachineCombiner(EVT VT,
                                      CodeGenOpt::Level OptLevel) const override;
 
   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 
   /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
   bool isDesirableToCommuteWithShift(const SDNode *N,
                                      CombineLevel Level) const override;
 
+  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
+  bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
+
   /// Return true if it is profitable to fold a pair of shifts into a mask.
   bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                          CombineLevel Level) const override;
 
   /// Returns true if it is beneficial to convert a load of a constant
   /// to just the constant itself.
   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                          Type *Ty) const override;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
     if (isMask_64(TruncMask) &&
         ShiftLHS.getOperand(0).getOpcode() == ISD::SRL &&
         isa<ConstantSDNode>(ShiftLHS.getOperand(0).getOperand(1)))
       return false;
   }
   return true;
 }
 
+bool AArch64TargetLowering::isDesirableToCommuteXorWithShift(
+    const SDNode *N) const {
+  assert(N->getOpcode() == ISD::XOR &&
+         (N->getOperand(0).getOpcode() == ISD::SHL ||
+          N->getOperand(0).getOpcode() == ISD::SRL) &&
+         "Expected XOR(SHIFT) pattern");
+
+  // Only commute if the entire NOT mask is a hidden shifted mask.
+  auto *XorC = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1));
+  if (XorC && ShiftC) {
+    unsigned MaskIdx, MaskLen;
+    if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) {
+      unsigned ShiftAmt = ShiftC->getZExtValue();
+      unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
+      if (N->getOperand(0).getOpcode() == ISD::SHL)
+        return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt);
+      return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt);
+    }
+  }
+
+  return false;
+}
+
 bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
     const SDNode *N, CombineLevel Level) const {
   assert(((N->getOpcode() == ISD::SHL &&
            N->getOperand(0).getOpcode() == ISD::SRL) ||
           (N->getOpcode() == ISD::SRL &&
            N->getOperand(0).getOpcode() == ISD::SHL)) &&
          "Expected shift-shift mask");
   // Don't allow multiuse shift folding with the same shift amount.

llvm/lib/Target/ARM/ARMISelLowering.h

public:
 
     /// Return the correct alignment for the current calling convention.
     Align getABIAlignmentForCallingConv(Type *ArgTy,
                                         const DataLayout &DL) const override;
 
     bool isDesirableToCommuteWithShift(const SDNode *N,
                                        CombineLevel Level) const override;
 
+    bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
+
     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                            CombineLevel Level) const override;
 
     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 
     bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
 
   protected:

llvm/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
 
   // Turn off commute-with-shift transform after legalization, so it doesn't
   // conflict with PerformSHLSimplify.  (We could try to detect when
   // PerformSHLSimplify would trigger more precisely, but it isn't
   // really necessary.)
   return false;
 }
 
+bool ARMTargetLowering::isDesirableToCommuteXorWithShift(
+    const SDNode *N) const {
+  assert(N->getOpcode() == ISD::XOR &&
+         (N->getOperand(0).getOpcode() == ISD::SHL ||
+          N->getOperand(0).getOpcode() == ISD::SRL) &&
+         "Expected XOR(SHIFT) pattern");
+
+  // Only commute if the entire NOT mask is a hidden shifted mask.
+  auto *XorC = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *ShiftC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1));
+  if (XorC && ShiftC) {
+    unsigned MaskIdx, MaskLen;
+    if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) {
+      unsigned ShiftAmt = ShiftC->getZExtValue();
+      unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
+      if (N->getOperand(0).getOpcode() == ISD::SHL)
+        return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt);
+      return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt);
+    }
+  }
+
+  return false;
+}
+
 bool ARMTargetLowering::shouldFoldConstantShiftPairToMask(
     const SDNode *N, CombineLevel Level) const {
   assert(((N->getOpcode() == ISD::SHL &&
            N->getOperand(0).getOpcode() == ISD::SRL) ||
           (N->getOpcode() == ISD::SRL &&
            N->getOperand(0).getOpcode() == ISD::SHL)) &&
          "Expected shift-shift mask");
 

llvm/test/CodeGen/Mips/bittest.ll

; MM32R6-NEXT:    jrc $ra
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_16_i32(i32 signext %a) nounwind {
 ; MIPS-LABEL: bittest_16_i32:
 ; MIPS:       # %bb.0:
-; MIPS-NEXT:    srl $1, $4, 16
-; MIPS-NEXT:    not $1, $1
+; MIPS-NEXT:    not $1, $4
+; MIPS-NEXT:    srl $1, $1, 16
 ; MIPS-NEXT:    jr $ra
 ; MIPS-NEXT:    andi $2, $1, 1
 ;
 ; MIPS32R2-LABEL: bittest_16_i32:
 ; MIPS32R2:       # %bb.0:
-; MIPS32R2-NEXT:    srl $1, $4, 16
-; MIPS32R2-NEXT:    not $1, $1
+; MIPS32R2-NEXT:    not $1, $4
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    andi $2, $1, 1
+; MIPS32R2-NEXT:    ext $2, $1, 16, 1
 ;
 ; MIPS32R6-LABEL: bittest_16_i32:
 ; MIPS32R6:       # %bb.0:
-; MIPS32R6-NEXT:    srl $1, $4, 16
-; MIPS32R6-NEXT:    not $1, $1
+; MIPS32R6-NEXT:    not $1, $4
 ; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    andi $2, $1, 1
+; MIPS32R6-NEXT:    ext $2, $1, 16, 1
 ;
 ; MIPS64-LABEL: bittest_16_i32:
 ; MIPS64:       # %bb.0:
-; MIPS64-NEXT:    srl $1, $4, 16
-; MIPS64-NEXT:    not $1, $1
+; MIPS64-NEXT:    not $1, $4
+; MIPS64-NEXT:    srl $1, $1, 16
 ; MIPS64-NEXT:    andi $1, $1, 1
 ; MIPS64-NEXT:    dsll $1, $1, 32
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    dsrl $2, $1, 32
 ;
 ; MIPS64R2-LABEL: bittest_16_i32:
 ; MIPS64R2:       # %bb.0:
-; MIPS64R2-NEXT:    srl $1, $4, 16
-; MIPS64R2-NEXT:    not $1, $1
-; MIPS64R2-NEXT:    andi $1, $1, 1
+; MIPS64R2-NEXT:    not $1, $4
+; MIPS64R2-NEXT:    ext $1, $1, 16, 1
 ; MIPS64R2-NEXT:    jr $ra
 ; MIPS64R2-NEXT:    dext $2, $1, 0, 32
 ;
 ; MIPS64R6-LABEL: bittest_16_i32:
 ; MIPS64R6:       # %bb.0:
-; MIPS64R6-NEXT:    srl $1, $4, 16
-; MIPS64R6-NEXT:    not $1, $1
-; MIPS64R6-NEXT:    andi $1, $1, 1
+; MIPS64R6-NEXT:    not $1, $4
+; MIPS64R6-NEXT:    ext $1, $1, 16, 1
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    dext $2, $1, 0, 32
 ;
 ; MM32R3-LABEL: bittest_16_i32:
 ; MM32R3:       # %bb.0:
-; MM32R3-NEXT:    srl $2, $4, 16
-; MM32R3-NEXT:    not16 $2, $2
-; MM32R3-NEXT:    andi16 $2, $2, 1
-; MM32R3-NEXT:    jrc $ra
+; MM32R3-NEXT:    not16 $2, $4
+; MM32R3-NEXT:    jr $ra
+; MM32R3-NEXT:    ext $2, $2, 16, 1
 ;
 ; MM32R6-LABEL: bittest_16_i32:
 ; MM32R6:       # %bb.0:
-; MM32R6-NEXT:    srl $2, $4, 16
-; MM32R6-NEXT:    not16 $2, $2
-; MM32R6-NEXT:    andi16 $2, $2, 1
+; MM32R6-NEXT:    not16 $2, $4
+; MM32R6-NEXT:    ext $2, $2, 16, 1
 ; MM32R6-NEXT:    jrc $ra
   %shr = lshr i32 %a, 16
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; MM32R6-NEXT:    jrc $ra
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_16_i64(i64 %a) nounwind {
 ; MIPS-LABEL: bittest_16_i64:
 ; MIPS:       # %bb.0:
-; MIPS-NEXT:    srl $1, $5, 16
-; MIPS-NEXT:    not $1, $1
+; MIPS-NEXT:    not $1, $5
+; MIPS-NEXT:    srl $1, $1, 16
 ; MIPS-NEXT:    andi $3, $1, 1
 ; MIPS-NEXT:    jr $ra
 ; MIPS-NEXT:    addiu $2, $zero, 0
 ;
 ; MIPS32R2-LABEL: bittest_16_i64:
 ; MIPS32R2:       # %bb.0:
-; MIPS32R2-NEXT:    srl $1, $5, 16
-; MIPS32R2-NEXT:    not $1, $1
-; MIPS32R2-NEXT:    andi $3, $1, 1
+; MIPS32R2-NEXT:    not $1, $5
+; MIPS32R2-NEXT:    ext $3, $1, 16, 1
 ; MIPS32R2-NEXT:    jr $ra
 ; MIPS32R2-NEXT:    addiu $2, $zero, 0
 ;
 ; MIPS32R6-LABEL: bittest_16_i64:
 ; MIPS32R6:       # %bb.0:
-; MIPS32R6-NEXT:    srl $1, $5, 16
-; MIPS32R6-NEXT:    not $1, $1
-; MIPS32R6-NEXT:    andi $3, $1, 1
+; MIPS32R6-NEXT:    not $1, $5
+; MIPS32R6-NEXT:    ext $3, $1, 16, 1
 ; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    addiu $2, $zero, 0
 ;
 ; MIPS64-LABEL: bittest_16_i64:
 ; MIPS64:       # %bb.0:
-; MIPS64-NEXT:    dsrl $1, $4, 16
-; MIPS64-NEXT:    daddiu $2, $zero, -1
-; MIPS64-NEXT:    xor $1, $1, $2
+; MIPS64-NEXT:    daddiu $1, $zero, -1
+; MIPS64-NEXT:    xor $1, $4, $1
+; MIPS64-NEXT:    dsrl $1, $1, 16
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    andi $2, $1, 1
 ;
 ; MIPS64R2-LABEL: bittest_16_i64:
 ; MIPS64R2:       # %bb.0:
-; MIPS64R2-NEXT:    dsrl $1, $4, 16
-; MIPS64R2-NEXT:    daddiu $2, $zero, -1
-; MIPS64R2-NEXT:    xor $1, $1, $2
+; MIPS64R2-NEXT:    daddiu $1, $zero, -1
+; MIPS64R2-NEXT:    xor $1, $4, $1
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    andi $2, $1, 1
+; MIPS64R2-NEXT:    dext $2, $1, 16, 1
 ;
 ; MIPS64R6-LABEL: bittest_16_i64:
 ; MIPS64R6:       # %bb.0:
-; MIPS64R6-NEXT:    dsrl $1, $4, 16
-; MIPS64R6-NEXT:    daddiu $2, $zero, -1
-; MIPS64R6-NEXT:    xor $1, $1, $2
+; MIPS64R6-NEXT:    daddiu $1, $zero, -1
+; MIPS64R6-NEXT:    xor $1, $4, $1
 ; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    andi $2, $1, 1
+; MIPS64R6-NEXT:    dext $2, $1, 16, 1
 ;
 ; MM32R3-LABEL: bittest_16_i64:
 ; MM32R3:       # %bb.0:
-; MM32R3-NEXT:    srl $2, $5, 16
-; MM32R3-NEXT:    not16 $2, $2
-; MM32R3-NEXT:    andi16 $3, $2, 1
+; MM32R3-NEXT:    not16 $2, $5
+; MM32R3-NEXT:    ext $3, $2, 16, 1
 ; MM32R3-NEXT:    li16 $2, 0
 ; MM32R3-NEXT:    jrc $ra
 ;
 ; MM32R6-LABEL: bittest_16_i64:
 ; MM32R6:       # %bb.0:
-; MM32R6-NEXT:    srl $2, $5, 16
-; MM32R6-NEXT:    not16 $2, $2
-; MM32R6-NEXT:    andi16 $3, $2, 1
+; MM32R6-NEXT:    not16 $2, $5
+; MM32R6-NEXT:    ext $3, $2, 16, 1
 ; MM32R6-NEXT:    li16 $2, 0
 ; MM32R6-NEXT:    jrc $ra
   %shr = lshr i64 %a, 16
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 

 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    not $1, $5
 ; MIPS32R6-NEXT:    srl $3, $1, 31
 ; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    addiu $2, $zero, 0
 ;
 ; MIPS64-LABEL: bittest_31_i64:
 ; MIPS64:       # %bb.0:
-; MIPS64-NEXT:    dsrl $1, $4, 31
-; MIPS64-NEXT:    daddiu $2, $zero, -1
-; MIPS64-NEXT:    xor $1, $1, $2
+; MIPS64-NEXT:    daddiu $1, $zero, -1
+; MIPS64-NEXT:    xor $1, $4, $1
+; MIPS64-NEXT:    dsrl $1, $1, 31
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    andi $2, $1, 1
 ;
 ; MIPS64R2-LABEL: bittest_31_i64:
 ; MIPS64R2:       # %bb.0:
-; MIPS64R2-NEXT:    dsrl $1, $4, 31
-; MIPS64R2-NEXT:    daddiu $2, $zero, -1
-; MIPS64R2-NEXT:    xor $1, $1, $2
+; MIPS64R2-NEXT:    daddiu $1, $zero, -1
+; MIPS64R2-NEXT:    xor $1, $4, $1
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    andi $2, $1, 1
+; MIPS64R2-NEXT:    dext $2, $1, 31, 1
 ;
 ; MIPS64R6-LABEL: bittest_31_i64:
 ; MIPS64R6:       # %bb.0:
-; MIPS64R6-NEXT:    dsrl $1, $4, 31
-; MIPS64R6-NEXT:    daddiu $2, $zero, -1
-; MIPS64R6-NEXT:    xor $1, $1, $2
+; MIPS64R6-NEXT:    daddiu $1, $zero, -1
+; MIPS64R6-NEXT:    xor $1, $4, $1
 ; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    andi $2, $1, 1
+; MIPS64R6-NEXT:    dext $2, $1, 31, 1
 ;
 ; MM32R3-LABEL: bittest_31_i64:
 ; MM32R3:       # %bb.0:
 ; MM32R3-NEXT:    not16 $2, $5
 ; MM32R3-NEXT:    srl $3, $2, 31
 ; MM32R3-NEXT:    li16 $2, 0
 ; MM32R3-NEXT:    jrc $ra
 ;

 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    not $1, $4
 ; MIPS32R6-NEXT:    andi $3, $1, 1
 ; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    addiu $2, $zero, 0
 ;
 ; MIPS64-LABEL: bittest_32_i64:
 ; MIPS64:       # %bb.0:
-; MIPS64-NEXT:    dsrl $1, $4, 32
-; MIPS64-NEXT:    daddiu $2, $zero, -1
-; MIPS64-NEXT:    xor $1, $1, $2
+; MIPS64-NEXT:    daddiu $1, $zero, -1
+; MIPS64-NEXT:    xor $1, $4, $1
+; MIPS64-NEXT:    dsrl $1, $1, 32
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    andi $2, $1, 1
 ;
 ; MIPS64R2-LABEL: bittest_32_i64:
 ; MIPS64R2:       # %bb.0:
-; MIPS64R2-NEXT:    dsrl $1, $4, 32
-; MIPS64R2-NEXT:    daddiu $2, $zero, -1
-; MIPS64R2-NEXT:    xor $1, $1, $2
+; MIPS64R2-NEXT:    daddiu $1, $zero, -1
+; MIPS64R2-NEXT:    xor $1, $4, $1
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    andi $2, $1, 1
+; MIPS64R2-NEXT:    dextu $2, $1, 32, 1
 ;
 ; MIPS64R6-LABEL: bittest_32_i64:
 ; MIPS64R6:       # %bb.0:
-; MIPS64R6-NEXT:    dsrl $1, $4, 32
-; MIPS64R6-NEXT:    daddiu $2, $zero, -1
-; MIPS64R6-NEXT:    xor $1, $1, $2
+; MIPS64R6-NEXT:    daddiu $1, $zero, -1
+; MIPS64R6-NEXT:    xor $1, $4, $1
 ; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    andi $2, $1, 1
+; MIPS64R6-NEXT:    dextu $2, $1, 32, 1
 ;
 ; MM32R3-LABEL: bittest_32_i64:
 ; MM32R3:       # %bb.0:
 ; MM32R3-NEXT:    not16 $2, $4
 ; MM32R3-NEXT:    andi16 $3, $2, 1
 ; MM32R3-NEXT:    li16 $2, 0
 ; MM32R3-NEXT:    jrc $ra
 ;

llvm/test/CodeGen/RISCV/bittest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32,RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64,RV64I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
 
 define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
 ; CHECK-LABEL: bittest_7_i32:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    ret
   %shr = lshr i32 %a, 10
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
-; NOZBS-LABEL: bittest_11_i32:
-; NOZBS:       # %bb.0:
-; NOZBS-NEXT:    srli a0, a0, 11
-; NOZBS-NEXT:    not a0, a0
-; NOZBS-NEXT:    andi a0, a0, 1
-; NOZBS-NEXT:    ret
+; RV32I-LABEL: bittest_11_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    slli a0, a0, 20
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: bittest_11_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    slli a0, a0, 52
+; RV64I-NEXT:    srli a0, a0, 63
+; RV64I-NEXT:    ret
 ;
 ; ZBS-LABEL: bittest_11_i32:
 ; ZBS:       # %bb.0:
+; ZBS-NEXT:    not a0, a0
 ; ZBS-NEXT:    bexti a0, a0, 11
-; ZBS-NEXT:    xori a0, a0, 1
 ; ZBS-NEXT:    ret
   %shr = lshr i32 %a, 11
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; RV64-NEXT:    ret
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_11_i64(i64 %a) nounwind {
 ; RV32I-LABEL: bittest_11_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 11
 ; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    slli a0, a0, 20
+; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_11_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 11
 ; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    slli a0, a0, 52
+; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bittest_11_i64:
 ; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    not a0, a0
 ; RV32ZBS-NEXT:    bexti a0, a0, 11
-; RV32ZBS-NEXT:    xori a0, a0, 1
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_11_i64:
 ; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    not a0, a0
 ; RV64ZBS-NEXT:    bexti a0, a0, 11
-; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 11
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_31_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_31_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a0
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    ret
 ;
-; RV64I-LABEL: bittest_31_i64:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 31
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    ret
-;
-; RV64ZBS-LABEL: bittest_31_i64:
-; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    bexti a0, a0, 31
-; RV64ZBS-NEXT:    xori a0, a0, 1
-; RV64ZBS-NEXT:    ret
+; RV64-LABEL: bittest_31_i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    not a0, a0
+; RV64-NEXT:    srliw a0, a0, 31
+; RV64-NEXT:    ret
   %shr = lshr i64 %a, 31
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_32_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_32_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a1
 ; RV32-NEXT:    andi a0, a0, 1
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_32_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_32_i64:
 ; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    not a0, a0
 ; RV64ZBS-NEXT:    bexti a0, a0, 32
-; RV64ZBS-NEXT:    xori a0, a0, 1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 32
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_63_i64(i64 %a) nounwind {

llvm/test/CodeGen/X86/speculative-load-hardening.ll

 ; X64-NEXT:    callq sink@PLT
 ; X64-NEXT:  .Lslh_ret_addr23:
 ; X64-NEXT:    movq %rsp, %rax
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-NEXT:    sarq $63, %rax
 ; X64-NEXT:    cmpq $.Lslh_ret_addr23, %rcx
 ; X64-NEXT:    cmovneq %r15, %rax
 ; X64-NEXT:    movswl (%rbx), %edi
-; X64-NEXT:    shrl $7, %edi
 ; X64-NEXT:    notl %edi
+; X64-NEXT:    shrl $7, %edi
 ; X64-NEXT:    orl $-65536, %edi # imm = 0xFFFF0000
 ; X64-NEXT:    orl %eax, %edi
 ; X64-NEXT:    shlq $47, %rax
 ; X64-NEXT:    orq %rax, %rsp
 ; X64-NEXT:    callq sink@PLT
 ; X64-NEXT:  .Lslh_ret_addr24:
 ; X64-NEXT:    movq %rsp, %rax
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx

 ; X64-LFENCE-NEXT:    movl (%rbx), %eax
 ; X64-LFENCE-NEXT:    movl (%r14), %ecx
 ; X64-LFENCE-NEXT:    leal 1(%rax,%rcx), %edi
 ; X64-LFENCE-NEXT:    callq sink@PLT
 ; X64-LFENCE-NEXT:    movl (%rbx), %edi
 ; X64-LFENCE-NEXT:    shll $7, %edi
 ; X64-LFENCE-NEXT:    callq sink@PLT
 ; X64-LFENCE-NEXT:    movswl (%rbx), %edi
-; X64-LFENCE-NEXT:    shrl $7, %edi
 ; X64-LFENCE-NEXT:    notl %edi
+; X64-LFENCE-NEXT:    shrl $7, %edi
 ; X64-LFENCE-NEXT:    orl $-65536, %edi # imm = 0xFFFF0000
 ; X64-LFENCE-NEXT:    callq sink@PLT
 ; X64-LFENCE-NEXT:    movzwl (%rbx), %eax
 ; X64-LFENCE-NEXT:    rolw $9, %ax
 ; X64-LFENCE-NEXT:    movswl %ax, %edi
 ; X64-LFENCE-NEXT:    negl %edi
 ; X64-LFENCE-NEXT:    callq sink@PLT
 ; X64-LFENCE-NEXT:    addq $8, %rsp