[DirectX] add thread/group id DXIL operations.

[python3kgae]

Summary

Add DXIL operation for thread/group id operations.

ID Name Description
93 ThreadId reads the thread ID
94 GroupId reads the group ID (SV_GroupID)
95 ThreadIdInGroup reads the thread ID within the group (SV_GroupThreadID)
96 FlattenedThreadIdInGroup provides a flattened index for a given thread within a given group (SV_GroupIndex)

Also add llvm intrinsic which map to these intrinsics to DXIL operation.

[beanz]

llvm/include/llvm/IR/IntrinsicsDXIL.td

15 ↗

(On Diff #437605)

nit: by convention in LLVM intrinsics are generally lower-case _ separated words.

[python3kgae]

Change intrinsic start with lower case.

[python3kgae]

llvm/include/llvm/IR/IntrinsicsDXIL.td

15 ↗

(On Diff #437605)

Fixed.

[beanz]

llvm/include/llvm/IR/IntrinsicsDXIL.td

15 ↗

(On Diff #437605)

_ separated, not camel case. group_id rather than groupId would be the convention.

[python3kgae]

Use _ for the whole name.

[python3kgae]

llvm/include/llvm/IR/IntrinsicsDXIL.td

15 ↗

(On Diff #437605)

Fixed.

[python3kgae]

Fix test.

[beanz]

Two small nits. Otherwise, looks good.

llvm/include/llvm/IR/IntrinsicsDXIL.td

1 ↗

(On Diff #437671)

We should name this file IntrinsicsDirectX.td not DXIL since it will be all the target intrinsics, and the header should be updated accordingly.

9 ↗

(On Diff #437671)

This should be DirectX-specific not R600 :)

[python3kgae]

Rename IntrinsicsDXIL to IntrinsicsDirectX.

[beanz]

I'm pretty sure you need to include IntrinsicsDirectX.h in Function.cpp for this to compile, otherwise this patch looks good to me.

[python3kgae]

include IntrinsicsDirectX.h in Function.cpp

[MaskRay]

I don't know the format, so I just make some random style related comments.

llvm/test/CodeGen/DirectX/comput_ids.ll

9

Ensure @ and ( are present.

13

add a space after :

llvm/include/llvm/IR/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Attributes.td)
 tablegen(LLVM Attributes.inc -gen-attrs)
 
 set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
 tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
 tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
 tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
 tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
 tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
 tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
+tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dxil)
 tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
 tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
 tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
 tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
 tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600)
 tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv)
 tablegen(LLVM IntrinsicsSPIRV.h -gen-intrinsic-enums -intrinsic-prefix=spv)
 tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390)
 tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm)
 tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86)
 tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore)
 tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve)
 add_public_tablegen_target(intrinsics_gen)

llvm/include/llvm/IR/Intrinsics.td

 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsAMDGPU.td"
 include "llvm/IR/IntrinsicsBPF.td"
 include "llvm/IR/IntrinsicsSystemZ.td"
 include "llvm/IR/IntrinsicsWebAssembly.td"
 include "llvm/IR/IntrinsicsRISCV.td"
 include "llvm/IR/IntrinsicsSPIRV.td"
 include "llvm/IR/IntrinsicsVE.td"
+include "llvm/IR/IntrinsicsDirectX.td"

llvm/include/llvm/IR/IntrinsicsDirectX.td

+//===- IntrinsicsDirectX.td - Defines DirectX intrinsics ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the DirectX-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "dxil" in {
+
+def int_dxil_thread_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
+def int_dxil_group_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
+def int_dxil_thread_id_in_group : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
+def int_dxil_flattened_thread_id_in_group : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrWillReturn]>;
+
+}

llvm/lib/IR/Function.cpp

 #include "llvm/IR/InstIterator.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsAArch64.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/IR/IntrinsicsBPF.h"
+#include "llvm/IR/IntrinsicsDirectX.h"
 #include "llvm/IR/IntrinsicsHexagon.h"
 #include "llvm/IR/IntrinsicsMips.h"
 #include "llvm/IR/IntrinsicsNVPTX.h"
 #include "llvm/IR/IntrinsicsPowerPC.h"
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/IR/IntrinsicsS390.h"
 #include "llvm/IR/IntrinsicsVE.h"

llvm/lib/Target/DirectX/DXIL.td

class dxil_class<string _name> {
   string name = _name;
 }
 class dxil_category<string _name> {
   string name = _name;
 }
 
 def Unary : dxil_class<"Unary">;
 def Binary : dxil_class<"Binary">;
+def FlattenedThreadIdInGroupClass : dxil_class<"FlattenedThreadIdInGroup">;
+def ThreadIdInGroupClass : dxil_class<"ThreadIdInGroup">;
+def ThreadIdClass : dxil_class<"ThreadId">;
+def GroupIdClass : dxil_class<"GroupId">;
 
 def binary_uint : dxil_category<"Binary uint">;
 def unary_float : dxil_category<"Unary float">;
-
+def ComputeID : dxil_category<"Compute/Mesh/Amplification shader">;
 
 
 // The parameter description for a DXIL instruction
 class dxil_param<int _pos, string type, string _name, string _doc,
                  bit _is_const = 0, string _enum_name = "",
                  int _max_value = 0> {
   int pos = _pos;           // position in parameter list
   string llvm_type = type; // llvm type name, $o for overload, $r for resource
def UMax :dxil_op< "UMax", 39,  Binary,  binary_uint, "unsigned integer maximum. UMax(a,b) = a > b ? a : b",
   [
     dxil_param<0,  "$o",  "",  "operation result">,
     dxil_param<1,  "i32",  "opcode",  "DXIL opcode">,
     dxil_param<2,  "$o",  "a",  "input value">,
     dxil_param<3,  "$o",  "b",  "input value">
   ],
   ["uints"]>,
   dxil_map_intrinsic<int_umax>;
+
+def ThreadId :dxil_op< "ThreadId", 93,  ThreadIdClass, ComputeID, "reads the thread ID", "i32;",  "rn",
+  [
+    dxil_param<0,  "i32",  "",  "thread ID component">,
+    dxil_param<1,  "i32",  "opcode",  "DXIL opcode">,
+    dxil_param<2,  "i32",  "component",  "component to read (x,y,z)">
+  ]>,
+  dxil_map_intrinsic<int_dxil_thread_id>;
+
+def GroupId :dxil_op< "GroupId", 94,  GroupIdClass, ComputeID, "reads the group ID (SV_GroupID)", "i32;",  "rn",
+  [
+    dxil_param<0,  "i32",  "",  "group ID component">,
+    dxil_param<1,  "i32",  "opcode",  "DXIL opcode">,
+    dxil_param<2,  "i32",  "component",  "component to read">
+  ]>,
+  dxil_map_intrinsic<int_dxil_group_id>;
+
+def ThreadIdInGroup :dxil_op< "ThreadIdInGroup", 95,  ThreadIdInGroupClass, ComputeID,
+  "reads the thread ID within the group (SV_GroupThreadID)", "i32;",  "rn",
+  [
+    dxil_param<0,  "i32",  "",  "thread ID in group component">,
+    dxil_param<1,  "i32",  "opcode",  "DXIL opcode">,
+    dxil_param<2,  "i32",  "component",  "component to read (x,y,z)">
+  ]>,
+  dxil_map_intrinsic<int_dxil_thread_id_in_group>;
+
+def FlattenedThreadIdInGroup :dxil_op< "FlattenedThreadIdInGroup", 96,  FlattenedThreadIdInGroupClass, ComputeID,
+   "provides a flattened index for a given thread within a given group (SV_GroupIndex)", "i32;",  "rn",
+  [
+    dxil_param<0,  "i32",  "",  "result">,
+    dxil_param<1,  "i32",  "opcode",  "DXIL opcode">
+  ]>,
+  dxil_map_intrinsic<int_dxil_flattened_thread_id_in_group>;

llvm/lib/Target/DirectX/DXILOpLowering.cpp

 
 #include "DXILConstants.h"
 #include "DirectX.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/IntrinsicsDirectX.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/PassManager.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define DEBUG_TYPE "dxil-op-lower"
 
 using namespace llvm;

llvm/test/CodeGen/DirectX/comput_ids.ll

+; RUN: opt -S -dxil-op-lower < %s | FileCheck %s
+
+; Make sure dxil operation function calls for all ComputeID dxil operations are generated.
+
+target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
+target triple = "dxil-pc-shadermodel6.7-library"
+
+; CHECK-LABEL:test_thread_id
+; Function Attrs: noinline nounwind optnone
+define i32 @test_thread_id(i32 %a) #0 {
+entry:
+; CHECK:call i32 @dx.op.threadId.i32(i32 93, i32 %{{.*}})
+  %0 = call i32 @llvm.dxil.thread.id(i32 %a)
+  ret i32 %0
+}
+
+; CHECK-LABEL:test_group_id
+; Function Attrs: noinline nounwind optnone
+define i32 @test_group_id(i32 %a) #0 {
+entry:
+; CHECK:call i32 @dx.op.groupId.i32(i32 94, i32 %{{.*}})
+  %0 = call i32 @llvm.dxil.group.id(i32 %a)
+  ret i32 %0
+}
+
+; CHECK-LABEL:test_thread_id_in_group
+; Function Attrs: noinline nounwind optnone
+define i32 @test_thread_id_in_group(i32 %a) #0 {
+entry:
+; CHECK:call i32 @dx.op.threadIdInGroup.i32(i32 95, i32 %{{.*}})
+  %0 = call i32 @llvm.dxil.thread.id.in.group(i32 %a)
+  ret i32 %0
+}
+
+; CHECK-LABEL:test_flattened_thread_id_in_group
+; Function Attrs: noinline nounwind optnone
+define i32 @test_flattened_thread_id_in_group() #0 {
+entry:
+; CHECK:call i32 @dx.op.flattenedThreadIdInGroup.i32(i32 96)
+  %0 = call i32 @llvm.dxil.flattened.thread.id.in.group()
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone willreturn
+declare i32 @llvm.dxil.thread.id(i32) #1
+declare i32 @llvm.dxil.group.id(i32) #1
+declare i32 @llvm.dxil.flattened.thread.id.in.group() #1
+declare i32 @llvm.dxil.thread.id.in.group(i32) #1
+
+attributes #0 = { noinline nounwind }
+attributes #1 = { nounwind readnone willreturn }