Found a fun little bug whereby the phys vgprs were being coalesced onto previous instructions, and then shouldClusterMemOps was assuming only virt regs. Added a workaround for that.

Update for two reasons:

Fix review comments.

Added the max3 cases too.

Changed it to a whitelist of types rather than a blacklist (much better idea).

Fixed review comments by Matt and added the extra test cases that were a great idea!

Reduce the number of DPP calls in the test for cleanliness, and reintroduce the convergent on WWM. The CFG test contains the bug that was exposed by the lack of convergent on WWM, LLVM will sink the WWM statement out of the branch which totally messes up all calculations.

Remove the explicit pass name.

Addressed all review comments.

Add a test case that triggers the target transform info code path.

LGTM.

LGTM.

In D57737#1392667, @tpr wrote:

But I still don't understand it:

1. Why do you want an exclusive scan? Surely what you're trying to do is just "sum" up all lanes into lane 63, which is an inclusive scan.

Fix comment that should now say exclusive scan instead of inclusive scan.

Make the final readlane be in the WWM section too as per the review comments.

Updated to bring in an additional fix to remove read_register exec and replace it with a ballot.

Fixed review comments.

Fix review comments.

Review comments.

Also tag s.getpc as scalar, and add tests in the Analysis folder like suggested.

@arsenm agreed - not quite sure how to do tests for this? I started to look at how we test alias analysis, and they have a cl::opt to force print the debug info for that pass, and that is how our amdgpu-alias-analysis.ll tests the aliasing rules. How exactly to test that divergence analysis did something here?

@cwabbott I planned to do a followup once this DPP change had landed to add the missing dpp/codegen patterns to the atomic optimizer - so watch this space!

Fix review comment.

Fix review comments.

@nhaehnle I've removed canReadVGPR as it only had the single callsite - but given @arsenm's comment I did not change getOpRegClass. I also don't feel super comfortable doing the change you suggested to addUsersToMoveToVALUWorklist as I'm worried that there will be non-LLVM-tested paths that I could trip up on with ease. I'd rather ship the commit as is if y'all are ok with it.

Removed canReadVGPR as it had only a single callsite.

Made the l1 flush change happen for MESA3D too (like Nicolai asked for).

Fixed review comments:

We discussed this on an internal AMD meeting Monday 5th November 2018, and came to the conclusion that even though I do want the scalar load combining to be brought upstream, it would be better as a separate change so that we can get broader testing across the users of our AMDGPU backend.

Fix review comments made by @nhaehnle

Review fixes.

Added an additional lit test for the dim variants (including the 2darraymsaa requested by @nhaehnle), and change the naming of the a16.d16 tests to vNf16.