The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.
Details
Diff Detail
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- rG LLVM Github Monorepo
Unit Tests
Event Timeline
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | ||
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232 | Checking isHalfTy rather than isBFloatTy here, isBFloatTy is bfloat type and we don't support that in any extension yet. |
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll | ||
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22–23 | Curious why there is still GPRRC here? I thought that should be FPRRC after this patch? |
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll | ||
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22–23 | Here is the register usage after VF is selected, all float types in this loop has been changed to the vector type after vectorization. |
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll | ||
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22–23 | Yeah, make sense, does it possible to add some testcase to show FPRRC? |
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll | ||
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22–23 | Yeah, it's very simple. Just set VF to 1 to show FPRRC. |
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | ||
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213 | Checking F is enough here since Zfh and D both implied F. |
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | ||
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213 | okey |
Sorry I didn't notice. I have submitted it.
You could create another NFC patch to address @frasercrmck's comment :)
Checking F is enough here since Zfh and D both implied F.