[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly

[eopXD]

Summary

Originally, OptLevel isn't passed into the MachineFunctionPass.
This lets the default parameter of SelectionDAGISel, which is
CodeGenOpt::Default, be passed in. OptLevelChanger captures the
optimization level with the parameter, and rather not the value
within TargetMachine. This lets the optimization be
unintentionally overwriten if other value than CodeGenOpt::Default
passed.

This patch fixes this by passing the optimization level rather
than using the default value.

[eopXD]

Created pre-commit test case D126677, will rebase upon it to reflect the change.

[craig.topper]

I see that this is how many other targets do it. It would have been helpful to mention that in the description so we immediately know you're not inventing something new.

LGTM

[eopXD]

Rebase and show bug fix.

[eopXD]

Update checks for CodeGen/RISCV/O0-pipeline.ll.

Now the correct optimization level is recovered, some passes should not be executed.

[eopXD]

In D126641#3546498, @craig.topper wrote:

I see that this is how many other targets do it. It would have been helpful to mention that in the description so we immediately know you're not inventing something new.

LGTM

Yes you are right, I could have done better explaining my patch.
I will try to mention how other targets do to bring in the context.
Thank you for the swift review.

[jrtc27]

In D126641#3546557, @eopXD wrote:

In D126641#3546498, @craig.topper wrote:

I see that this is how many other targets do it. It would have been helpful to mention that in the description so we immediately know you're not inventing something new.

LGTM

Yes you are right, I could have done better explaining my patch.
I will try to mention how other targets do to bring in the context.
Thank you for the swift review.

The commit message was identical to the original review summary?..

[eopXD]

In D126641#3546557, @eopXD wrote:

In D126641#3546498, @craig.topper wrote:

I see that this is how many other targets do it. It would have been helpful to mention that in the description so we immediately know you're not inventing something new.

LGTM

Yes you are right, I could have done better explaining my patch.
I will try to mention how other targets do to bring in the context.
Thank you for the swift review.

What I meant is I will explain things better in the future.

llvm/lib/Target/RISCV/RISCV.h

 class MachineOperand;
 class PassRegistry;
 
 bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP);
 bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
                                          MCOperand &MCOp, const AsmPrinter &AP);
 
-FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
+FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
+                                 CodeGenOpt::Level OptLevel);
 
 FunctionPass *createRISCVMakeCompressibleOptPass();
 void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
 
 FunctionPass *createRISCVGatherScatterLoweringPass();
 void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
 
 FunctionPass *createRISCVSExtWRemovalPass();

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

 
 // RISCV-specific code to select RISCV machine instructions for
 // SelectionDAG operations.
 namespace llvm {
 class RISCVDAGToDAGISel : public SelectionDAGISel {
   const RISCVSubtarget *Subtarget = nullptr;
 
 public:
-  explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
-      : SelectionDAGISel(TargetMachine) {}
+  explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
+                             CodeGenOpt::Level OptLevel)
+      : SelectionDAGISel(TargetMachine, OptLevel) {}
 
   StringRef getPassName() const override {
     return "RISCV DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<RISCVSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(SDNode *N) {
   SDNode *Result = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
   ReplaceUses(N, Result);
 
   return true;
 }
 
 // This pass converts a legalized DAG into a RISCV-specific DAG, ready
 // for instruction scheduling.
-FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) {
-  return new RISCVDAGToDAGISel(TM);
+FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
+                                       CodeGenOpt::Level OptLevel) {
+  return new RISCVDAGToDAGISel(TM, OptLevel);
 }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

if (TM->getOptLevel() != CodeGenOpt::None) {
     // deleted block address after enabling default outlining. See D99707 for
     // more details.
     addPass(createBarrierNoopPass());
   }
   return false;
 }
 
 bool RISCVPassConfig::addInstSelector() {
-  addPass(createRISCVISelDag(getRISCVTargetMachine()));
+  addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
 
   return false;
 }
 
 bool RISCVPassConfig::addIRTranslator() {
   addPass(new IRTranslator(getOptLevel()));
   return false;
 }

llvm/test/CodeGen/RISCV/O0-pipeline.ll

 ; CHECK-NEXT:       Remove unreachable blocks from the CFG
 ; CHECK-NEXT:       Expand vector predication intrinsics
 ; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors
 ; CHECK-NEXT:       Module Verifier
-; CHECK-NEXT:       Basic Alias Analysis (stateless AA impl)
-; CHECK-NEXT:       Function Alias Analysis Results
-; CHECK-NEXT:       Natural Loop Information
-; CHECK-NEXT:       Post-Dominator Tree Construction
-; CHECK-NEXT:       Branch Probability Analysis
-; CHECK-NEXT:       Lazy Branch Probability Analysis
-; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       RISCV DAG->DAG Pattern Instruction Selection
 ; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation
 ; CHECK-NEXT:       RISCV Insert VSETVLI pass
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
 ; CHECK-NEXT:       Fast Register Allocator
 ; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis

llvm/test/CodeGen/RISCV/isel-optnone.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -O0 -mtriple=riscv64 -debug-only=isel 2>&1 | FileCheck %s
 
 define i32* @fooOptnone(i32* %p, i32* %q, i32** %z) #0 {
-; CHECK: Changing optimization level for Function fooOptnone
-; CHECL: Before: -O2 ; After: -O0
+; CHECK-NOT: Changing optimization level for Function fooOptnone
+; CHECK-NOT: Restoring optimization level for Function fooOptnone
 
-; CHECK: Restoring optimization level for Function fooOptnone
-; CHECK: Before: -O0 ; After: -O2
 entry:
   %r = load i32, i32* %p
   %s = load i32, i32* %q
   %y = load i32*, i32** %z
 
   %t0 = add i32 %r, %s
   %t1 = add i32 %t0, 1
   %t2 = getelementptr i32, i32* %y, i32 1
   %t3 = getelementptr i32, i32* %t2, i32 %t1
 
   ret i32* %t3
 
 }
 
 attributes #0 = { nounwind optnone noinline }