[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

[craig.topper]

Summary

This bug is in generic DAG combine and easily reproducible on many
targets.

[david-arm]

LGTM!

llvm/test/CodeGen/AArch64/arm64-rev.ll

956

Yep, that looks wrong!

llvm/test/CodeGen/AArch64/arm64-rev.ll

entry:
   %2 = shl i64 %a, 8
   %3 = or i64 %1, %2
   %4 = and i64 %2, 1095216660480
   %5 = or i64 %3, %4
   %6 = and i64 %0, 16711680
   %7 = or i64 %5, %6
   ret i64 %7
 }
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev w8, w0
+; CHECK-NEXT:    asr w0, w8, #16
+; CHECK-NEXT:    ret
+;
+; GISEL-LABEL: pr55484:
+; GISEL:       // %bb.0:
+; GISEL-NEXT:    lsl w8, w0, #8
+; GISEL-NEXT:    orr w8, w8, w0, lsr #8
+; GISEL-NEXT:    sxth w0, w8
+; GISEL-NEXT:    ret
+  %2 = lshr i32 %0, 8
+  %3 = shl i32 %0, 8
+  %4 = or i32 %2, %3
+  %5 = trunc i32 %4 to i16
+  %6 = sext i16 %5 to i32
+  ret i32 %6
+}

llvm/test/CodeGen/ARM/rev.ll

 ; CHECK-LABEL: test10:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    rev16 r0, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %conv3 = call i16 @llvm.bswap.i16(i16 %v)
   ret i16 %conv3
 }
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
+  %2 = lshr i32 %0, 8
+  %3 = shl i32 %0, 8
+  %4 = or i32 %2, %3
+  %5 = trunc i32 %4 to i16
+  %6 = sext i16 %5 to i32
+  ret i32 %6
+}

llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

 ; RV64ZBP-LABEL: test_bitreverse_bswap_i64:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    rev.b a0, a0
 ; RV64ZBP-NEXT:    ret
   %tmp = call i64 @llvm.bitreverse.i64(i64 %a)
   %tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
   ret i64 %tmp2
 }
+
+define i32 @pr55484(i32 %0) {
+; RV32I-LABEL: pr55484:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a1, a0, 8
+; RV32I-NEXT:    slli a0, a0, 8
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srai a0, a0, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: pr55484:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a1, a0, 8
+; RV64I-NEXT:    slli a0, a0, 8
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srai a0, a0, 48
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: pr55484:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    rev8 a0, a0
+; RV32ZBB-NEXT:    srai a0, a0, 16
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: pr55484:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    rev8 a0, a0
+; RV64ZBB-NEXT:    srai a0, a0, 48
+; RV64ZBB-NEXT:    ret
+;
+; RV32ZBKB-LABEL: pr55484:
+; RV32ZBKB:       # %bb.0:
+; RV32ZBKB-NEXT:    srli a1, a0, 8
+; RV32ZBKB-NEXT:    slli a0, a0, 8
+; RV32ZBKB-NEXT:    or a0, a1, a0
+; RV32ZBKB-NEXT:    slli a0, a0, 16
+; RV32ZBKB-NEXT:    srai a0, a0, 16
+; RV32ZBKB-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pr55484:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    srli a1, a0, 8
+; RV64ZBKB-NEXT:    slli a0, a0, 8
+; RV64ZBKB-NEXT:    or a0, a1, a0
+; RV64ZBKB-NEXT:    slli a0, a0, 48
+; RV64ZBKB-NEXT:    srai a0, a0, 48
+; RV64ZBKB-NEXT:    ret
+;
+; RV32ZBP-LABEL: pr55484:
+; RV32ZBP:       # %bb.0:
+; RV32ZBP-NEXT:    srli a1, a0, 8
+; RV32ZBP-NEXT:    slli a0, a0, 8
+; RV32ZBP-NEXT:    or a0, a1, a0
+; RV32ZBP-NEXT:    slli a0, a0, 16
+; RV32ZBP-NEXT:    srai a0, a0, 16
+; RV32ZBP-NEXT:    ret
+;
+; RV64ZBP-LABEL: pr55484:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    srli a1, a0, 8
+; RV64ZBP-NEXT:    slli a0, a0, 8
+; RV64ZBP-NEXT:    or a0, a1, a0
+; RV64ZBP-NEXT:    slli a0, a0, 48
+; RV64ZBP-NEXT:    srai a0, a0, 48
+; RV64ZBP-NEXT:    ret
+  %2 = lshr i32 %0, 8
+  %3 = shl i32 %0, 8
+  %4 = or i32 %2, %3
+  %5 = trunc i32 %4 to i16
+  %6 = sext i16 %5 to i32
+  ret i32 %6
+}

llvm/test/CodeGen/Thumb/rev.ll

entry:
   %shr9 = lshr i16 %a, 8
   %conv2 = zext i16 %shr9 to i32
   %shl = shl nuw nsw i32 %conv, 8
   %or = or i32 %conv2, %shl
   %sext = shl i32 %or, 16
   %conv8 = ashr exact i32 %sext, 16
   ret i32 %conv8
 }
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    revsh r0, r0
+; CHECK-NEXT:    bx lr
+  %2 = lshr i32 %0, 8
+  %3 = shl i32 %0, 8
+  %4 = or i32 %2, %3
+  %5 = trunc i32 %4 to i16
+  %6 = sext i16 %5 to i32
+  ret i32 %6
+}

llvm/test/CodeGen/X86/bswap.ll

 ; CHECK64-NEXT:    movq %r10, (%rax)
 ; CHECK64-NEXT:    movw %si, 64(%rax)
 ; CHECK64-NEXT:    popq %rbx
 ; CHECK64-NEXT:    retq
   %Z = call i528 @llvm.bswap.i528(i528 %A)
   ret i528 %Z
 }
 declare i528 @llvm.bswap.i528(i528)
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    bswapl %eax
+; CHECK-NEXT:    sarl $16, %eax
+; CHECK-NEXT:    retl
+;
+; CHECK64-LABEL: pr55484:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    movl %edi, %eax
+; CHECK64-NEXT:    bswapl %eax
+; CHECK64-NEXT:    sarl $16, %eax
+; CHECK64-NEXT:    retq
+  %2 = lshr i32 %0, 8
+  %3 = shl i32 %0, 8
+  %4 = or i32 %2, %3
+  %5 = trunc i32 %4 to i16
+  %6 = sext i16 %5 to i32
+  ret i32 %6
+}