Skip to insert vsetvli if SEWLMULRatio had not been chagned.
Vector mask logical instructions are always unmasked and always updated
with a tail-agnostic policy.
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| Differential D124833
[RISCV] Optimize redundant vsetvli for Vector Mask-Register Logical Instructions. AbandonedPublic Authored by khchen on May 3 2022, 2:22 AM.
Details Summary Skip to insert vsetvli if SEWLMULRatio had not been chagned. Vector mask logical instructions are always unmasked and always updated
Diff Detail
Event TimelineComment Actions Sorry for not seeing/ignoring this for so long. Rebase needed. The basic structure of your patch makes sense, but can I suggest that you split this into two patches. The first isn't specific to logical mask ops at all. It would handle instructions with fixed policy bits generically. These instructions don't have policy ops, which means the existing computeInfoForInstr code which just pick some default. I think you can write a generic change which uses usesMaskPolicy and doesForceTailAgnostic to allow the tail policy difference in needVSETVLI. The second patch is basically this one, but with clear comments about the VL interaction and reusing the generic bit from patch one for the policy handling.
This revision now requires changes to proceed.Jun 3 2022, 10:42 AM
Revision Contents
Diff 426610 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
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default: return false? Then we don't need IsMaskLogicalOp