[DAGCombiner] Scalarize extend/truncate for splat vector.

[jacquesguan]

Summary

This revision scalarizes extend/truncate for splat vector.

[RKSimon]

llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll

28 ↗

(On Diff #419646)

Any luck with these regressions?

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

2–3

You need to re-add triple specific checks now that some of these test results diverge

; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

437

I don't think UnOp is the right term here. UnaryOperator in IR is the base clang used by fneg. CastOp would probably be better.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

437

Done, thanks.

llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll

28 ↗

(On Diff #419646)

Done, thanks.

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

2–3

Done, thanks.

[RKSimon]

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

548

regressions?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

548

RISC-V is weak on scalar zero extend in the base ISA. We get a zext.w operation with the Zba extension. On the vector side a widening vwsub.wx is probably more expensive than a non-widening vsub.vx

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

23537

Should we be extracting from a SPLAT_VECTOR node like this or should we be accessing (and maybe truncating?) the N0.getOperand(0) directly?

[jacquesguan]

rebase.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

23537

Thanks, I changed it to the latter one.

[jacquesguan]

ping

[frasercrmck]

Sorry, I'm a bit rusty. What happens with the equivalent fixed-length vector splats (BUILD_VECTOR)? If they're scalarized can we do the same for SPLAT_VECTOR in the same place? If they're not scalarized, what's the logic for only doing this transform for SPLAT_VECTOR?

[jacquesguan]

rebase main and address comment.

[jacquesguan]

In D122875#3467800, @frasercrmck wrote:

Sorry, I'm a bit rusty. What happens with the equivalent fixed-length vector splats (BUILD_VECTOR)? If they're scalarized can we do the same for SPLAT_VECTOR in the same place? If they're not scalarized, what's the logic for only doing this transform for SPLAT_VECTOR?

I changed some code to support other kinds splat.

[jacquesguan]

ping.

[jacquesguan]

ping.

[jacquesguan]

ping.

[RKSimon]

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

33

Still a regression - can RISCV64 really not be coaxed into generating something better?

[jacquesguan]

Disable salarize sign_ext and zero_ext for RISCV target.

[jacquesguan]

Fix test.

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

33

In order to generate widening instruction, I disable scalarizing of sign_ext and zero_ext, because the scalar type integer extention is easy to combine with other node, make it won't match the pattern.

[RKSimon]

cheers - its up to the RISCV guys as to whether this is acceptable (and whether it should be pulled out as a parent patch?)

[jacquesguan]

In D122875#3731428, @RKSimon wrote:

cheers - its up to the RISCV guys as to whether this is acceptable (and whether it should be pulled out as a parent patch?)

@craig.topper @frasercrmck What do you about this way, or any advice?

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

33

Do you think there's any way to fix it?

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

33

I think if we change the widen pattern to DAG combiner, maybe could generte some, but common DAG folder may fold extend to for others example: ext_inreg firstly. So more condition we need to consider

[jacquesguan]

ping.

[jacquesguan]

ping.

[RKSimon]

@frasercrmck @craig.topper - any more comments?

[RKSimon]

LGTM - cheers

[RKSimon]

@jacquesguan Please can you take a look at https://github.com/llvm/llvm-project/issues/62234 thats related to this patch?

[jacquesguan]

In D122875#4280169, @RKSimon wrote:

@jacquesguan Please can you take a look at https://github.com/llvm/llvm-project/issues/62234 thats related to this patch?

OK.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitUMUL_LOHI(SDNode *N);
     SDValue visitMULO(SDNode *N);
     SDValue visitIMINMAX(SDNode *N);
     SDValue visitAND(SDNode *N);
     SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
     SDValue visitOR(SDNode *N);
     SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
     SDValue visitXOR(SDNode *N);
+    SDValue SimplifyVCastOp(SDNode *N, const SDLoc &DL);
     SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL);
     SDValue visitSHL(SDNode *N);
     SDValue visitSRA(SDNode *N);
     SDValue visitSRL(SDNode *N);
     SDValue visitFunnelShift(SDNode *N);
     SDValue visitSHLSAT(SDNode *N);
     SDValue visitRotate(SDNode *N);
     SDValue visitABS(SDNode *N);
SDValue DAGCombiner::foldSextSetcc(SDNode *N) {
   return SDValue();
 }
 
 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
+  if (VT.isVector())
+    if (SDValue FoldedVOp = SimplifyVCastOp(N, DL))
+      return FoldedVOp;
+
   // sext(undef) = 0 because the top bit will all be the same.
   if (N0.isUndef())
     return DAG.getConstant(0, DL, VT);
 
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
   // fold (sext (sext x)) -> (sext x)
static SDValue widenCtPop(SDNode *Extend, SelectionDAG &DAG) {
   SDValue NewZext = DAG.getZExtOrTrunc(CtPop.getOperand(0), DL, VT);
   return DAG.getNode(ISD::CTPOP, DL, VT, NewZext);
 }
 
 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
+  if (VT.isVector())
+    if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N)))
+      return FoldedVOp;
+
   // zext(undef) = 0
   if (N0.isUndef())
     return DAG.getConstant(0, SDLoc(N), VT);
 
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
   // fold (zext (zext x)) -> (zext x)
SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
+  if (VT.isVector())
+    if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N)))
+      return FoldedVOp;
+
   // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
   if (N->hasOneUse() &&
       N->use_begin()->getOpcode() == ISD::FP_ROUND)
     return SDValue();
 
   // fold (fp_extend c1fp) -> c1fp
   if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
     return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
 
   // bo (splat X, Index), (splat Y, Index) --> splat (bo X, Y), Index
   if (VT.isScalableVector())
     return DAG.getSplatVector(VT, DL, ScalarBO);
   SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
   return DAG.getBuildVector(VT, DL, Ops);
 }
 
+/// Visit a vector cast operation, like FP_EXTEND.
+SDValue DAGCombiner::SimplifyVCastOp(SDNode *N, const SDLoc &DL) {
+  EVT VT = N->getValueType(0);
+  assert(VT.isVector() && "SimplifyVCastOp only works on vectors!");
+  EVT EltVT = VT.getVectorElementType();
+  unsigned Opcode = N->getOpcode();
+
+  SDValue N0 = N->getOperand(0);
+  EVT SrcVT = N0->getValueType(0);
+  EVT SrcEltVT = SrcVT.getVectorElementType();
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+
+  // TODO: promote operation might be also good here?
+  int Index0;
+  SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
+  if (Src0 &&
+      (N0.getOpcode() == ISD::SPLAT_VECTOR ||
+       TLI.isExtractVecEltCheap(VT, Index0)) &&
+      TLI.isOperationLegalOrCustom(Opcode, EltVT)) {
+    SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL);
+    SDValue Elt =
+        DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcEltVT, Src0, IndexC);
+    SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags());
+    if (VT.isScalableVector())
+      return DAG.getSplatVector(VT, DL, ScalarBO);
+    SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
+    return DAG.getBuildVector(VT, DL, Ops);
+  }
+
+  return SDValue();
+}
+
 /// Visit a binary vector operation, like ADD.
 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N, const SDLoc &DL) {
   EVT VT = N->getValueType(0);
   assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
 
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   unsigned Opcode = N->getOpcode();

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
                                     (vti.Mask true_mask), (XLenVT srcvalue))),
                    (wti.Vector (riscv_fpextend_vl_oneuse
                                     (vti.Vector vti.RegClass:$rs2),
                                     (vti.Mask true_mask), (XLenVT srcvalue))),
                    (wti.Vector wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
-                                    (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                                    (vti.Mask true_mask), (XLenVT srcvalue))),
+    def : Pat<(fma (wti.Vector (SplatFPOp
+                                    (fpext_oneuse vti.ScalarRegClass:$rs1))),
                    (wti.Vector (riscv_fpextend_vl_oneuse
                                     (vti.Vector vti.RegClass:$rs2),
                                     (vti.Mask true_mask), (XLenVT srcvalue))),
                    (wti.Vector wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
 multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
   foreach vtiToWti = AllWidenableFloatVectors in {
     defvar vti = vtiToWti.Vti;
     defvar wti = vtiToWti.Wti;
     def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
                                           (vti.Vector vti.RegClass:$rs1),
                                           (vti.Mask true_mask), (XLenVT srcvalue)))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    (fneg wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (riscv_fpextend_vl_oneuse
-                        (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                        (vti.Mask true_mask), (XLenVT srcvalue)),
+    def : Pat<(fma (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)),
                    (fneg (wti.Vector (riscv_fpextend_vl_oneuse
                                           (vti.Vector vti.RegClass:$rs2),
                                           (vti.Mask true_mask), (XLenVT srcvalue)))),
                    (fneg wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
-                                          (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                                          (vti.Mask true_mask), (XLenVT srcvalue)))),
+    def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    (fneg wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
 multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
   foreach vtiToWti = AllWidenableFloatVectors in {
     defvar vti = vtiToWti.Vti;
     defvar wti = vtiToWti.Wti;
     def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
                                     (vti.Vector vti.RegClass:$rs1),
                                     (vti.Mask true_mask), (XLenVT srcvalue))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    (fneg wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
-                                    (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                                    (vti.Mask true_mask), (XLenVT srcvalue))),
+    def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    (fneg wti.RegClass:$rd)),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
 multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
   foreach vtiToWti = AllWidenableFloatVectors in {
     defvar vti = vtiToWti.Vti;
     defvar wti = vtiToWti.Wti;
     def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
                                           (vti.Vector vti.RegClass:$rs1),
                                           (vti.Mask true_mask), (XLenVT srcvalue)))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    wti.RegClass:$rd),
               (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
-                                    (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                                    (vti.Mask true_mask), (XLenVT srcvalue))),
+    def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))),
                    (fneg (wti.Vector (riscv_fpextend_vl_oneuse
                                           (vti.Vector vti.RegClass:$rs2),
                                           (vti.Mask true_mask), (XLenVT srcvalue)))),
                    wti.RegClass:$rd),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
-                                          (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
-                                          (vti.Mask true_mask), (XLenVT srcvalue)))),
+    def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
                    (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
                                              (vti.Mask true_mask), (XLenVT srcvalue)),
                    wti.RegClass:$rd),
               (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                  wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }

llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x half> %vs to <vscale x 1 x float>
   %r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %e)
   ret <vscale x 1 x float> %r
 }
 
 define <vscale x 1 x float> @vfcopysign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1 x float> %vm, half %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f32_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v10
+; CHECK-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %esplat = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
   %r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %esplat)
   ret <vscale x 1 x float> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x float>
   %r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %eneg)
   ret <vscale x 1 x float> %r
 }
 
 define <vscale x 1 x float> @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1 x float> %vm, half %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v10
+; CHECK-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %n = fneg <vscale x 1 x half> %splat
   %eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x float>
   %r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %eneg)
   ret <vscale x 1 x float> %r
 }
; CHECK-NEXT:    ret
   %e = fpext <vscale x 8 x half> %vs to <vscale x 8 x float>
   %r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %e)
   ret <vscale x 8 x float> %r
 }
 
 define <vscale x 8 x float> @vfcopysign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8 x float> %vm, half %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f32_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v12, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v16, v12
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v16
+; CHECK-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %esplat = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
   %r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %esplat)
   ret <vscale x 8 x float> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x float>
   %r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %eneg)
   ret <vscale x 8 x float> %r
 }
 
 define <vscale x 8 x float> @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8 x float> %vm, half %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v12, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v16, v12
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v16
+; CHECK-NEXT:    fcvt.s.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %n = fneg <vscale x 8 x half> %splat
   %eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x float>
   %r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %eneg)
   ret <vscale x 8 x float> %r
 }
; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x half> %vs to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %e)
   ret <vscale x 1 x double> %r
 }
 
 define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x 1 x double> %vm, half %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfwcvt.f.f.v v9, v10
-; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v9
+; CHECK-NEXT:    fcvt.d.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %esplat = fpext <vscale x 1 x half> %splat to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %esplat)
   ret <vscale x 1 x double> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %eneg)
   ret <vscale x 1 x double> %r
 }
 
 define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x 1 x double> %vm, half %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfwcvt.f.f.v v9, v10
-; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT:    fcvt.d.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %n = fneg <vscale x 1 x half> %splat
   %eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %eneg)
   ret <vscale x 1 x double> %r
 }
; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x float> %vs to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %e)
   ret <vscale x 1 x double> %r
 }
 
 define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x 1 x double> %vm, float %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v10
+; CHECK-NEXT:    fcvt.d.s ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %s, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %esplat = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %esplat)
   ret <vscale x 1 x double> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 1 x float> %n to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %eneg)
   ret <vscale x 1 x double> %r
 }
 
 define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x 1 x double> %vm, float %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v9, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v10, v9
-; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v10
+; CHECK-NEXT:    fcvt.d.s ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %s, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %n = fneg <vscale x 1 x float> %splat
   %eneg = fpext <vscale x 1 x float> %n to <vscale x 1 x double>
   %r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %eneg)
   ret <vscale x 1 x double> %r
 }
; CHECK-NEXT:    ret
   %e = fpext <vscale x 8 x half> %vs to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %e)
   ret <vscale x 8 x double> %r
 }
 
 define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x 8 x double> %vm, half %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v16, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v20, v16
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfwcvt.f.f.v v24, v20
-; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v24
+; CHECK-NEXT:    fcvt.d.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %esplat = fpext <vscale x 8 x half> %splat to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %esplat)
   ret <vscale x 8 x double> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %eneg)
   ret <vscale x 8 x double> %r
 }
 
 define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x 8 x double> %vm, half %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vfmv.v.f v16, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v20, v16
-; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfwcvt.f.f.v v24, v20
-; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v24
+; CHECK-NEXT:    fcvt.d.h ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x half> poison, half %s, i32 0
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %n = fneg <vscale x 8 x half> %splat
   %eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %eneg)
   ret <vscale x 8 x double> %r
 }
; CHECK-NEXT:    ret
   %e = fpext <vscale x 8 x float> %vs to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %e)
   ret <vscale x 8 x double> %r
 }
 
 define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x 8 x double> %vm, float %s) {
 ; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v16, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v24, v16
-; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vfsgnj.vv v8, v8, v24
+; CHECK-NEXT:    fcvt.d.s ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfsgnj.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %s, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %esplat = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %esplat)
   ret <vscale x 8 x double> %r
 }
 
; CHECK-NEXT:    ret
   %eneg = fpext <vscale x 8 x float> %n to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %eneg)
   ret <vscale x 8 x double> %r
 }
 
 define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x 8 x double> %vm, float %s) {
 ; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vfmv.v.f v16, fa0
-; CHECK-NEXT:    vfwcvt.f.f.v v24, v16
-; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT:    vfsgnjn.vv v8, v8, v24
+; CHECK-NEXT:    fcvt.d.s ft0, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfsgnjn.vf v8, v8, ft0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %s, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %n = fneg <vscale x 8 x float> %splat
   %eneg = fpext <vscale x 8 x float> %n to <vscale x 8 x double>
   %r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %eneg)
   ret <vscale x 8 x double> %r
 }

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wv v8, v8, v9
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vc
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
 define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsra.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsra.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsra.vx v8, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v8
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vc
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
 define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsra.wx v10, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vnsra.wx v10, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsra.vx v10, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vc
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
 define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsra.wx v12, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vnsra.wx v12, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsra.vx v12, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vc
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
 define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsra.wx v16, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vnsra.wx v16, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsra.vx v16, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vc
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
 define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsra.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsra.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsra.vx v8, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v8
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vc
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
 define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsra.wx v10, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vnsra.wx v10, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsra.vx v10, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vc
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
 define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsra.wx v12, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vnsra.wx v12, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsra.vx v12, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vc
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
 define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsra.wx v16, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vnsra.wx v16, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsra.vx v16, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v8, v8, v9
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vc
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
 define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsrl.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsrl.vx v8, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v8
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vc
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
 define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsrl.wx v10, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vnsrl.wx v10, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsrl.vx v10, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vc
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
 define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsrl.wx v12, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vnsrl.wx v12, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsrl.vx v12, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vc
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
 define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_sext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsrl.wx v16, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vnsrl.wx v16, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsrl.vx v16, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vc
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
 define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vnsrl.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsrl.vx v8, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v8
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vc
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
 define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vnsrl.wx v10, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vnsrl.wx v10, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsrl.vx v10, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vc
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
 define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vnsrl.wx v12, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vnsrl.wx v12, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsrl.vx v12, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vc
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
 define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_zext:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vnsrl.wx v16, v8, a0
-; CHECK-NEXT:    vmv.v.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vnsrl.wx v16, v8, a0
+; RV32-NEXT:    vmv.v.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsrl.vx v16, v8, a0
+; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT:    vncvt.x.x.w v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 

llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i64> @vwadd_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vwadd_vv_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vwadd.vv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %ve = add <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwadd_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwadd.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwadd.vx v9, v8, a0
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsext.vf2 v9, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vadd.vx v8, v9, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = add <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwaddu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwaddu.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwaddu.vx v9, v8, a0
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vzext.vf2 v9, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vadd.vx v8, v9, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = add <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %vd = add <vscale x 1 x i64> %va, %vc
   ret <vscale x 1 x i64> %vd
 }
 
 define <vscale x 1 x i64> @vwadd_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwadd.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_wx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwadd.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_wx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %vc = add <vscale x 1 x i64> %va, %vb
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vwaddu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwaddu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_wx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwaddu.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_wx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %vc = add <vscale x 1 x i64> %va, %vb
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vwadd_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %ve = add <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwadd_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwadd.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwadd.vx v10, v8, a0
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsext.vf2 v10, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vadd.vx v8, v10, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = add <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwaddu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwaddu.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwaddu.vx v10, v8, a0
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vzext.vf2 v10, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vadd.vx v8, v10, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = add <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %vd = add <vscale x 2 x i64> %va, %vc
   ret <vscale x 2 x i64> %vd
 }
 
 define <vscale x 2 x i64> @vwadd_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwadd.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_wx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwadd.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_wx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %vc = add <vscale x 2 x i64> %va, %vb
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vwaddu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwaddu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_wx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwaddu.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_wx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %vc = add <vscale x 2 x i64> %va, %vb
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vwadd_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %ve = add <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwadd_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwadd.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwadd.vx v12, v8, a0
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsext.vf2 v12, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vadd.vx v8, v12, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = add <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwaddu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwaddu.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwaddu.vx v12, v8, a0
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vzext.vf2 v12, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vadd.vx v8, v12, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = add <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv4r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %vd = add <vscale x 4 x i64> %va, %vc
   ret <vscale x 4 x i64> %vd
 }
 
 define <vscale x 4 x i64> @vwadd_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwadd.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_wx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwadd.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_wx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %vc = add <vscale x 4 x i64> %va, %vb
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vwaddu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwaddu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_wx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwaddu.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_wx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %vc = add <vscale x 4 x i64> %va, %vb
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vwadd_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %ve = add <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwadd_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwadd_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwadd.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwadd.vx v16, v8, a0
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsext.vf2 v16, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vadd.vx v8, v16, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = add <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwaddu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwaddu.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwaddu.vx v16, v8, a0
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vzext.vf2 v16, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vadd.vx v8, v16, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = add <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv8r.v v8, v24
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %vd = add <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
 
 define <vscale x 8 x i64> @vwadd_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwadd_wx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwadd.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwadd_wx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwadd.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwadd_wx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %vc = add <vscale x 8 x i64> %va, %vb
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vwaddu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwaddu_wx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwaddu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwaddu_wx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwaddu.wx v8, v8, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwaddu_wx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vadd.vx v8, v8, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %vc = add <vscale x 8 x i64> %va, %vb
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
 ; CHECK-LABEL: vwmacc_vv_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vwmacc.vv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv1i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmacc.vx v9, a0, v8
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmacc_vx_nxv1i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmacc.vx v9, a0, v8
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmacc_vx_nxv1i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsext.vf2 v10, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v10, a0, v9
+; RV64-NEXT:    vmv.v.v v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
; CHECK-NEXT:    ret
   %ve = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv1i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmaccu.vx v9, a0, v8
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccu_vx_nxv1i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmaccu.vx v9, a0, v8
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv1i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vzext.vf2 v10, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v10, a0, v9
+; RV64-NEXT:    vmv.v.v v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv1i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmaccsu.vx v9, a0, v8
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccsu_vx_nxv1i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmaccsu.vx v9, a0, v8
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv1i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vzext.vf2 v10, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v10, a0, v9
+; RV64-NEXT:    vmv.v.v v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
 }
 
 define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv1i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmaccus.vx v9, a0, v8
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccus_vx_nxv1i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmaccus.vx v9, a0, v8
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv1i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsext.vf2 v10, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v10, a0, v9
+; RV64-NEXT:    vmv.v.v v8, v10
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
 
   %x = mul <vscale x 1 x i64> %vd, %ve
   %y = add <vscale x 1 x i64> %x, %vc
   ret <vscale x 1 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
 }
 
 define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv2i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmacc.vx v10, a0, v8
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmacc_vx_nxv2i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmacc.vx v10, a0, v8
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmacc_vx_nxv2i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsext.vf2 v12, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v12, a0, v10
+; RV64-NEXT:    vmv.v.v v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
; CHECK-NEXT:    ret
   %ve = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
 }
 
 define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv2i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmaccu.vx v10, a0, v8
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccu_vx_nxv2i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmaccu.vx v10, a0, v8
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv2i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vzext.vf2 v12, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v12, a0, v10
+; RV64-NEXT:    vmv.v.v v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
 }
 
 define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv2i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmaccsu.vx v10, a0, v8
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccsu_vx_nxv2i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmaccsu.vx v10, a0, v8
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv2i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vzext.vf2 v12, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v12, a0, v10
+; RV64-NEXT:    vmv.v.v v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
 }
 
 define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv2i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmaccus.vx v10, a0, v8
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccus_vx_nxv2i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmaccus.vx v10, a0, v8
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv2i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsext.vf2 v12, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v12, a0, v10
+; RV64-NEXT:    vmv.v.v v8, v12
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
 
   %x = mul <vscale x 2 x i64> %vd, %ve
   %y = add <vscale x 2 x i64> %x, %vc
   ret <vscale x 2 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
 }
 
 define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv4i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmacc.vx v12, a0, v8
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmacc_vx_nxv4i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmacc.vx v12, a0, v8
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmacc_vx_nxv4i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsext.vf2 v16, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v16, a0, v12
+; RV64-NEXT:    vmv.v.v v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
; CHECK-NEXT:    ret
   %ve = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
 }
 
 define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv4i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmaccu.vx v12, a0, v8
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccu_vx_nxv4i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmaccu.vx v12, a0, v8
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv4i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vzext.vf2 v16, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v16, a0, v12
+; RV64-NEXT:    vmv.v.v v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
 }
 
 define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv4i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmaccsu.vx v12, a0, v8
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccsu_vx_nxv4i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmaccsu.vx v12, a0, v8
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv4i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vzext.vf2 v16, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v16, a0, v12
+; RV64-NEXT:    vmv.v.v v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
 }
 
 define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv4i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmaccus.vx v12, a0, v8
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccus_vx_nxv4i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmaccus.vx v12, a0, v8
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv4i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsext.vf2 v16, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v16, a0, v12
+; RV64-NEXT:    vmv.v.v v8, v16
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
 
   %x = mul <vscale x 4 x i64> %vd, %ve
   %y = add <vscale x 4 x i64> %x, %vc
   ret <vscale x 4 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
 }
 
 define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmacc_vx_nxv8i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmacc.vx v16, a0, v8
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmacc_vx_nxv8i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmacc.vx v16, a0, v8
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmacc_vx_nxv8i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsext.vf2 v24, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v24, a0, v16
+; RV64-NEXT:    vmv.v.v v8, v24
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
; CHECK-NEXT:    ret
   %ve = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
 }
 
 define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccu_vx_nxv8i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmaccu.vx v16, a0, v8
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccu_vx_nxv8i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmaccu.vx v16, a0, v8
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccu_vx_nxv8i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vzext.vf2 v24, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v24, a0, v16
+; RV64-NEXT:    vmv.v.v v8, v24
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
; CHECK-NEXT:    ret
   %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
 }
 
 define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccsu_vx_nxv8i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmaccsu.vx v16, a0, v8
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccsu_vx_nxv8i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmaccsu.vx v16, a0, v8
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccsu_vx_nxv8i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vzext.vf2 v24, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmadd.vx v24, a0, v16
+; RV64-NEXT:    vmv.v.v v8, v24
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
 }
 
 define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
-; CHECK-LABEL: vwmaccus_vx_nxv8i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmaccus.vx v16, a0, v8
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmaccus_vx_nxv8i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmaccus.vx v16, a0, v8
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmaccus_vx_nxv8i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsext.vf2 v24, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmadd.vx v24, a0, v16
+; RV64-NEXT:    vmv.v.v v8, v24
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
 
   %x = mul <vscale x 8 x i64> %vd, %ve
   %y = add <vscale x 8 x i64> %x, %vc
   ret <vscale x 8 x i64> %y
 }

llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <vscale x 1 x i64> @vwmul_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vwmul_vv_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vwmul.vv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %ve = mul <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwmul_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmul.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmul_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmul.vx v9, v8, a0
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmul_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsext.vf2 v9, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmul.vx v8, v9, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = mul <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwmulu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmulu.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulu_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmulu.vx v9, v8, a0
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulu_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vzext.vf2 v9, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v9, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = mul <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwmulsu.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulsu_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; RV32-NEXT:    vwmulsu.vx v9, v8, a0
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vsext.vf2 v9, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v9, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = mul <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %ve = mul <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwmul_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmul.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmul_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmul.vx v10, v8, a0
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmul_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsext.vf2 v10, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmul.vx v8, v10, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = mul <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwmulu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmulu.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulu_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmulu.vx v10, v8, a0
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulu_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vzext.vf2 v10, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v10, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = mul <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwmulsu.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulsu_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; RV32-NEXT:    vwmulsu.vx v10, v8, a0
+; RV32-NEXT:    vmv2r.v v8, v10
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vsext.vf2 v10, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v10, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = mul <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %ve = mul <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwmul_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmul.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmul_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmul.vx v12, v8, a0
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmul_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsext.vf2 v12, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmul.vx v8, v12, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = mul <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwmulu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmulu.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulu_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmulu.vx v12, v8, a0
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulu_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vzext.vf2 v12, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v12, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = mul <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwmulsu.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulsu_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; RV32-NEXT:    vwmulsu.vx v12, v8, a0
+; RV32-NEXT:    vmv4r.v v8, v12
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vsext.vf2 v12, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v12, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = mul <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 

 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %ve = mul <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwmul_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmul_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmul.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmul_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmul.vx v16, v8, a0
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmul_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsext.vf2 v16, v8
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    vmul.vx v8, v16, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = mul <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwmulu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulu_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmulu.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulu_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmulu.vx v16, v8, a0
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulu_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vzext.vf2 v16, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v16, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = mul <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwmulsu_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwmulsu.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwmulsu_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; RV32-NEXT:    vwmulsu.vx v16, v8, a0
+; RV32-NEXT:    vmv8r.v v8, v16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vwmulsu_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vsext.vf2 v16, v8
+; RV64-NEXT:    slli a0, a0, 32
+; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    vmul.vx v8, v16, a0
+; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = mul <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64
 
 define <vscale x 1 x i64> @vwsub_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vwsub_vv_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vwsub.vv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %ve = sub <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwsub_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwsub.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_vx_nxv1i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT:    vwsub.vx v9, v8, a0
+; CHECK32-NEXT:    vmv1r.v v8, v9
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv1i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT:    vsext.vf2 v9, v8
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsub.vx v8, v9, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = sub <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 
 define <vscale x 1 x i64> @vwsubu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwsubu.vx v9, v8, a0
-; CHECK-NEXT:    vmv1r.v v8, v9
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_vx_nxv1i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT:    vwsubu.vx v9, v8, a0
+; CHECK32-NEXT:    vmv1r.v v8, v9
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv1i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT:    vzext.vf2 v9, v8
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsub.vx v8, v9, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
   %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %ve = sub <vscale x 1 x i64> %vc, %vd
   ret <vscale x 1 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %vd = sub <vscale x 1 x i64> %va, %vc
   ret <vscale x 1 x i64> %vd
 }
 
 define <vscale x 1 x i64> @vwsub_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwsub.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_wx_nxv1i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT:    vwsub.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv1i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %vc = sub <vscale x 1 x i64> %va, %vb
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vwsubu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv1i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT:    vwsubu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_wx_nxv1i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK32-NEXT:    vwsubu.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv1i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %vc = sub <vscale x 1 x i64> %va, %vb
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vwsub_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %ve = sub <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwsub_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwsub.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_vx_nxv2i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT:    vwsub.vx v10, v8, a0
+; CHECK32-NEXT:    vmv2r.v v8, v10
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv2i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT:    vsext.vf2 v10, v8
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsub.vx v8, v10, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = sub <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 
 define <vscale x 2 x i64> @vwsubu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwsubu.vx v10, v8, a0
-; CHECK-NEXT:    vmv2r.v v8, v10
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_vx_nxv2i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT:    vwsubu.vx v10, v8, a0
+; CHECK32-NEXT:    vmv2r.v v8, v10
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv2i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT:    vzext.vf2 v10, v8
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsub.vx v8, v10, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
   %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %ve = sub <vscale x 2 x i64> %vc, %vd
   ret <vscale x 2 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
   %vd = sub <vscale x 2 x i64> %va, %vc
   ret <vscale x 2 x i64> %vd
 }
 
 define <vscale x 2 x i64> @vwsub_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwsub.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_wx_nxv2i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT:    vwsub.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv2i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %vc = sub <vscale x 2 x i64> %va, %vb
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vwsubu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vwsubu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_wx_nxv2i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK32-NEXT:    vwsubu.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv2i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %vc = sub <vscale x 2 x i64> %va, %vb
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vwsub_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %ve = sub <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwsub_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwsub.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_vx_nxv4i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT:    vwsub.vx v12, v8, a0
+; CHECK32-NEXT:    vmv4r.v v8, v12
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv4i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT:    vsext.vf2 v12, v8
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsub.vx v8, v12, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = sub <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 
 define <vscale x 4 x i64> @vwsubu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwsubu.vx v12, v8, a0
-; CHECK-NEXT:    vmv4r.v v8, v12
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_vx_nxv4i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT:    vwsubu.vx v12, v8, a0
+; CHECK32-NEXT:    vmv4r.v v8, v12
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv4i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT:    vzext.vf2 v12, v8
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsub.vx v8, v12, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
   %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %ve = sub <vscale x 4 x i64> %vc, %vd
   ret <vscale x 4 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv4r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
   %vd = sub <vscale x 4 x i64> %va, %vc
   ret <vscale x 4 x i64> %vd
 }
 
 define <vscale x 4 x i64> @vwsub_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwsub.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_wx_nxv4i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT:    vwsub.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv4i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %vc = sub <vscale x 4 x i64> %va, %vb
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vwsubu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv4i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vwsubu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_wx_nxv4i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK32-NEXT:    vwsubu.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv4i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %vc = sub <vscale x 4 x i64> %va, %vb
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vwsub_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %ve = sub <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwsub_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsub_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwsub.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_vx_nxv8i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT:    vwsub.vx v16, v8, a0
+; CHECK32-NEXT:    vmv8r.v v8, v16
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_vx_nxv8i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT:    vsext.vf2 v16, v8
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsub.vx v8, v16, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = sub <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 
 define <vscale x 8 x i64> @vwsubu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_vx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwsubu.vx v16, v8, a0
-; CHECK-NEXT:    vmv8r.v v8, v16
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_vx_nxv8i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT:    vwsubu.vx v16, v8, a0
+; CHECK32-NEXT:    vmv8r.v v8, v16
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_vx_nxv8i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT:    vzext.vf2 v16, v8
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsub.vx v8, v16, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %ve = sub <vscale x 8 x i64> %vc, %vd
   ret <vscale x 8 x i64> %ve
 }
 

 ; CHECK-NEXT:    vmv8r.v v8, v24
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
   %vd = sub <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
 
 define <vscale x 8 x i64> @vwsub_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsub_wx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwsub.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsub_wx_nxv8i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT:    vwsub.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsub_wx_nxv8i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    sext.w a0, a0
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %vc = sub <vscale x 8 x i64> %va, %vb
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vwsubu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
-; CHECK-LABEL: vwsubu_wx_nxv8i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vwsubu.wx v8, v8, a0
-; CHECK-NEXT:    ret
+; CHECK32-LABEL: vwsubu_wx_nxv8i64:
+; CHECK32:       # %bb.0:
+; CHECK32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK32-NEXT:    vwsubu.wx v8, v8, a0
+; CHECK32-NEXT:    ret
+;
+; CHECK64-LABEL: vwsubu_wx_nxv8i64:
+; CHECK64:       # %bb.0:
+; CHECK64-NEXT:    slli a0, a0, 32
+; CHECK64-NEXT:    srli a0, a0, 32
+; CHECK64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK64-NEXT:    vsub.vx v8, v8, a0
+; CHECK64-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %vc = sub <vscale x 8 x i64> %va, %vb
   ret <vscale x 8 x i64> %vc
 }