[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub

[Jimerlife]

Summary

Supplement SDNode patterns for vfwmul/vfwadd/vfwsub

[jacquesguan]

LGTM

[frasercrmck]

I'm kind of surprised this (fp->splat/splat->fp) isn't canonicalized one way or the other. What's going on? Are we missing a canonicalization for scalable vectors?

[jacquesguan]

In D122720#3416303, @frasercrmck wrote:

I'm kind of surprised this (fp->splat/splat->fp) isn't canonicalized one way or the other. What's going on? Are we missing a canonicalization for scalable vectors?

I create a new revision to do this, https://reviews.llvm.org/D122875 .

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
               (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
                  vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
                  vti.Vti.AVL, vti.Vti.Log2SEW)>;
     def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
                   (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatFPOp vti.Vti.ScalarRegClass:$rs1))))),
               (!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
                  vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
                  vti.Vti.AVL, vti.Vti.Log2SEW)>;
+    def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+                  (vti.Wti.Vector (SplatFPOp (fpext_oneuse vti.Vti.ScalarRegClass:$rs1)))),
+              (!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
+                 vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
+                 vti.Vti.AVL, vti.Vti.Log2SEW)>;
   }
 }
 
 multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
   foreach vti = AllWidenableFloatVectors in {
     def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
                   (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
               (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
                  vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
                  vti.Vti.AVL, vti.Vti.Log2SEW)>;
     def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
                   (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatFPOp vti.Vti.ScalarRegClass:$rs1))))),
               (!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
                  vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
                  vti.Vti.AVL, vti.Vti.Log2SEW)>;
+      def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+                  (vti.Wti.Vector (SplatFPOp (fpext_oneuse vti.Vti.ScalarRegClass:$rs1)))),
+              (!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
+                 vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
+                 vti.Vti.AVL, vti.Vti.Log2SEW)>;
   }
 }
 
 multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
   defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
   defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
 }
 

llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll

; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
   %vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %ve = fadd <vscale x 1 x double> %vc, %vd
   ret <vscale x 1 x double> %ve
 }
 
+define <vscale x 1 x double> @vfwadd_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv1f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwadd.vf v9, v8, fa0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+  %ve = fadd <vscale x 1 x double> %vc, %splat
+  ret <vscale x 1 x double> %ve
+}
+
 define <vscale x 1 x double> @vfwadd_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
 ; CHECK-LABEL: vfwadd_wv_nxv1f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfwadd.wv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %vc = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %vd = fadd <vscale x 1 x double> %va, %vc
   ret <vscale x 1 x double> %vd
 }
 
+define <vscale x 1 x double> @vfwadd_wf_nxv1f64_2(<vscale x 1 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv1f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwadd.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %vd = fadd <vscale x 1 x double> %va, %splat
+  ret <vscale x 1 x double> %vd
+}
+
 define <vscale x 2 x double> @vfwadd_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
 ; CHECK-LABEL: vfwadd_vv_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwadd.vv v10, v8, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
   %vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
   %ve = fadd <vscale x 2 x double> %vc, %vd
   ret <vscale x 2 x double> %ve
 }
 
+define <vscale x 2 x double> @vfwadd_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv2f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwadd.vf v10, v8, fa0
+; CHECK-NEXT:    vmv2r.v v8, v10
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+  %ve = fadd <vscale x 2 x double> %vc, %splat
+  ret <vscale x 2 x double> %ve
+}
+
 define <vscale x 2 x double> @vfwadd_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
 ; CHECK-LABEL: vfwadd_wv_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwadd.wv v12, v8, v10
 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
   %vc = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
   %vd = fadd <vscale x 2 x double> %va, %vc
   ret <vscale x 2 x double> %vd
 }
 
+define <vscale x 2 x double> @vfwadd_wf_nxv2f64_2(<vscale x 2 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv2f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwadd.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+  %vd = fadd <vscale x 2 x double> %va, %splat
+  ret <vscale x 2 x double> %vd
+}
+
 define <vscale x 4 x double> @vfwadd_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
 ; CHECK-LABEL: vfwadd_vv_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfwadd.vv v12, v8, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
   %vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
   %ve = fadd <vscale x 4 x double> %vc, %vd
   ret <vscale x 4 x double> %ve
 }
 
+define <vscale x 4 x double> @vfwadd_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv4f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwadd.vf v12, v8, fa0
+; CHECK-NEXT:    vmv4r.v v8, v12
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+  %ve = fadd <vscale x 4 x double> %vc, %splat
+  ret <vscale x 4 x double> %ve
+}
+
 define <vscale x 4 x double> @vfwadd_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
 ; CHECK-LABEL: vfwadd_wv_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfwadd.wv v16, v8, v12
 ; CHECK-NEXT:    vmv4r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
   %vc = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
   %vd = fadd <vscale x 4 x double> %va, %vc
   ret <vscale x 4 x double> %vd
 }
 
+define <vscale x 4 x double> @vfwadd_wf_nxv4f64_2(<vscale x 4 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv4f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwadd.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %vd = fadd <vscale x 4 x double> %va, %splat
+  ret <vscale x 4 x double> %vd
+}
+
 define <vscale x 8 x double> @vfwadd_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
 ; CHECK-LABEL: vfwadd_vv_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwadd.vv v16, v8, v12
 ; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
   %vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %ve = fadd <vscale x 8 x double> %vc, %vd
   ret <vscale x 8 x double> %ve
 }
 
+define <vscale x 8 x double> @vfwadd_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv8f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwadd.vf v16, v8, fa0
+; CHECK-NEXT:    vmv8r.v v8, v16
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+  %ve = fadd <vscale x 8 x double> %vc, %splat
+  ret <vscale x 8 x double> %ve
+}
+
 define <vscale x 8 x double> @vfwadd_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
 ; CHECK-LABEL: vfwadd_wv_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwadd.wv v24, v8, v16
 ; CHECK-NEXT:    vmv8r.v v8, v24
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
   %vd = fadd <vscale x 8 x double> %va, %vc
   ret <vscale x 8 x double> %vd
 }
 
 define <vscale x 8 x double> @vfwadd_wf_nxv8f64(<vscale x 8 x double> %va, float %b) {
 ; CHECK-LABEL: vfwadd_wf_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwadd.wf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %vc = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %vd = fadd <vscale x 8 x double> %va, %vc
   ret <vscale x 8 x double> %vd
 }
+
+define <vscale x 8 x double> @vfwadd_wf_nxv8f64_2(<vscale x 8 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv8f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwadd.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  %vd = fadd <vscale x 8 x double> %va, %splat
+  ret <vscale x 8 x double> %vd
+}

llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll

; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
   %vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %ve = fmul <vscale x 1 x double> %vc, %vd
   ret <vscale x 1 x double> %ve
 }
 
+define <vscale x 1 x double> @vfwmul_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv1f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwmul.vf v9, v8, fa0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+  %ve = fmul <vscale x 1 x double> %vc, %splat
+  ret <vscale x 1 x double> %ve
+}
+
 define <vscale x 2 x double> @vfwmul_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
 ; CHECK-LABEL: vfwmul_vv_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwmul.vv v10, v8, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
   %vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
   %ve = fmul <vscale x 2 x double> %vc, %vd
   ret <vscale x 2 x double> %ve
 }
 
+define <vscale x 2 x double> @vfwmul_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv2f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwmul.vf v10, v8, fa0
+; CHECK-NEXT:    vmv2r.v v8, v10
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+  %ve = fmul <vscale x 2 x double> %vc, %splat
+  ret <vscale x 2 x double> %ve
+}
+
 define <vscale x 4 x double> @vfwmul_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
 ; CHECK-LABEL: vfwmul_vv_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfwmul.vv v12, v8, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
   %vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
   %ve = fmul <vscale x 4 x double> %vc, %vd
   ret <vscale x 4 x double> %ve
 }
 
+define <vscale x 4 x double> @vfwmul_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv4f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwmul.vf v12, v8, fa0
+; CHECK-NEXT:    vmv4r.v v8, v12
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+  %ve = fmul <vscale x 4 x double> %vc, %splat
+  ret <vscale x 4 x double> %ve
+}
+
 define <vscale x 8 x double> @vfwmul_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
 ; CHECK-LABEL: vfwmul_vv_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwmul.vv v16, v8, v12
 ; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
   %vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %ve = fmul <vscale x 8 x double> %vc, %vd
   ret <vscale x 8 x double> %ve
 }
+
+define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv8f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwmul.vf v16, v8, fa0
+; CHECK-NEXT:    vmv8r.v v8, v16
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+  %ve = fmul <vscale x 8 x double> %vc, %splat
+  ret <vscale x 8 x double> %ve
+}

llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll

; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
   %vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %ve = fsub <vscale x 1 x double> %vc, %vd
   ret <vscale x 1 x double> %ve
 }
 
+define <vscale x 1 x double> @vfwsub_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv1f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwsub.vf v9, v8, fa0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+  %ve = fsub <vscale x 1 x double> %vc, %splat
+  ret <vscale x 1 x double> %ve
+}
+
 define <vscale x 1 x double> @vfwsub_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
 ; CHECK-LABEL: vfwsub_wv_nxv1f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfwsub.wv v10, v8, v9
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
   %vc = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
   %vd = fsub <vscale x 1 x double> %va, %vc
   ret <vscale x 1 x double> %vd
 }
 
+define <vscale x 1 x double> @vfwsub_wf_nxv1f64_2(<vscale x 1 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv1f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwsub.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %vd = fsub <vscale x 1 x double> %va, %splat
+  ret <vscale x 1 x double> %vd
+}
+
 define <vscale x 2 x double> @vfwsub_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
 ; CHECK-LABEL: vfwsub_vv_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwsub.vv v10, v8, v9
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
   %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
   %vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
   %ve = fsub <vscale x 2 x double> %vc, %vd
   ret <vscale x 2 x double> %ve
 }
 
+define <vscale x 2 x double> @vfwsub_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv2f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwsub.vf v10, v8, fa0
+; CHECK-NEXT:    vmv2r.v v8, v10
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+  %ve = fsub <vscale x 2 x double> %vc, %splat
+  ret <vscale x 2 x double> %ve
+}
+
 define <vscale x 2 x double> @vfwsub_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
 ; CHECK-LABEL: vfwsub_wv_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vfwsub.wv v12, v8, v10
 ; CHECK-NEXT:    vmv2r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
   %vc = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
   %vd = fsub <vscale x 2 x double> %va, %vc
   ret <vscale x 2 x double> %vd
 }
 
+define <vscale x 2 x double> @vfwsub_wf_nxv2f64_2(<vscale x 2 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv2f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwsub.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+  %vd = fsub <vscale x 2 x double> %va, %splat
+  ret <vscale x 2 x double> %vd
+}
+
 define <vscale x 4 x double> @vfwsub_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
 ; CHECK-LABEL: vfwsub_vv_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfwsub.vv v12, v8, v10
 ; CHECK-NEXT:    vmv4r.v v8, v12
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
   %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
   %vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
   %ve = fsub <vscale x 4 x double> %vc, %vd
   ret <vscale x 4 x double> %ve
 }
 
+define <vscale x 4 x double> @vfwsub_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv4f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwsub.vf v12, v8, fa0
+; CHECK-NEXT:    vmv4r.v v8, v12
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+  %ve = fsub <vscale x 4 x double> %vc, %splat
+  ret <vscale x 4 x double> %ve
+}
+
 define <vscale x 4 x double> @vfwsub_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
 ; CHECK-LABEL: vfwsub_wv_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vfwsub.wv v16, v8, v12
 ; CHECK-NEXT:    vmv4r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
   %vc = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
   %vd = fsub <vscale x 4 x double> %va, %vc
   ret <vscale x 4 x double> %vd
 }
 
+define <vscale x 4 x double> @vfwsub_wf_nxv4f64_2(<vscale x 4 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv4f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwsub.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %vd = fsub <vscale x 4 x double> %va, %splat
+  ret <vscale x 4 x double> %vd
+}
+
 define <vscale x 8 x double> @vfwsub_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
 ; CHECK-LABEL: vfwsub_vv_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwsub.vv v16, v8, v12
 ; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
   %vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %ve = fsub <vscale x 8 x double> %vc, %vd
   ret <vscale x 8 x double> %ve
 }
 
+define <vscale x 8 x double> @vfwsub_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv8f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwsub.vf v16, v8, fa0
+; CHECK-NEXT:    vmv8r.v v8, v16
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+  %ve = fsub <vscale x 8 x double> %vc, %splat
+  ret <vscale x 8 x double> %ve
+}
+
 define <vscale x 8 x double> @vfwsub_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
 ; CHECK-LABEL: vfwsub_wv_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwsub.wv v24, v8, v16
 ; CHECK-NEXT:    vmv8r.v v8, v24
 ; CHECK-NEXT:    ret
   %vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
   %vd = fsub <vscale x 8 x double> %va, %vc
   ret <vscale x 8 x double> %vd
 }
 
 define <vscale x 8 x double> @vfwsub_wf_nxv8f64(<vscale x 8 x double> %va, float %b) {
 ; CHECK-LABEL: vfwsub_wf_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vfwsub.wf v8, v8, fa0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
   %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
   %vc = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
   %vd = fsub <vscale x 8 x double> %va, %vc
   ret <vscale x 8 x double> %vd
 }
+
+define <vscale x 8 x double> @vfwsub_wf_nxv8f64_2(<vscale x 8 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv8f64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwsub.wf v8, v8, fa0
+; CHECK-NEXT:    ret
+  %fpext = fpext float %b to double
+  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+  %vd = fsub <vscale x 8 x double> %va, %splat
+  ret <vscale x 8 x double> %vd
+}