[RISCV] Honor the VT when converting float point register names to register class for inline assembly.

[craig.topper]

Summary

It appears the code here was written for the inline asm clobbering
a specific register, but it also gets used for named input and
output registers.

For the input and output case, we should honor the VT so we
don't insert conversion instructions around the inline assembly.

For the clobber, case we need to pick the largest register class.

[jrtc27]

Ouch

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
                         .Cases("{f27}", "{fs11}", RISCV::F27_F)
                         .Cases("{f28}", "{ft8}", RISCV::F28_F)
                         .Cases("{f29}", "{ft9}", RISCV::F29_F)
                         .Cases("{f30}", "{ft10}", RISCV::F30_F)
                         .Cases("{f31}", "{ft11}", RISCV::F31_F)
                         .Default(RISCV::NoRegister);
     if (FReg != RISCV::NoRegister) {
       assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg");
-      if (Subtarget.hasStdExtD()) {
+      if (Subtarget.hasStdExtD() && (VT == MVT::f64 || VT == MVT::Other)) {
         unsigned RegNo = FReg - RISCV::F0_F;
         unsigned DReg = RISCV::F0_D + RegNo;
         return std::make_pair(DReg, &RISCV::FPR64RegClass);
       }
+      if (VT == MVT::f32 || VT == MVT::Other)
         return std::make_pair(FReg, &RISCV::FPR32RegClass);
+      if (Subtarget.hasStdExtZfh() && VT == MVT::f16) {
+        unsigned RegNo = FReg - RISCV::F0_F;
+        unsigned HReg = RISCV::F0_H + RegNo;
+        return std::make_pair(HReg, &RISCV::FPR16RegClass);
+      }
     }
   }
 
   if (Subtarget.hasVInstructions()) {
     Register VReg = StringSwitch<Register>(Constraint.lower())
                         .Case("{v0}", RISCV::V0)
                         .Case("{v1}", RISCV::V1)
                         .Case("{v2}", RISCV::V2)

llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32D %s
+; RUN:   | FileCheck -check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV64D %s
+; RUN:   | FileCheck -check-prefix=RV64F %s
 
 @gf = external global float
 
 define float @constraint_f_float(float %a) nounwind {
 ; RV32F-LABEL: constraint_f_float:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a1, %hi(gf)
 ; RV32F-NEXT:    flw ft0, %lo(gf)(a1)

 ; RV64F-NEXT:    lui a1, %hi(gf)
 ; RV64F-NEXT:    flw ft0, %lo(gf)(a1)
 ; RV64F-NEXT:    fmv.w.x ft1, a0
 ; RV64F-NEXT:    #APP
 ; RV64F-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64F-NEXT:    #NO_APP
 ; RV64F-NEXT:    fmv.x.w a0, ft0
 ; RV64F-NEXT:    ret
-;
-; RV32D-LABEL: constraint_f_float:
-; RV32D:       # %bb.0:
-; RV32D-NEXT:    lui a1, %hi(gf)
-; RV32D-NEXT:    flw ft0, %lo(gf)(a1)
-; RV32D-NEXT:    fmv.w.x ft1, a0
-; RV32D-NEXT:    #APP
-; RV32D-NEXT:    fadd.s ft0, ft1, ft0
-; RV32D-NEXT:    #NO_APP
-; RV32D-NEXT:    fmv.x.w a0, ft0
-; RV32D-NEXT:    ret
-;
-; RV64D-LABEL: constraint_f_float:
-; RV64D:       # %bb.0:
-; RV64D-NEXT:    lui a1, %hi(gf)
-; RV64D-NEXT:    flw ft0, %lo(gf)(a1)
-; RV64D-NEXT:    fmv.w.x ft1, a0
-; RV64D-NEXT:    #APP
-; RV64D-NEXT:    fadd.s ft0, ft1, ft0
-; RV64D-NEXT:    #NO_APP
-; RV64D-NEXT:    fmv.x.w a0, ft0
-; RV64D-NEXT:    ret
   %1 = load float, float* @gf
   %2 = tail call float asm "fadd.s $0, $1, $2", "=f,f,f"(float %a, float %1)
   ret float %2
 }
 
 define float @constraint_f_float_abi_name(float %a) nounwind {
 ; RV32F-LABEL: constraint_f_float_abi_name:
 ; RV32F:       # %bb.0:

 ; RV64F-NEXT:    lui a1, %hi(gf)
 ; RV64F-NEXT:    flw fs0, %lo(gf)(a1)
 ; RV64F-NEXT:    fmv.w.x fa0, a0
 ; RV64F-NEXT:    #APP
 ; RV64F-NEXT:    fadd.s ft0, fa0, fs0
 ; RV64F-NEXT:    #NO_APP
 ; RV64F-NEXT:    fmv.x.w a0, ft0
 ; RV64F-NEXT:    ret
-;
-; RV32D-LABEL: constraint_f_float_abi_name:
-; RV32D:       # %bb.0:
-; RV32D-NEXT:    lui a1, %hi(gf)
-; RV32D-NEXT:    flw ft0, %lo(gf)(a1)
-; RV32D-NEXT:    fmv.w.x ft1, a0
-; RV32D-NEXT:    fcvt.d.s fa0, ft1
-; RV32D-NEXT:    fcvt.d.s fs0, ft0
-; RV32D-NEXT:    #APP
-; RV32D-NEXT:    fadd.s ft0, fa0, fs0
-; RV32D-NEXT:    #NO_APP
-; RV32D-NEXT:    fcvt.s.d ft0, ft0
-; RV32D-NEXT:    fmv.x.w a0, ft0
-; RV32D-NEXT:    ret
-;
-; RV64D-LABEL: constraint_f_float_abi_name:
-; RV64D:       # %bb.0:
-; RV64D-NEXT:    lui a1, %hi(gf)
-; RV64D-NEXT:    flw ft0, %lo(gf)(a1)
-; RV64D-NEXT:    fmv.w.x ft1, a0
-; RV64D-NEXT:    fcvt.d.s fa0, ft1
-; RV64D-NEXT:    fcvt.d.s fs0, ft0
-; RV64D-NEXT:    #APP
-; RV64D-NEXT:    fadd.s ft0, fa0, fs0
-; RV64D-NEXT:    #NO_APP
-; RV64D-NEXT:    fcvt.s.d ft0, ft0
-; RV64D-NEXT:    fmv.x.w a0, ft0
-; RV64D-NEXT:    ret
   %1 = load float, float* @gf
   %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)
   ret float %2
 }

llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll

 }
 
 define half @constraint_f_half_abi_name(half %a) nounwind {
 ; RV32ZFH-LABEL: constraint_f_half_abi_name:
 ; RV32ZFH:       # %bb.0:
 ; RV32ZFH-NEXT:    addi sp, sp, -16
 ; RV32ZFH-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
 ; RV32ZFH-NEXT:    lui a0, %hi(gh)
-; RV32ZFH-NEXT:    flh ft0, %lo(gh)(a0)
-; RV32ZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV32ZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV32ZFH-NEXT:    flh fs0, %lo(gh)(a0)
 ; RV32ZFH-NEXT:    #APP
 ; RV32ZFH-NEXT:    fadd.s ft0, fa0, fs0
 ; RV32ZFH-NEXT:    #NO_APP
-; RV32ZFH-NEXT:    fcvt.h.s fa0, ft0
+; RV32ZFH-NEXT:    fmv.h fa0, ft0
 ; RV32ZFH-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; RV32ZFH-NEXT:    addi sp, sp, 16
 ; RV32ZFH-NEXT:    ret
 ;
 ; RV64ZFH-LABEL: constraint_f_half_abi_name:
 ; RV64ZFH:       # %bb.0:
 ; RV64ZFH-NEXT:    addi sp, sp, -16
 ; RV64ZFH-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
 ; RV64ZFH-NEXT:    lui a0, %hi(gh)
-; RV64ZFH-NEXT:    flh ft0, %lo(gh)(a0)
-; RV64ZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV64ZFH-NEXT:    fcvt.s.h fs0, ft0
+; RV64ZFH-NEXT:    flh fs0, %lo(gh)(a0)
 ; RV64ZFH-NEXT:    #APP
 ; RV64ZFH-NEXT:    fadd.s ft0, fa0, fs0
 ; RV64ZFH-NEXT:    #NO_APP
-; RV64ZFH-NEXT:    fcvt.h.s fa0, ft0
+; RV64ZFH-NEXT:    fmv.h fa0, ft0
 ; RV64ZFH-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; RV64ZFH-NEXT:    addi sp, sp, 16
 ; RV64ZFH-NEXT:    ret
 ;
 ; RV32DZFH-LABEL: constraint_f_half_abi_name:
 ; RV32DZFH:       # %bb.0:
 ; RV32DZFH-NEXT:    addi sp, sp, -16
 ; RV32DZFH-NEXT:    fsd fs0, 8(sp) # 8-byte Folded Spill
 ; RV32DZFH-NEXT:    lui a0, %hi(gh)
-; RV32DZFH-NEXT:    flh ft0, %lo(gh)(a0)
-; RV32DZFH-NEXT:    fcvt.d.h fa0, fa0
-; RV32DZFH-NEXT:    fcvt.d.h fs0, ft0
+; RV32DZFH-NEXT:    flh fs0, %lo(gh)(a0)
 ; RV32DZFH-NEXT:    #APP
 ; RV32DZFH-NEXT:    fadd.s ft0, fa0, fs0
 ; RV32DZFH-NEXT:    #NO_APP
-; RV32DZFH-NEXT:    fcvt.h.d fa0, ft0
+; RV32DZFH-NEXT:    fmv.h fa0, ft0
 ; RV32DZFH-NEXT:    fld fs0, 8(sp) # 8-byte Folded Reload
 ; RV32DZFH-NEXT:    addi sp, sp, 16
 ; RV32DZFH-NEXT:    ret
 ;
 ; RV64DZFH-LABEL: constraint_f_half_abi_name:
 ; RV64DZFH:       # %bb.0:
 ; RV64DZFH-NEXT:    addi sp, sp, -16
 ; RV64DZFH-NEXT:    fsd fs0, 8(sp) # 8-byte Folded Spill
 ; RV64DZFH-NEXT:    lui a0, %hi(gh)
-; RV64DZFH-NEXT:    flh ft0, %lo(gh)(a0)
-; RV64DZFH-NEXT:    fcvt.d.h fa0, fa0
-; RV64DZFH-NEXT:    fcvt.d.h fs0, ft0
+; RV64DZFH-NEXT:    flh fs0, %lo(gh)(a0)
 ; RV64DZFH-NEXT:    #APP
 ; RV64DZFH-NEXT:    fadd.s ft0, fa0, fs0
 ; RV64DZFH-NEXT:    #NO_APP
-; RV64DZFH-NEXT:    fcvt.h.d fa0, ft0
+; RV64DZFH-NEXT:    fmv.h fa0, ft0
 ; RV64DZFH-NEXT:    fld fs0, 8(sp) # 8-byte Folded Reload
 ; RV64DZFH-NEXT:    addi sp, sp, 16
 ; RV64DZFH-NEXT:    ret
   %1 = load half, half* @gh
   %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1)
   ret half %2
 }