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Differential D116567

[RISCV] Don't advertise i32->i64 zextload as free for RV64.
ClosedPublic

Authored by craig.topper on Jan 3 2022, 4:39 PM.

Details

Reviewers
asb
luismarques
frasercrmck
Commits
rG75117fb340da: [RISCV] Don't advertise i32->i64 zextload as free for RV64.
Summary

The zextload hook is only used to determine whether to insert a
zero_extend or any_extend for narrow types leaving a basic block.
Returning true from this hook tends to cause any load whose output
leaves the basic block to become an LWU instead of an LW.

Since we tend to prefer sexts for i32 compares on RV64, this can
cause extra sext.w instructions to be created in other basic blocks.

If we use LW instead of LWU this gives the MIR pass from D116397
a better chance of removing them.

Another option might be to teach getPreferredExtendForValue in
FunctionLoweringInfo.cpp about our preference for sign_extend of
i32 compares. That would cause SIGN_EXTEND to be chosen for any
value used by a compare instead of using the isZExtFree heuristic.
That will require code to convert from the llvm::Type* to EVT/MVT
as well as querying the type legalization actions to get the
promoted type in order to call TargetLowering::isSExtCheaperThanZExt.
That seemed like many extra steps when no other target wants it.
Though it would avoid us needing to lean on the MIR pass in some cases.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 3 2022, 4:39 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptJan 3 2022, 4:39 PM
craig.topper requested review of this revision.Jan 3 2022, 4:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2022, 4:39 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B141402: Diff 397161.Jan 3 2022, 5:23 PM
asb accepted this revision.Jan 6 2022, 7:17 AM

I think in principle, leaving isZExtFree as-is and making other changes to resolve the issue around compares is better. But that's quite a lot more work, and this patch solves a real problem, so I'm happy to go with the pragmatic option, landing this patch as-is.

This revision is now accepted and ready to land.Jan 6 2022, 7:17 AM
This revision was landed with ongoing or failed builds.Jan 6 2022, 8:16 AM
Closed by commit rG75117fb340da: [RISCV] Don't advertise i32->i64 zextload as free for RV64. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG75117fb340da: [RISCV] Don't advertise i32->i64 zextload as free for RV64..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
5 lines
test/
CodeGen/
RISCV/
40 lines
8 lines
2 lines

Diff 397900

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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Show First 20 Lines • Show All 1,168 Lines • ▼ Show 20 Lines if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
return false; return false;
unsigned SrcBits = SrcVT.getSizeInBits(); unsigned SrcBits = SrcVT.getSizeInBits();
unsigned DestBits = DstVT.getSizeInBits(); unsigned DestBits = DstVT.getSizeInBits();
return (SrcBits == 64 && DestBits == 32); return (SrcBits == 64 && DestBits == 32);
} }
bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
// Zexts are free if they can be combined with a load. // Zexts are free if they can be combined with a load.
// Don't advertise i32->i64 zextload as being free for RV64. It interacts
// poorly with type legalization of compares preferring sext.
if (auto *LD = dyn_cast<LoadSDNode>(Val)) { if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
EVT MemVT = LD->getMemoryVT(); EVT MemVT = LD->getMemoryVT();
if ((MemVT == MVT::i8 || MemVT == MVT::i16 || if ((MemVT == MVT::i8 || MemVT == MVT::i16) &&
(Subtarget.is64Bit() && MemVT == MVT::i32)) &&
(LD->getExtensionType() == ISD::NON_EXTLOAD || (LD->getExtensionType() == ISD::NON_EXTLOAD ||
LD->getExtensionType() == ISD::ZEXTLOAD)) LD->getExtensionType() == ISD::ZEXTLOAD))
return true; return true;
} }
return TargetLowering::isZExtFree(Val, VT2); return TargetLowering::isZExtFree(Val, VT2);
} }
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llvm/test/CodeGen/RISCV/atomic-rmw.ll

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; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_max_i32_acquire: ; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
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; RV64I-LABEL: atomicrmw_max_i32_release: ; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
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; RV64I-LABEL: atomicrmw_max_i32_acq_rel: ; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
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; RV64I-LABEL: atomicrmw_max_i32_seq_cst: ; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
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; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_min_i32_acquire: ; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
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; RV64I-LABEL: atomicrmw_min_i32_release: ; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
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; RV64I-LABEL: atomicrmw_min_i32_acq_rel: ; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
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; RV64I-LABEL: atomicrmw_min_i32_seq_cst: ; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
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; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_umax_i32_acquire: ; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
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; RV64I-LABEL: atomicrmw_umax_i32_release: ; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
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; RV64I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
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; RV64I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
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; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_umin_i32_acquire: ; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
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; RV64I-LABEL: atomicrmw_umin_i32_release: ; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
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; RV64I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
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; RV64I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
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llvm/test/CodeGen/RISCV/atomic-signext.ll

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; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB32_2 ; RV64I-NEXT: j .LBB32_2
; RV64I-NEXT: .LBB32_1: # %atomicrmw.start ; RV64I-NEXT: .LBB32_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB33_2 ; RV64I-NEXT: j .LBB33_2
; RV64I-NEXT: .LBB33_1: # %atomicrmw.start ; RV64I-NEXT: .LBB33_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB34_2 ; RV64I-NEXT: j .LBB34_2
; RV64I-NEXT: .LBB34_1: # %atomicrmw.start ; RV64I-NEXT: .LBB34_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
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llvm/test/CodeGen/RISCV/inline-asm.ll

Show All 13 Lines
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: constraint_r: ; RV64I-LABEL: constraint_r:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(gi) ; RV64I-NEXT: lui a1, %hi(gi)
; RV64I-NEXT: lwu a1, %lo(gi)(a1) ; RV64I-NEXT: lw a1, %lo(gi)(a1)
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = load i32, i32* @gi %1 = load i32, i32* @gi
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
ret i32 %2 ret i32 %2
} }
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