Intrinsic for checking floating point class

[sepavloff]

Summary

This change introduces a new intrinsic, llvm.is.fclass, which checks
if the provided floating point number belongs to the specifies value
class. It implements the checks made by C standard library functions
isnan, isinf, isfinite, isnormal, issubnormal, issignaling
and corresponding IEEE-754 operations.

The primary motivation for this intrinsic is the support of strict FP
mode. In this mode using compare instructions or other FP operations is
not possible, because if the value is a signaling NaN, floating point
exception Invalid is raised, but the aforementioned functions must
never raise exceptions.

Currently there are two solutions for this problem, both are
implemented partially. One of them is using integer operations to
implement the check. It was implemented in https://reviews.llvm.org/D95948
for isnan. It solves the problem of exceptions, but offers one
solution for all targets, although some can do the check in more
efficient way.

The other, implemented in https://reviews.llvm.org/D96568, introduced a
hook 'clang::TargetCodeGenInfo::testFPKind', which injects a target
specific code into IR to implement isnan. It is convenient for
targets that has dedicated instruction to determine FP data class.
However using target-specific intrinsic complicates analysis and can
prevent some optimizations.

Using a special intrinsic to represent a value class check allows
representing data class test with enough flexibility. During IR
transformations it represents the check in target-independent way and
prevents it from undesired transformations. In the instruction selector
it allows efficient lowering depending on the target and used mode.

This implementation is an extended variant of llvm.isnan introduced
in https://reviews.llvm.org/D104854. It is limited to minimal intrinsic
support. Target-specific treatment will be implemented in separate
patches.

[sepavloff]

The patch was tested in runtime using extended version of tests https://reviews.llvm.org/D106804 and temporary clang patch that implements classification builtins by calls to llvm.is.fclass.

[arsenm]

llvm/docs/LangRef.rst

21984–21993

AMDGPU has a class instruction but the fields are a bit more expansive than this. Specifically, it has positive and negative versions of each of the non-nan fields. e.g. you can check specifically +inf separately from -inf, and the same for the rest.

I guess we could identify and (signbit check), (class %x, !foo)

[sepavloff]

Make test specification more flexible

Now test data class specification is not limited by the test necessary for
implementation of C classification functions, but is made more close to
the facility provided by data class inquiry instruction existing on many
targets.

The intrinsic is renamed to llvm.is_fpclass to use the similar naming as
in fpclassify.

The patch is rebased.

[sepavloff]

llvm/docs/LangRef.rst

21984–21993

Updated the patch to better represent targets with such instructions.

[sepavloff]

Updated patch

• Check for inverted test was moved into a separate function.
• Fixed code generation for negative zeros and normals check.
• Fixed code generation for snan checks.
• Number of codegen tests were reduced.

[sepavloff]

This patch was tested using a patches for clang https://reviews.llvm.org/D112932 and test-suite https://reviews.llvm.org/D112933. Clang build with the patch were used to compile llvm-test-suite/SingleSource/UnitTests/Float/classify.c. Running the obtained executable executes the unit tests.

[arsenm]

llvm/include/llvm/IR/Intrinsics.td

723

The word "is" here reads weird to me, and you dropped it from the ISD node name. How about just llvm.fpclass? Also the description says "fclass"

[sepavloff]

llvm/include/llvm/IR/Intrinsics.td

723

I agree that this name is a bit awkward. Initially it was llvm.fclass, as you noticed, but then it was changed because:

• it is inconsistent with C function fpclassify, which also may get a special llvm intrinsic,
• llvm.fclass might be understood as if the intrinsic calculated the value class. Actually it only tests the value against the specified classes.

[sepavloff]

Updated patch

• Use integer constants instead of metadata to represent fp class test.
• Added support for fp80.
• Renamed test, dropped the prefix 'x86-'.
• Prepared code for sharing with GlobalISel.

[sepavloff]

This patch with the set of dependent patches provides support of the intrinsic in IR and CodeGen. Default lowering is implemented using integer operations, IEEE and Intel 80-bit extended precision formats are supported in it. Custom lowering for non-IEEE types is provided in separate patches (D113908 and D113414). Targets that support FCLASS or similar instruction can have especially efficient implementation, a patch for SystemZ represents an example (D114695). Patches that implement support for this intrinsic in GlobalISel are also published (D121454 and D121296).

The patch includes large number of tests. To facilitate validation, a preliminary clang patch was prepared (D112932), which enables runtime testing. Appropriate change for test suite is also provided (D112933). The implementation was tested on X86 and AArch64 hardware and PowerPC emulator.

The intrinsic has evolved to rather generic form and a question may rise if it would be profitable to implement an intrinsic for fpclassify and then use it to implement classification functions. The drawback of the solution based on fpclassify is that this function returns a numeric value which is then exists in runtime. If a target provides instruction FCLASS, it would be convenient to have numerical representation of floating-point classes consistent with the output of FCLASS. Different targets use different layouts for FCLASS output, for example RISC-V, SystemZ and AMDGPU all have such instruction and all use different encoding. It is not possible to use FP class numbering that would be convenient for all targets. There is no such problem for is_fpclass. FP class numbers in this case are used in compile-time constants only.

[sepavloff]

Ping.

[sepavloff]

Any feedback?

[thopre]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

7130

Does them refer to unsupported values? So an exponent of 0 and a int_bit set is a supported value. But the equality check on line 7392 will return true for that case so I'm a bit confused.

7139

[sepavloff]

Fixed comments

[sepavloff]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

7130

You are right, the comment describes supported values. Thank you for the catch.

7139

Here you are also right. Fixed.

[thopre]

LGTM but I'd prefer someone else to approve.

[sepavloff]

In D112025#3464119, @thopre wrote:

LGTM but I'd prefer someone else to approve.

Thanks!
I'll wait for more feedback.

[efriedma]

llvm/docs/LangRef.rst

21991

*Quiet

21999

*Negative

22018

Maybe give an example here, e.g. 0x104 tests for a normal number.

Is there some reason the bits are arranged in this particular order? Not that I really have a better suggestion.

llvm/include/llvm/IR/Intrinsics.td

726

Did you mean to add ImmArg<ArgIndex<1>>?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

7012

You could try to handle more cases here, e.g. fcPosNormal is two comparisons. Not sure how worthwhile that is.

[sepavloff]

Addressed review notes. Rebased.

[sepavloff]

llvm/docs/LangRef.rst

22018

I put a small example explaining the use of 'test' argument.

As for bit representation of particular tests, it is practically arbitrary. The sequence of bits agrees with the sequence of classes specified by IEEE-754 in 5.7.2. If there were a better sequence, it would be no problems to change the bits.

llvm/include/llvm/IR/Intrinsics.td

726

Exactly! Thank you!

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

7012

These cases can be implemented with a single comparison operation. Other cases require more than one comparison. For example, the test fcPosNormal can be implemented as (x >= SmallestNormalized) && (x <= Largest). Also floating-point constant materialization may have some cost. The resulting gain is not obvious. For x86 floating point operations produce better code if SSE is available, but much worse code if x87 is used. So the advantage of floating point comparisons is target-dependent.

[efriedma]

LGTM

[sepavloff]

Thanks!

[nlopes]

Is the second argument required to be a constant? If so, it would be great to document that. Thanks!

[sepavloff]

In D112025#3485583, @nlopes wrote:

Is the second argument required to be a constant? If so, it would be great to document that. Thanks!

Fixed in https://github.com/llvm/llvm-project/commit/d9b5544e0f99656ac18e39daf31fa8231ea0d9ef.
Thanks!

[nlopes]

In D112025#3488141, @sepavloff wrote:

In D112025#3485583, @nlopes wrote:

Is the second argument required to be a constant? If so, it would be great to document that. Thanks!

Fixed in https://github.com/llvm/llvm-project/commit/d9b5544e0f99656ac18e39daf31fa8231ea0d9ef.
Thanks!

Thank you!
Will add support for this in Alive2 soonish.

[nlopes]

We believe that there's a bug when the 2nd argument is 0.
See here: https://gcc.godbolt.org/z/9735rYbqP

LLVM produces 1, but it should be 0. Found by @regehr.

[sepavloff]

In D112025#3527153, @nlopes wrote:

We believe that there's a bug when the 2nd argument is 0.
See here: https://gcc.godbolt.org/z/9735rYbqP

LLVM produces 1, but it should be 0. Found by @regehr.

Although this is a degenerated case and any result is possible, treating 2nd argument as a set of FP classes is more consistent with zero return value.
Thanks!

llvm/docs/LangRef.rst

 """"""""""
 
 The '``llvm.set.rounding``' intrinsic sets the current rounding mode. It is
 similar to C library function 'fesetround', however this intrinsic does not
 return any value and uses platform-independent representation of IEEE rounding
 modes.
 
 
+Floating Point Test Intrinsics
+------------------------------
+
+These functions get properties of floating point values.
+
+
+'``llvm.is.fpclass``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+::
+
+      declare i1 @llvm.is.fpclass(<fptype> <op>, metadata <test>)
+      declare <N x i1> @llvm.is.fpclass(<vector-fptype> <op>, metadata <test>)
+
+Overview:
+"""""""""
+
+The '``llvm.is.fpclass``' intrinsic returns a boolean value or vector of boolean
+values depending on whether the first argument satisfies the test specified by
+the second argument.
+
+If the first argument is a floating-point scalar, then the result type is a
+boolean (:ref:`i1 <t_integer>`).
+
+If the first argument is a floating-point vector, then the result type is a
+vector of boolean with the same number of elements as the first argument.
+
+Arguments:
+""""""""""
+
+The first argument to the '``llvm.is.fpclass``' intrinsic must be
+:ref:`floating-point <t_floating>` or :ref:`vector <t_vector>`
+of floating-point values.
+
+The second argument specifies the test to perform. It may represent a single
+data class name. Such test is string with one of the following values:
+- "``zero``": yields ``true`` if the value is a zero.
+- "``+zero``": yields ``true`` if the value is a positive zero.
+- "``-zero``": yields ``true`` if the value is a negative zero.
+- "``subnormal``": yields ``true`` if the value is subnormal.
+- "``+subnormal``": yields ``true`` if the value is positive subnormal.
+- "``-subnormal``": yields ``true`` if the value is negative subnormal.
+- "``normal``": yields ``true`` if the value is normal (neither zero, subnormal,
+  infinite, nor NaN).
+- "``+normal``": yields ``true`` if the value is positive normal.
+- "``-normal``": yields ``true`` if the value is positive normal.
+- "``finite``": yields ``true`` if the value is finite (not an infinity or NaN).
+- "``+finite``": yields ``true`` if the value is positive finite.
+- "``-finite``": yields ``true`` if the value is negatitive finite.
+- "``inf``": yields ``true`` if the value is an infinity.
+- "``+inf``": yields ``true`` if the value is a positive infinity.
+- "``-inf``": yields ``true`` if the value is a negative infinity.
+- "``nan``": yields ``true`` if the value is a NAN.
+- "``snan``": yields ``true`` if the value is a signaling NAN.
+- "``qnan``": yields ``true`` if the value is a quietNAN.
+The test aslo can be specified as a OR-ed combination of data classed, like
+"zero|subnormal|+inf". In this case a number satisfies the test if its data
+class is any of the combination.
+
+Semantics:
+""""""""""
+
+The function checks if ``op`` belongs to any of the floating point classes
+specified by ``test``. If ``op`` is a vector, then the check is made element by
+element. Each check yields an :ref:`i1 <t_integer>` result, which is ``true``,
+if the element value satisfies the specified test. The function never raises
+floating point exceptions.
+
+
 General Intrinsics
 ------------------
 
 This class of intrinsics is designed to be generic and has no specific
 purpose.
 
 '``llvm.var.annotation``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 

llvm/include/llvm/CodeGen/ISDOpcodes.h

 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares codegen opcodes and related utilities.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_ISDOPCODES_H
 #define LLVM_CODEGEN_ISDOPCODES_H
 
 #include "llvm/CodeGen/ValueTypes.h"
 
 namespace llvm {
 
+class Value;
+
 /// ISD namespace - This namespace contains an enum which represents all of the
 /// SelectionDAG node types and value types.
 ///
 namespace ISD {
 
 //===--------------------------------------------------------------------===//
 /// ISD::NodeType enum - This enum defines the target-independent operators
 /// for a SelectionDAG.
enum NodeType {
 
   /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
   /// value as an integer 0/1 value.
   FGETSIGN,
 
   /// Returns platform specific canonical encoding of a floating point number.
   FCANONICALIZE,
 
+  /// Performs a check of floating point class property, defined by IEEE-754.
+  /// The first operand is the floating point value to check. The second operand
+  /// specifies the checked property and is a TargetConstant with value obtained
+  /// from flags in FPClassCheck. Returns boolean value.
+  IS_FPCLASS,
+
   /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
   /// with the specified, possibly variable, elements. The types of the
   /// operands must match the vector element type, except that integer types
   /// are allowed to be larger than the element type, in which case the
   /// operands are implicitly truncated. The types of the operands must all
   /// be the same.
   BUILD_VECTOR,
 

 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type);
 
 /// Return the result of a logical AND between different comparisons of
 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type);
 
+/// Floating point class tests, supported by IS_FPCLASS node. Actual test may be
+/// an OR combination of these tests.
+enum FPClassCheck {
+  fcBad           = 0,
+  fcSNan          = 0x0001,
+  fcQNan          = 0x0002,
+  fcNegInf        = 0x0004,
+  fcNegNormal     = 0x0008,
+  fcNegSubnormal  = 0x0010,
+  fcNegZero       = 0x0020,
+  fcPosZero       = 0x0040,
+  fcPosSubnormal  = 0x0080,
+  fcPosNormal     = 0x0100,
+  fcPosInf        = 0x0200,
+
+  fcNan           = fcSNan | fcQNan,
+  fcInf           = fcPosInf | fcNegInf,
+  fcNormal        = fcPosNormal | fcNegNormal,
+  fcSubnormal     = fcPosSubnormal | fcNegSubnormal,
+  fcZero          = fcPosZero | fcNegZero,
+  fcPosFinite     = fcPosNormal | fcPosSubnormal | fcPosZero,
+  fcNegFinite     = fcNegNormal | fcNegSubnormal | fcNegZero,
+  fcFinite        = fcPosFinite | fcNegFinite,
+  fcAllFlags      = fcNan | fcInf | fcFinite
+};
+
+/// Convert floating point class test, which must be a metadata argument as
+/// specified in invocations of `is_fpclass`, into corresponding numeric code.
+unsigned getFPClassCheck(const Value *V);
+
 } // namespace ISD
 
 } // namespace llvm
 
 #endif

llvm/include/llvm/CodeGen/TargetLowering.h

   /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
   SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
 
   /// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
   /// \param N Node to expand
   /// \returns The expansion result
   SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const;
 
+  /// Expand check for floating point class.
+  /// \param ResultVT The type of intrinsic call result
+  /// \param Op The tested value
+  /// \param Check The test to perform
+  /// \param Flags The optimization flags
+  /// \returns The expansion result or SDValue() if it fails.
+  SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, unsigned Check,
+                           SDNodeFlags Flags, const SDLoc &DL,
+                           SelectionDAG &DAG) const;
+
+  /// Check if the specified FP class test is an inversion of a simpler test.
+  /// An example is the test "inf|normal|subnormal|zero", which is an inversion
+  /// of "nan".
+  /// \param Check The test as specified in IS_FPCLASS node.
+  /// \returns The inverted test, or zero, if inversion does not produce simpler
+  /// test.
+  unsigned checkInvertedFPClass(unsigned Check) const;
+
   /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
   /// vector nodes can only succeed if all operations are legal/custom.
   /// \param N Node to expand
   /// \returns The expansion result or SDValue() if it fails.
   SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const;
 
   /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
   /// vector nodes can only succeed if all operations are legal/custom.

llvm/include/llvm/IR/Intrinsics.td

 //===--------------- Access to Floating Point Environment -----------------===//
 //
 
 let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in {
   def int_flt_rounds    : DefaultAttrsIntrinsic<[llvm_i32_ty], []>;
   def int_set_rounding  : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>;
 }
 
+//===--------------- Floating Point Test Intrinsics -----------------------===//
+//
+
+def int_is_fpclass
+    : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+                            [llvm_anyfloat_ty, llvm_metadata_ty],
+                            [IntrNoMem, IntrWillReturn]>;
+
 //===--------------- Constrained Floating Point Intrinsics ----------------===//
 //
 
 let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in {
   def int_experimental_constrained_fadd : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

#endif
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_UMIN:
   case ISD::VECREDUCE_FMAX:
   case ISD::VECREDUCE_FMIN:
+  case ISD::IS_FPCLASS:
     Action = TLI.getOperationAction(
         Node->getOpcode(), Node->getOperand(0).getValueType());
     break;
   case ISD::VECREDUCE_SEQ_FADD:
   case ISD::VECREDUCE_SEQ_FMUL:
   case ISD::VP_REDUCE_FADD:
   case ISD::VP_REDUCE_FMUL:
   case ISD::VP_REDUCE_ADD:
case ISD::FCOPYSIGN:
     Results.push_back(ExpandFCOPYSIGN(Node));
     break;
   case ISD::FNEG:
     Results.push_back(ExpandFNEG(Node));
     break;
   case ISD::FABS:
     Results.push_back(ExpandFABS(Node));
     break;
+  case ISD::IS_FPCLASS: {
+    auto CNode = cast<ConstantSDNode>(Node->getOperand(1));
+    auto Check = static_cast<ISD::FPClassCheck>(CNode->getZExtValue());
+    if (SDValue Expanded =
+            TLI.expandIS_FPCLASS(Node->getValueType(0), Node->getOperand(0),
+                                 Check, Node->getFlags(), SDLoc(Node), DAG))
+      Results.push_back(Expanded);
+    break;
+  }
   case ISD::SMIN:
   case ISD::SMAX:
   case ISD::UMIN:
   case ISD::UMAX: {
     // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
     ISD::CondCode Pred;
     switch (Node->getOpcode()) {
     default: llvm_unreachable("How did we get here?");

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

case ISD::VP_SHL:
     Res = PromoteIntRes_SHL(N, /*IsVP*/ true);
     break;
   case ISD::VP_ASHR:
     Res = PromoteIntRes_SRA(N, /*IsVP*/ true);
     break;
   case ISD::VP_LSHR:
     Res = PromoteIntRes_SRL(N, /*IsVP*/ true);
     break;
+
+  case ISD::IS_FPCLASS:
+    Res = PromoteIntRes_IS_FPCLASS(N);
+    break;
   }
 
   // If the result is null then the sub-method took care of registering it.
   if (Res.getNode())
     SetPromotedInteger(SDValue(N, ResNo), Res);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
   } else
     SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
                         N->getOperand(1), N->getOperand(2));
 
   // Convert to the expected type.
   return DAG.getSExtOrTrunc(SetCC, dl, NVT);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
+  SDLoc DL(N);
+  SDValue Arg = N->getOperand(0);
+  SDValue Check = N->getOperand(1);
+  EVT NResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  return DAG.getNode(ISD::IS_FPCLASS, DL, NResVT, Arg, Check);
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N, bool IsVP) {
   SDValue LHS = GetPromotedInteger(N->getOperand(0));
   SDValue RHS = N->getOperand(1);
   if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
     RHS = ZExtPromotedInteger(RHS);
   if (!IsVP)
     return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
   return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue PromoteIntRes_MULFIX(SDNode *N);
   SDValue PromoteIntRes_DIVFIX(SDNode *N);
   SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
   SDValue PromoteIntRes_VECREDUCE(SDNode *N);
   SDValue PromoteIntRes_VP_REDUCE(SDNode *N);
   SDValue PromoteIntRes_ABS(SDNode *N);
   SDValue PromoteIntRes_Rotate(SDNode *N);
   SDValue PromoteIntRes_FunnelShift(SDNode *N);
+  SDValue PromoteIntRes_IS_FPCLASS(SDNode *N);
 
   // Integer Operand Promotion.
   bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
   SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
   SDValue PromoteIntOp_BITCAST(SDNode *N);
   SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
   SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
private:
   SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
   SDValue ScalarizeVecRes_VSELECT(SDNode *N);
   SDValue ScalarizeVecRes_SELECT(SDNode *N);
   SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
   SDValue ScalarizeVecRes_SETCC(SDNode *N);
   SDValue ScalarizeVecRes_UNDEF(SDNode *N);
   SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
   SDValue ScalarizeVecRes_FP_TO_XINT_SAT(SDNode *N);
+  SDValue ScalarizeVecRes_IS_FPCLASS(SDNode *N);
 
   SDValue ScalarizeVecRes_FIX(SDNode *N);
 
   // Vector Operand Scalarization: <1 x ty> -> ty.
   bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
   SDValue ScalarizeVecOp_BITCAST(SDNode *N);
   SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
   SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
private:
 
   void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
+  void SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
private:
   SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
   SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
   SDValue WidenVecRes_StrictFP(SDNode *N);
   SDValue WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo);
   SDValue WidenVecRes_Convert(SDNode *N);
   SDValue WidenVecRes_Convert_StrictFP(SDNode *N);
   SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N);
   SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
+  SDValue WidenVecRes_IS_FPCLASS(SDNode *N);
   SDValue WidenVecRes_POWI(SDNode *N);
   SDValue WidenVecRes_Unary(SDNode *N);
   SDValue WidenVecRes_InregOp(SDNode *N);
 
   // Widen Vector Operand.
   bool WidenVectorOperand(SDNode *N, unsigned OpNo);
   SDValue WidenVecOp_BITCAST(SDNode *N);
   SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
   SDValue WidenVecOp_EXTEND(SDNode *N);
   SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
   SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
   SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
   SDValue WidenVecOp_STORE(SDNode* N);
   SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
   SDValue WidenVecOp_MGATHER(SDNode* N, unsigned OpNo);
   SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo);
   SDValue WidenVecOp_SETCC(SDNode* N);
   SDValue WidenVecOp_STRICT_FSETCC(SDNode* N);
   SDValue WidenVecOp_VSELECT(SDNode *N);
 
   SDValue WidenVecOp_Convert(SDNode *N);
   SDValue WidenVecOp_FP_TO_XINT_SAT(SDNode *N);
   SDValue WidenVecOp_FCOPYSIGN(SDNode *N);
+  SDValue WidenVecOp_IS_FPCLASS(SDNode *N);
   SDValue WidenVecOp_VECREDUCE(SDNode *N);
   SDValue WidenVecOp_VECREDUCE_SEQ(SDNode *N);
 
   /// Helper function to generate a set of operations to perform
   /// a vector operation for a wider type.
   ///
   SDValue UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE);
 

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file performs vector type splitting and scalarization for LegalizeTypes.
#endif
   case ISD::SCALAR_TO_VECTOR:  R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
   case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
   case ISD::VSELECT:           R = ScalarizeVecRes_VSELECT(N); break;
   case ISD::SELECT:            R = ScalarizeVecRes_SELECT(N); break;
   case ISD::SELECT_CC:         R = ScalarizeVecRes_SELECT_CC(N); break;
   case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
+  case ISD::IS_FPCLASS:        R = ScalarizeVecRes_IS_FPCLASS(N); break;
   case ISD::ANY_EXTEND_VECTOR_INREG:
   case ISD::SIGN_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     R = ScalarizeVecRes_VecInregOp(N);
     break;
   case ISD::ABS:
   case ISD::ANY_EXTEND:
   case ISD::BITREVERSE:
SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
                             N->getOperand(2));
   // Vectors may have a different boolean contents to scalars.  Promote the
   // value appropriately.
   ISD::NodeType ExtendCode =
       TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
   return DAG.getNode(ExtendCode, DL, NVT, Res);
 }
 
+SDValue DAGTypeLegalizer::ScalarizeVecRes_IS_FPCLASS(SDNode *N) {
+  SDLoc DL(N);
+  SDValue Arg = N->getOperand(0);
+  SDValue Check = N->getOperand(1);
+  EVT ArgVT = Arg.getValueType();
+  EVT ResultVT = N->getValueType(0).getVectorElementType();
+
+  if (getTypeAction(ArgVT) == TargetLowering::TypeScalarizeVector) {
+    Arg = GetScalarizedVector(Arg);
+  } else {
+    EVT VT = ArgVT.getVectorElementType();
+    Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Arg,
+                      DAG.getVectorIdxConstant(0, DL));
+  }
+
+  SDValue Res =
+      DAG.getNode(ISD::IS_FPCLASS, DL, MVT::i1, {Arg, Check}, N->getFlags());
+  // Vectors may have a different boolean contents to scalars.  Promote the
+  // value appropriately.
+  ISD::NodeType ExtendCode =
+      TargetLowering::getExtendForContent(TLI.getBooleanContents(ArgVT));
+  return DAG.getNode(ExtendCode, DL, ResultVT, Res);
+}
 
 //===----------------------------------------------------------------------===//
 //  Operand Vector Scalarization <1 x ty> -> ty.
 //===----------------------------------------------------------------------===//
 
 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
   LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
              dbgs() << "\n");
#endif
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
   case ISD::BITCAST:           SplitVecRes_BITCAST(N, Lo, Hi); break;
   case ISD::BUILD_VECTOR:      SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
   case ISD::CONCAT_VECTORS:    SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
   case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
   case ISD::INSERT_SUBVECTOR:  SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
   case ISD::FPOWI:             SplitVecRes_FPOWI(N, Lo, Hi); break;
   case ISD::FCOPYSIGN:         SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
+  case ISD::IS_FPCLASS:        SplitVecRes_IS_FPCLASS(N, Lo, Hi); break;
   case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
   case ISD::SPLAT_VECTOR:
   case ISD::SCALAR_TO_VECTOR:
     SplitVecRes_ScalarOp(N, Lo, Hi);
     break;
   case ISD::STEP_VECTOR:
     SplitVecRes_STEP_VECTOR(N, Lo, Hi);
     break;
void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
   else
     std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
 
 
   Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
   Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
 }
 
+void DAGTypeLegalizer::SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo,
+                                              SDValue &Hi) {
+  SDLoc DL(N);
+  SDValue ArgLo, ArgHi;
+  SDValue Check = N->getOperand(1);
+  GetSplitVector(N->getOperand(0), ArgLo, ArgHi);
+  EVT LoVT, HiVT;
+  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+
+  Lo = DAG.getNode(ISD::IS_FPCLASS, DL, LoVT, ArgLo, Check, N->getFlags());
+  Hi = DAG.getNode(ISD::IS_FPCLASS, DL, HiVT, ArgHi, Check, N->getFlags());
+}
+
 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
   SDValue LHSLo, LHSHi;
   GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
   SDLoc dl(N);
 
   EVT LoVT, HiVT;
   std::tie(LoVT, HiVT) =
#include "llvm/IR/ConstrainedOps.def"
   case ISD::SMULO:
     Res = WidenVecRes_OverflowOp(N, ResNo);
     break;
 
   case ISD::FCOPYSIGN:
     Res = WidenVecRes_FCOPYSIGN(N);
     break;
 
+  case ISD::IS_FPCLASS:
+    Res = WidenVecRes_IS_FPCLASS(N);
+    break;
+
   case ISD::FPOWI:
     Res = WidenVecRes_POWI(N);
     break;
 
   case ISD::ANY_EXTEND_VECTOR_INREG:
   case ISD::SIGN_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
   if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
     return WidenVecRes_BinaryCanTrap(N);
 
   // If the types are different, fall back to unrolling.
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
 }
 
+SDValue DAGTypeLegalizer::WidenVecRes_IS_FPCLASS(SDNode *N) {
+  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  SDValue Arg = GetWidenedVector(N->getOperand(0));
+  return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, {Arg, N->getOperand(1)},
+                     N->getFlags());
+}
+
 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue InOp = GetWidenedVector(N->getOperand(0));
   SDValue ShOp = N->getOperand(1);
   return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
#endif
   case ISD::MSTORE:             Res = WidenVecOp_MSTORE(N, OpNo); break;
   case ISD::MGATHER:            Res = WidenVecOp_MGATHER(N, OpNo); break;
   case ISD::MSCATTER:           Res = WidenVecOp_MSCATTER(N, OpNo); break;
   case ISD::SETCC:              Res = WidenVecOp_SETCC(N); break;
   case ISD::STRICT_FSETCC:
   case ISD::STRICT_FSETCCS:     Res = WidenVecOp_STRICT_FSETCC(N); break;
   case ISD::VSELECT:            Res = WidenVecOp_VSELECT(N); break;
   case ISD::FCOPYSIGN:          Res = WidenVecOp_FCOPYSIGN(N); break;
+  case ISD::IS_FPCLASS:         Res = WidenVecOp_IS_FPCLASS(N); break;
 
   case ISD::ANY_EXTEND:
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
     Res = WidenVecOp_EXTEND(N);
     break;
 
   case ISD::FP_EXTEND:

 
 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
   // The result (and first input) is legal, but the second input is illegal.
   // We can't do much to fix that, so just unroll and let the extracts off of
   // the second input be widened as needed later.
   return DAG.UnrollVectorOp(N);
 }
 
+SDValue DAGTypeLegalizer::WidenVecOp_IS_FPCLASS(SDNode *N) {
+  SDLoc DL(N);
+  EVT ResultVT = N->getValueType(0);
+  SDValue Check = N->getOperand(1);
+  SDValue WideArg = GetWidenedVector(N->getOperand(0));
+
+  // Process this node similarly to SETCC.
+  EVT WideResultVT = getSetCCResultType(WideArg.getValueType());
+  if (ResultVT.getScalarType() == MVT::i1)
+    WideResultVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
+                                    WideResultVT.getVectorNumElements());
+
+  SDValue WideNode = DAG.getNode(ISD::IS_FPCLASS, DL, WideResultVT,
+                                 {WideArg, Check}, N->getFlags());
+
+  // Extract the needed results from the result vector.
+  EVT ResVT =
+      EVT::getVectorVT(*DAG.getContext(), WideResultVT.getVectorElementType(),
+                       ResultVT.getVectorNumElements());
+  SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, WideNode,
+                           DAG.getVectorIdxConstant(0, DL));
+
+  EVT OpVT = N->getOperand(0).getValueType();
+  ISD::NodeType ExtendCode =
+      TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
+  return DAG.getNode(ExtendCode, DL, ResultVT, CC);
+}
+
 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
   // Since the result is legal and the input is illegal.
   EVT VT = N->getValueType(0);
   EVT EltVT = VT.getVectorElementType();
   SDLoc dl(N);
   unsigned NumElts = VT.getVectorNumElements();
   SDValue InOp = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
   assert(getTypeAction(InOp.getValueType()) ==

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (IsInteger) {
     case ISD::SETOLT: Result = ISD::SETULT  ; break;  // SETULT & SETNE
     case ISD::SETOGT: Result = ISD::SETUGT  ; break;  // SETUGT & SETNE
     }
   }
 
   return Result;
 }
 
+unsigned ISD::getFPClassCheck(const llvm::Value *V) {
+  Metadata *MD = cast<MetadataAsValue>(V)->getMetadata();
+  if (!MD || !isa<MDString>(MD))
+    return ISD::FPClassCheck::fcBad;
+  StringRef Val = cast<MDString>(MD)->getString();
+  unsigned Res = 0;
+  do {
+    StringRef Flag;
+    std::tie(Flag, Val) = Val.split("|");
+    unsigned FlagVal = StringSwitch<unsigned>(Flag)
+                           .Case("+zero", fcPosZero)
+                           .Case("-zero", fcNegZero)
+                           .Case("zero", fcZero)
+                           .Case("+subnormal", fcPosSubnormal)
+                           .Case("-subnormal", fcNegSubnormal)
+                           .Case("subnormal", fcSubnormal)
+                           .Case("+normal", fcPosNormal)
+                           .Case("-normal", fcNegNormal)
+                           .Case("normal", fcNormal)
+                           .Case("+finite", fcPosFinite)
+                           .Case("-finite", fcNegFinite)
+                           .Case("finite", fcFinite)
+                           .Case("+inf", fcPosInf)
+                           .Case("-inf", fcNegInf)
+                           .Case("inf", fcInf)
+                           .Case("qnan", fcQNan)
+                           .Case("snan", fcSNan)
+                           .Case("nan", fcNan)
+                           .Default(fcBad);
+    assert(FlagVal != fcBad && "Invalid fpclass test");
+    Res |= FlagVal;
+  } while (!Val.empty());
+  return Res;
+}
+
 //===----------------------------------------------------------------------===//
 //                           SDNode Profile Support
 //===----------------------------------------------------------------------===//
 
 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)  {
   ID.AddInteger(OpC);
 }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::set_rounding:
     setValue(&I, Res);
     DAG.setRoot(Res.getValue(0));
     return;
   case Intrinsic::pcmarker: {
     SDValue Tmp = getValue(I.getArgOperand(0));
     DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
     return;
   }
+  case Intrinsic::is_fpclass: {
+    const DataLayout DLayout = DAG.getDataLayout();
+    EVT DestVT = TLI.getValueType(DLayout, I.getType());
+    EVT ArgVT = TLI.getValueType(DLayout, I.getArgOperand(0)->getType());
+    unsigned FC = ISD::getFPClassCheck(I.getArgOperand(1));
+    assert(FC != ISD::fcBad);
+    MachineFunction &MF = DAG.getMachineFunction();
+    const Function &F = MF.getFunction();
+    SDValue Op = getValue(I.getArgOperand(0));
+    SDNodeFlags Flags;
+    Flags.setNoFPExcept(
+        !F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP));
+    // If ISD::IS_FPCLASS should be expanded, do it right now, because the
+    // expansion can use illegal types. Making expansion early allows
+    // legalizing these types prior to selection.
+    if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) {
+      SDValue Result = TLI.expandIS_FPCLASS(DestVT, Op, FC, Flags, sdl, DAG);
+      setValue(&I, Result);
+      return;
+    }
+
+    SDValue Check = DAG.getTargetConstant(FC, sdl, MVT::i32);
+    SDValue V = DAG.getNode(ISD::IS_FPCLASS, sdl, DestVT, {Op, Check}, Flags);
+    setValue(&I, V);
+    return;
+  }
   case Intrinsic::readcyclecounter: {
     SDValue Op = getRoot();
     Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
                       DAG.getVTList(MVT::i64, MVT::Other), Op);
     setValue(&I, Res);
     DAG.setRoot(Res.getValue(1));
     return;
   }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

 //===- SelectionDAGDumper.cpp - Implement SelectionDAG::dump() ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This implements the SelectionDAG::dump method and friends.
#endif
   case ISD::FMA:                        return "fma";
   case ISD::STRICT_FMA:                 return "strict_fma";
   case ISD::FMAD:                       return "fmad";
   case ISD::FREM:                       return "frem";
   case ISD::STRICT_FREM:                return "strict_frem";
   case ISD::FCOPYSIGN:                  return "fcopysign";
   case ISD::FGETSIGN:                   return "fgetsign";
   case ISD::FCANONICALIZE:              return "fcanonicalize";
+  case ISD::IS_FPCLASS:                 return "is_fpclass";
   case ISD::FPOW:                       return "fpow";
   case ISD::STRICT_FPOW:                return "strict_fpow";
   case ISD::SMIN:                       return "smin";
   case ISD::SMAX:                       return "smax";
   case ISD::UMIN:                       return "umin";
   case ISD::UMAX:                       return "umax";
 
   case ISD::FPOWI:                      return "fpowi";

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (Node->getFlags().hasNoNaNs()) {
     Flags.setNoSignedZeros(true);
     SelCC->setFlags(Flags);
     return SelCC;
   }
 
   return SDValue();
 }
 
+SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
+                                         unsigned Check, SDNodeFlags Flags,
+                                         const SDLoc &DL,
+                                         SelectionDAG &DAG) const {
+  EVT OperandVT = Op.getValueType();
+  assert(OperandVT.isFloatingPoint());
+
+  APInt InvertMask = APInt::getAllOnesValue(ResultVT.getScalarSizeInBits());
+  SDValue InvertMaskV = DAG.getConstant(InvertMask, DL, ResultVT);
+
+  bool IsInverted = false;
+  if (unsigned InvertedCheck = checkInvertedFPClass(Check)) {
+    IsInverted = true;
+    Check = InvertedCheck;
+  }
+
+  // Some checks can be implemented using float comparisons, if floating point
+  // exceptions are ignored.
+  if (Flags.hasNoFPExcept() &&
+      isOperationLegalOrCustom(ISD::SETCC, OperandVT.getScalarType())) {
+    if (Check == ISD::fcZero)
+      return DAG.getSetCC(DL, ResultVT, Op,
+                          DAG.getConstantFP(0.0, DL, OperandVT),
+                          IsInverted ? ISD::SETUNE : ISD::SETOEQ);
+    if (Check == ISD::fcNan)
+      return DAG.getSetCC(DL, ResultVT, Op, Op,
+                          IsInverted ? ISD::SETO : ISD::SETUO);
+  }
+
+  // In the general case use integer operations. They also allow avoiding
+  // floating point exceptions.
+  unsigned BitSize = OperandVT.getScalarSizeInBits();
+  EVT IntVT = OperandVT.changeTypeToInteger();
+  SDValue OpAsInt = DAG.getBitcast(IntVT, Op);
+
+  EVT ScalarFloatVT = OperandVT.getScalarType();
+  const Type *FloatTy = ScalarFloatVT.getTypeForEVT(*DAG.getContext());
+  const llvm::fltSemantics &Semantics = FloatTy->getFltSemantics();
+
+  APInt SignMask = APInt::getSignedMaxValue(BitSize);
+  APInt SignBit = APInt::getSignMask(BitSize);
+  APInt ExpMask = APFloat::getInf(Semantics).bitcastToAPInt();
+  APInt AllOneMantissa =
+      APFloat::getLargest(Semantics).bitcastToAPInt() & ~ExpMask;
+  APInt QNaNBitMask = AllOneMantissa & ~(AllOneMantissa.lshr(1));
+
+  SDValue SignMaskV = DAG.getConstant(SignMask, DL, IntVT);
+  SDValue SignBitV = DAG.getConstant(SignBit, DL, IntVT);
+  SDValue ExpMaskV = DAG.getConstant(ExpMask, DL, IntVT);
+
+  SDValue Res;
+  const auto CombineResult = [&](SDValue V) -> bool {
+    if (!V)
+      return false;
+    if (IsInverted) {
+      assert(!Res);
+      Res = DAG.getNode(ISD::XOR, DL, ResultVT, V, InvertMaskV);
+      return true;
+    }
+    if (Res)
+      Res = DAG.getNode(ISD::OR, DL, ResultVT, Res, V);
+    else
+      Res = V;
+    return false;
+  };
+
+  // Split the value into sign bit and absolute value.
+  SDValue AbsV = DAG.getNode(ISD::AND, DL, IntVT, OpAsInt, SignMaskV);
+  SDValue SignV = DAG.getSetCC(DL, ResultVT, OpAsInt,
+                               DAG.getConstant(0.0, DL, IntVT), ISD::SETLT);
+
+  // The tests that involve more than one data classes should be processed
+  // first.
+  SDValue PartialRes;
+
+  unsigned PartialCheck = Check & ISD::fcFinite;
+  if (PartialCheck == ISD::fcFinite) {
+    // finite(V) ==> exp mask > abs(V)
+    PartialRes = DAG.getSetCC(DL, ResultVT, ExpMaskV, AbsV, ISD::SETGT);
+    Check &= ~ISD::fcFinite;
+  } else if (PartialCheck == ISD::fcPosFinite) {
+    // finite(V) && V > 0 ==> exp mask > V
+    PartialRes = DAG.getSetCC(DL, ResultVT, ExpMaskV, OpAsInt, ISD::SETUGT);
+    Check &= ~ISD::fcPosFinite;
+  } else if (PartialCheck == ISD::fcNegFinite) {
+    // finite(V) && V < 0 ==> exp mask > abs(V) && signbit == 1
+    PartialRes = DAG.getSetCC(DL, ResultVT, ExpMaskV, AbsV, ISD::SETGT);
+    PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
+    Check &= ~ISD::fcNegFinite;
+  }
+  if (CombineResult(PartialRes))
+    return Res;
+
+  // Check for individual classes.
+
+  PartialCheck = Check & ISD::fcZero;
+  if (PartialCheck) {
+    if (PartialCheck == ISD::fcPosZero)
+      PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt,
+                                DAG.getConstant(0, DL, IntVT), ISD::SETEQ);
+    else if (PartialCheck == ISD::fcZero)
+      PartialRes = DAG.getSetCC(DL, ResultVT, AbsV,
+                                DAG.getConstant(0, DL, IntVT), ISD::SETEQ);
+    else // ISD::fcNegZero
+      PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, SignBitV, ISD::SETEQ);
+    if (CombineResult(PartialRes))
+      return Res;
+  }
+
+  PartialCheck = Check & ISD::fcInf;
+  if (PartialCheck) {
+    if (PartialCheck == ISD::fcPosInf)
+      PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, ExpMaskV, ISD::SETEQ);
+    else if (PartialCheck == ISD::fcInf)
+      PartialRes = DAG.getSetCC(DL, ResultVT, ExpMaskV, AbsV, ISD::SETEQ);
+    else { // ISD::fcNegInf
+      APInt NegInf = APFloat::getInf(Semantics, true).bitcastToAPInt();
+      SDValue NegInfV = DAG.getConstant(NegInf, DL, IntVT);
+      PartialRes = DAG.getSetCC(DL, ResultVT, OpAsInt, NegInfV, ISD::SETEQ);
+    }
+    if (CombineResult(PartialRes))
+      return Res;
+  }
+
+  PartialCheck = Check & ISD::fcNan;
+  if (PartialCheck) {
+    APInt ExpWithQNaNBit = ExpMask | QNaNBitMask;
+    SDValue ExpWithQNaNBitV = DAG.getConstant(ExpWithQNaNBit, DL, IntVT);
+    if (PartialCheck == ISD::fcNan)
+      // isnan(V) ==> exp mask < abs(V)
+      PartialRes = DAG.getSetCC(DL, ResultVT, ExpMaskV, AbsV, ISD::SETLT);
+    else if (PartialCheck == ISD::fcQNan)
+      // isquiet(V) ==> unsigned(V) >= exp_mask | quiet_bit
+      PartialRes =
+          DAG.getSetCC(DL, ResultVT, AbsV, ExpWithQNaNBitV, ISD::SETGE);
+    else { // ISD::fcSNan
+      // issignaling(V) ==> abs(V) > exp_mask &&
+      //                    abs(V) < (exp_mask | quiet_bit)
+      SDValue IsNaN = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETGT);
+      SDValue IsNotQNaN =
+          DAG.getSetCC(DL, ResultVT, AbsV, ExpWithQNaNBitV, ISD::SETLT);
+      PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, IsNaN, IsNotQNaN);
+    }
+    if (CombineResult(PartialRes))
+      return Res;
+  }
+
+  PartialCheck = Check & ISD::fcSubnormal;
+  if (PartialCheck) {
+    // issubnormal(V) ==> unsigned(abs(V) - 1) < (all mantissa bits set)
+    // issubnormal(V) && V>0 ==> unsigned(V - 1) < (all mantissa bits set)
+    SDValue V = (PartialCheck == ISD::fcPosSubnormal) ? OpAsInt : AbsV;
+    SDValue MantissaV = DAG.getConstant(AllOneMantissa, DL, IntVT);
+    SDValue MinusOneV =
+        DAG.getNode(ISD::SUB, DL, IntVT, V, DAG.getConstant(1, DL, IntVT));
+    PartialRes = DAG.getSetCC(DL, ResultVT, MinusOneV, MantissaV, ISD::SETULT);
+    if (PartialCheck == ISD::fcNegSubnormal)
+      PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
+    if (CombineResult(PartialRes))
+      return Res;
+  }
+
+  PartialCheck = Check & ISD::fcNormal;
+  if (PartialCheck) {
+    // isnormal(V) ==> (0 < exp < max_exp) == (unsigned(exp-1) < (max_exp-1))
+    APInt ExpLSB = ExpMask & ~(ExpMask.shl(1));
+    SDValue ExpLSBV = DAG.getConstant(ExpLSB, DL, IntVT);
+    SDValue DecExp = DAG.getNode(ISD::SUB, DL, IntVT, AbsV, ExpLSBV);
+    APInt ExpLimit = ExpMask - ExpLSB;
+    SDValue ExpLimitV = DAG.getConstant(ExpLimit, DL, IntVT);
+    PartialRes = DAG.getSetCC(DL, ResultVT, DecExp, ExpLimitV, ISD::SETULT);
+    if (PartialCheck == ISD::fcNegNormal)
+      PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
+    else if (PartialCheck == ISD::fcPosNormal) {
+      SDValue PosSignV =
+          DAG.getNode(ISD::XOR, DL, ResultVT, SignV, InvertMaskV);
+      PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, PosSignV);
+    }
+    if (CombineResult(PartialRes))
+      return Res;
+  }
+
+  return Res;
+}
+
+unsigned TargetLowering::checkInvertedFPClass(unsigned Test) const {
+  unsigned InvertedTest = ~Test & ISD::fcAllFlags;
+  switch (InvertedTest) {
+  default:
+    break;
+  case ISD::fcNan:
+  case ISD::fcSNan:
+  case ISD::fcQNan:
+  case ISD::fcInf:
+  case ISD::fcPosInf:
+  case ISD::fcNegInf:
+  case ISD::fcNormal:
+  case ISD::fcPosNormal:
+  case ISD::fcNegNormal:
+  case ISD::fcSubnormal:
+  case ISD::fcPosSubnormal:
+  case ISD::fcNegSubnormal:
+  case ISD::fcZero:
+  case ISD::fcPosZero:
+  case ISD::fcNegZero:
+  case ISD::fcFinite:
+  case ISD::fcPosFinite:
+  case ISD::fcNegFinite:
+    return InvertedTest;
+  }
+  return 0;
+}
+
 // Only expand vector types if we have the appropriate vector bit operations.
 static bool canExpandVectorCTPOP(const TargetLowering &TLI, EVT VT) {
   assert(VT.isVector() && "Expected vector type");
   unsigned Len = VT.getScalarSizeInBits();
   return TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
          TLI.isOperationLegalOrCustom(ISD::SUB, VT) &&
          TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
          (Len == 8 || TLI.isOperationLegalOrCustom(ISD::MUL, VT)) &&

llvm/lib/CodeGen/TargetLoweringBase.cpp

for (unsigned IM = (unsigned)ISD::PRE_INC;
       setIndexedMaskedStoreAction(IM, VT, Expand);
     }
 
     // Most backends expect to see the node which just returns the value loaded.
     setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
 
     // These operations default to expand.
     setOperationAction(ISD::FGETSIGN, VT, Expand);
+    setOperationAction(ISD::IS_FPCLASS, VT, Expand);
     setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
     setOperationAction(ISD::FMINNUM, VT, Expand);
     setOperationAction(ISD::FMAXNUM, VT, Expand);
     setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
     setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
     setOperationAction(ISD::FMINIMUM, VT, Expand);
     setOperationAction(ISD::FMAXIMUM, VT, Expand);
     setOperationAction(ISD::FMAD, VT, Expand);

llvm/test/CodeGen/X86/x86-is_fpclass.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 | FileCheck %s -check-prefix=CHECK-32
+; RUN: llc < %s -mtriple=x86_64 | FileCheck %s -check-prefix=CHECK-64
+
+define i1 @isnan_f(float %x) {
+; CHECK-32-LABEL: isnan_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ucomiss %xmm0, %xmm0
+; CHECK-64-NEXT:    setp %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"nan")
+  ret i1 %0
+}
+
+define i1 @isnot_nan_f(float %x) {
+; CHECK-32-LABEL: isnot_nan_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnot_nan_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ucomiss %xmm0, %xmm0
+; CHECK-64-NEXT:    setnp %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"zero|subnormal|normal|inf")
+  ret i1 %0
+}
+
+define i1 @issignaling_f(float %x) {
+; CHECK-32-LABEL: issignaling_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2143289344, %eax # imm = 0x7FC00000
+; CHECK-32-NEXT:    setl %cl
+; CHECK-32-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: issignaling_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2143289344, %eax # imm = 0x7FC00000
+; CHECK-64-NEXT:    setl %cl
+; CHECK-64-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-64-NEXT:    setge %al
+; CHECK-64-NEXT:    andb %cl, %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"snan")
+  ret i1 %0
+}
+
+define i1 @isquiet_f(float %x) {
+; CHECK-32-LABEL: isquiet_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2143289344, %eax # imm = 0x7FC00000
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isquiet_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2143289344, %eax # imm = 0x7FC00000
+; CHECK-64-NEXT:    setge %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"qnan")
+  ret i1 %0
+}
+
+define i1 @isinf_f(float %x) {
+; CHECK-32-LABEL: isinf_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isinf_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"inf")
+  ret i1 %0
+}
+
+define i1 @is_plus_inf_f(float %x) {
+; CHECK-32-LABEL: is_plus_inf_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_plus_inf_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"+inf")
+  ret i1 %0
+}
+
+define i1 @is_minus_inf_f(float %x) {
+; CHECK-32-LABEL: is_minus_inf_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_minus_inf_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    cmpl $-8388608, %eax # imm = 0xFF800000
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"-inf")
+  ret i1 %0
+}
+
+define i1 @isfinite_f(float %x) {
+; CHECK-32-LABEL: isfinite_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isfinite_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    setl %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"finite")
+  ret i1 %0
+}
+
+define i1 @is_plus_finite_f(float %x) {
+; CHECK-32-LABEL: is_plus_finite_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_plus_finite_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"+finite")
+  ret i1 %0
+}
+
+define i1 @is_minus_finite_f(float %x) {
+; CHECK-32-LABEL: is_minus_finite_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    testl %eax, %eax
+; CHECK-32-NEXT:    sets %cl
+; CHECK-32-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_minus_finite_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    testl %eax, %eax
+; CHECK-64-NEXT:    sets %cl
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    setl %al
+; CHECK-64-NEXT:    andb %cl, %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"-finite")
+  ret i1 %0
+}
+
+define i1 @isnormal_f(float %x) {
+; CHECK-32-LABEL: isnormal_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    addl $-8388608, %eax # imm = 0xFF800000
+; CHECK-32-NEXT:    cmpl $2130706432, %eax # imm = 0x7F000000
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnormal_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    addl $-8388608, %eax # imm = 0xFF800000
+; CHECK-64-NEXT:    cmpl $2130706432, %eax # imm = 0x7F000000
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"normal")
+  ret i1 %0
+}
+
+define i1 @is_plus_normal_f(float %x) {
+; CHECK-32-LABEL: is_plus_normal_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    testl %eax, %eax
+; CHECK-32-NEXT:    setns %cl
+; CHECK-32-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    addl $-8388608, %eax # imm = 0xFF800000
+; CHECK-32-NEXT:    cmpl $2130706432, %eax # imm = 0x7F000000
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_plus_normal_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    testl %eax, %eax
+; CHECK-64-NEXT:    setns %cl
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    addl $-8388608, %eax # imm = 0xFF800000
+; CHECK-64-NEXT:    cmpl $2130706432, %eax # imm = 0x7F000000
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    andb %cl, %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"+normal")
+  ret i1 %0
+}
+
+define i1 @issubnormal_f(float %x) {
+; CHECK-32-LABEL: issubnormal_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    decl %eax
+; CHECK-32-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: issubnormal_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    decl %eax
+; CHECK-64-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"subnormal")
+  ret i1 %0
+}
+
+define i1 @is_plus_subnormal_f(float %x) {
+; CHECK-32-LABEL: is_plus_subnormal_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    decl %eax
+; CHECK-32-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_plus_subnormal_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    decl %eax
+; CHECK-64-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"+subnormal")
+  ret i1 %0
+}
+
+define i1 @is_minus_subnormal_f(float %x) {
+; CHECK-32-LABEL: is_minus_subnormal_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    testl %eax, %eax
+; CHECK-32-NEXT:    sets %cl
+; CHECK-32-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    decl %eax
+; CHECK-32-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_minus_subnormal_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    testl %eax, %eax
+; CHECK-64-NEXT:    sets %cl
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    decl %eax
+; CHECK-64-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    andb %cl, %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"-subnormal")
+  ret i1 %0
+}
+
+define i1 @iszero_f(float %x) {
+; CHECK-32-LABEL: iszero_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fldz
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %cl
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: iszero_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    xorps %xmm1, %xmm1
+; CHECK-64-NEXT:    cmpeqss %xmm0, %xmm1
+; CHECK-64-NEXT:    movd %xmm1, %eax
+; CHECK-64-NEXT:    andl $1, %eax
+; CHECK-64-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"zero")
+  ret i1 %0
+}
+
+define i1 @is_plus_zero_f(float %x) {
+; CHECK-32-LABEL: is_plus_zero_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_plus_zero_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    testl %eax, %eax
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"+zero")
+  ret i1 %0
+}
+
+define i1 @is_minus_zero_f(float %x) {
+; CHECK-32-LABEL: is_minus_zero_f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmpl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: is_minus_zero_f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    cmpl $-2147483648, %eax # imm = 0x80000000
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"-zero")
+  ret i1 %0
+}
+
+
+
+define i1 @isnan_f_strictfp(float %x) strictfp {
+; CHECK-32-LABEL: isnan_f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-64-NEXT:    setge %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"nan")
+  ret i1 %0
+}
+
+define i1 @isfinite_f_strictfp(float %x) strictfp {
+; CHECK-32-LABEL: isfinite_f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isfinite_f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT:    setl %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"finite")
+  ret i1 %0
+}
+
+define i1 @iszero_f_strictfp(float %x) strictfp {
+; CHECK-32-LABEL: iszero_f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: iszero_f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    testl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f32(float %x, metadata !"zero")
+  ret i1 %0
+}
+
+
+define i1 @isnan_d(double %x) {
+; CHECK-32-LABEL: isnan_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ucomisd %xmm0, %xmm0
+; CHECK-64-NEXT:    setp %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"nan")
+  ret i1 %0
+}
+
+define i1 @isinf_d(double %x) {
+; CHECK-32-LABEL: isinf_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    xorl $2146435072, %eax # imm = 0x7FF00000
+; CHECK-32-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isinf_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"inf")
+  ret i1 %0
+}
+
+define i1 @isfinite_d(double %x) {
+; CHECK-32-LABEL: isfinite_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2146435072, %eax # imm = 0x7FF00000
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isfinite_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setl %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"finite")
+  ret i1 %0
+}
+
+define i1 @isnormal_d(double %x) {
+; CHECK-32-LABEL: isnormal_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    addl $-1048576, %eax # imm = 0xFFF00000
+; CHECK-32-NEXT:    shrl $21, %eax
+; CHECK-32-NEXT:    cmpl $1023, %eax # imm = 0x3FF
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnormal_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
+; CHECK-64-NEXT:    addq %rcx, %rax
+; CHECK-64-NEXT:    shrq $53, %rax
+; CHECK-64-NEXT:    cmpl $1023, %eax # imm = 0x3FF
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"normal")
+  ret i1 %0
+}
+
+define i1 @issubnormal_d(double %x) {
+; CHECK-32-LABEL: issubnormal_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    addl $-1, %eax
+; CHECK-32-NEXT:    adcl $-1, %ecx
+; CHECK-32-NEXT:    cmpl $-1, %eax
+; CHECK-32-NEXT:    sbbl $1048575, %ecx # imm = 0xFFFFF
+; CHECK-32-NEXT:    setb %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: issubnormal_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    decq %rcx
+; CHECK-64-NEXT:    movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setb %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"subnormal")
+  ret i1 %0
+}
+
+define i1 @iszero_d(double %x) {
+; CHECK-32-LABEL: iszero_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fldz
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %cl
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: iszero_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    xorpd %xmm1, %xmm1
+; CHECK-64-NEXT:    cmpeqsd %xmm0, %xmm1
+; CHECK-64-NEXT:    movq %xmm1, %rax
+; CHECK-64-NEXT:    andl $1, %eax
+; CHECK-64-NEXT:    # kill: def $al killed $al killed $rax
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"zero")
+  ret i1 %0
+}
+
+define i1 @issignaling_d(double %x) {
+; CHECK-32-LABEL: issignaling_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    xorl %ecx, %ecx
+; CHECK-32-NEXT:    cmpl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    movl $2146435072, %ecx # imm = 0x7FF00000
+; CHECK-32-NEXT:    sbbl %eax, %ecx
+; CHECK-32-NEXT:    setl %cl
+; CHECK-32-NEXT:    cmpl $2146959360, %eax # imm = 0x7FF80000
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    andb %cl, %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: issignaling_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setl %dl
+; CHECK-64-NEXT:    movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setg %al
+; CHECK-64-NEXT:    andb %dl, %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"snan")
+  ret i1 %0
+}
+
+define i1 @isquiet_d(double %x) {
+; CHECK-32-LABEL: isquiet_d:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2146959360, %eax # imm = 0x7FF80000
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isquiet_d:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setg %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"qnan")
+  ret i1 %0
+}
+
+define i1 @isnan_d_strictfp(double %x) strictfp {
+; CHECK-32-LABEL: isnan_d_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    xorl %ecx, %ecx
+; CHECK-32-NEXT:    cmpl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    movl $2146435072, %ecx # imm = 0x7FF00000
+; CHECK-32-NEXT:    sbbl %eax, %ecx
+; CHECK-32-NEXT:    setl %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_d_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-64-NEXT:    andq %rax, %rcx
+; CHECK-64-NEXT:    movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; CHECK-64-NEXT:    cmpq %rax, %rcx
+; CHECK-64-NEXT:    setg %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"nan")
+  ret i1 %0
+}
+
+define i1 @iszero_d_strictfp(double %x) strictfp {
+; CHECK-32-LABEL: iszero_d_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: iszero_d_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movq %xmm0, %rax
+; CHECK-64-NEXT:    shlq $1, %rax
+; CHECK-64-NEXT:    testq %rax, %rax
+; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, metadata !"zero")
+  ret i1 %0
+}
+
+
+
+define <1 x i1> @isnan_v1f(<1 x float> %x) {
+; CHECK-32-LABEL: isnan_v1f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_v1f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ucomiss %xmm0, %xmm0
+; CHECK-64-NEXT:    setp %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, metadata !"nan")
+  ret <1 x i1> %0
+}
+
+define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp {
+; CHECK-32-LABEL: isnan_v1f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_v1f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    movd %xmm0, %eax
+; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-64-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-64-NEXT:    setge %al
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, metadata !"nan")
+  ret <1 x i1> %0
+}
+
+define <2 x i1> @isnan_v2f(<2 x float> %x) {
+; CHECK-32-LABEL: isnan_v2f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %cl
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %dl
+; CHECK-32-NEXT:    movl %ecx, %eax
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_v2f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    cmpunordps %xmm0, %xmm0
+; CHECK-64-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, metadata !"nan")
+  ret <2 x i1> %0
+}
+
+
+define <2 x i1> @isnot_nan_v2f(<2 x float> %x) {
+; CHECK-32-LABEL: isnot_nan_v2f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %cl
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %dl
+; CHECK-32-NEXT:    movl %ecx, %eax
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnot_nan_v2f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    cmpordps %xmm0, %xmm0
+; CHECK-64-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, metadata !"zero|subnormal|normal|inf")
+  ret <2 x i1> %0
+}
+
+define <2 x i1> @isnan_v2f_strictfp(<2 x float> %x) strictfp {
+; CHECK-32-LABEL: isnan_v2f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    andl %ecx, %eax
+; CHECK-32-NEXT:    cmpl $2139095041, %eax # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %al
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    cmpl $2139095041, %ecx # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %dl
+; CHECK-32-NEXT:    retl
+;
+; CHECK-64-LABEL: isnan_v2f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; CHECK-64-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-64-NEXT:    pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, metadata !"nan")
+  ret <2 x i1> %0
+}
+
+define <4 x i1> @isnan_v4f(<4 x float> %x) {
+; CHECK-32-LABEL: isnan_v4f:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %dh
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %dl
+; CHECK-32-NEXT:    addb %dl, %dl
+; CHECK-32-NEXT:    orb %dh, %dl
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %dh
+; CHECK-32-NEXT:    fucomp %st(0)
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setp %al
+; CHECK-32-NEXT:    addb %al, %al
+; CHECK-32-NEXT:    orb %dh, %al
+; CHECK-32-NEXT:    shlb $2, %al
+; CHECK-32-NEXT:    orb %dl, %al
+; CHECK-32-NEXT:    movb %al, (%ecx)
+; CHECK-32-NEXT:    movl %ecx, %eax
+; CHECK-32-NEXT:    retl $4
+;
+; CHECK-64-LABEL: isnan_v4f:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    cmpunordps %xmm0, %xmm0
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, metadata !"nan")
+  ret <4 x i1> %0
+}
+
+define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
+; CHECK-32-LABEL: isnan_v4f_strictfp:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    pushl %esi
+; CHECK-32-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-32-NEXT:    .cfi_offset %esi, -8
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-32-NEXT:    andl %ecx, %edx
+; CHECK-32-NEXT:    cmpl $2139095041, %edx # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %dh
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-32-NEXT:    andl %ecx, %esi
+; CHECK-32-NEXT:    cmpl $2139095041, %esi # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %dl
+; CHECK-32-NEXT:    addb %dl, %dl
+; CHECK-32-NEXT:    orb %dh, %dl
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-32-NEXT:    andl %ecx, %esi
+; CHECK-32-NEXT:    cmpl $2139095041, %esi # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %dh
+; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    cmpl $2139095041, %ecx # imm = 0x7F800001
+; CHECK-32-NEXT:    setge %cl
+; CHECK-32-NEXT:    addb %cl, %cl
+; CHECK-32-NEXT:    orb %dh, %cl
+; CHECK-32-NEXT:    shlb $2, %cl
+; CHECK-32-NEXT:    orb %dl, %cl
+; CHECK-32-NEXT:    movb %cl, (%eax)
+; CHECK-32-NEXT:    popl %esi
+; CHECK-32-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-32-NEXT:    retl $4
+;
+; CHECK-64-LABEL: isnan_v4f_strictfp:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-64-NEXT:    pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-64-NEXT:    retq
+entry:
+  %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, metadata !"nan")
+  ret <4 x i1> %0
+}
+
+
+declare i1 @llvm.is.fpclass.f32(float, metadata)
+declare i1 @llvm.is.fpclass.f64(double, metadata)
+declare <1 x i1> @llvm.is.fpclass.v1f32(<1 x float>, metadata)
+declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, metadata)
+declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, metadata)