[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

496

Comment here needs updating for the right opcodes

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

492 ↗

(On Diff #351600)

Seems like this test is regressing. Is there a one-use check that may help here?

[craig.topper]

Limit to cases where mul has a single use. There may be a better heuristic here,
but this is a simple starting point.

[frasercrmck]

LGTM, cheers!

[eopXD]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

485

I am not familiar with SD Patterns and the TableGen syntax, so I may be wrong.

According to v-spec:

vmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]

Shouldn't $rs1 be multiplying with $rs2 here?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

485

Aren't these patterns for

vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i]

[eopXD]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

485

Ah I see. You are correct.
Thank you for answering!

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   case CASE_VFMA_SPLATS(FMSAC):
   case CASE_VFMA_SPLATS(FNMADD):
   case CASE_VFMA_SPLATS(FNMSUB):
   case CASE_VFMA_SPLATS(FNMACC):
   case CASE_VFMA_SPLATS(FNMSAC):
   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
+  case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV):
+  case CASE_VFMA_OPCODE_LMULS(MADD, VX):
+  case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
+  case CASE_VFMA_OPCODE_LMULS(MACC, VX):
+  case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
+  case CASE_VFMA_OPCODE_LMULS(MACC, VV):
+  case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
     // For these instructions we can only swap operand 1 and operand 3 by
     // changing the opcode.
     unsigned CommutableOpIdx1 = 1;
     unsigned CommutableOpIdx2 = 3;
     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
                               CommutableOpIdx2))
       return false;
     return true;
   }
   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
+  case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV):
+  case CASE_VFMA_OPCODE_LMULS(MADD, VV):
+  case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
     // For these instructions we have more freedom. We can commute with the
     // other multiplicand or with the addend/subtrahend/minuend.
 
     // Any fixed operand must be from source 1, 2 or 3.
     if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
       return false;
     if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
       return false;
MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   case CASE_VFMA_SPLATS(FMSUB):
   case CASE_VFMA_SPLATS(FNMACC):
   case CASE_VFMA_SPLATS(FNMADD):
   case CASE_VFMA_SPLATS(FNMSAC):
   case CASE_VFMA_SPLATS(FNMSUB):
   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
+  case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV):
+  case CASE_VFMA_OPCODE_LMULS(MADD, VX):
+  case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
+  case CASE_VFMA_OPCODE_LMULS(MACC, VX):
+  case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
+  case CASE_VFMA_OPCODE_LMULS(MACC, VV):
+  case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
     // It only make sense to toggle these between clobbering the
     // addend/subtrahend/minuend one of the multiplicands.
     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
     assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
     unsigned Opc;
     switch (MI.getOpcode()) {
       default:
         llvm_unreachable("Unexpected opcode");
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
       CASE_VFMA_CHANGE_OPCODE_LMULS(FMACC, FMADD, VV)
       CASE_VFMA_CHANGE_OPCODE_LMULS(FMSAC, FMSUB, VV)
       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMACC, FNMADD, VV)
       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSAC, FNMSUB, VV)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VX)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VX)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV)
+      CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VV)
     }
 
     auto &WorkingMI = cloneIfNew(MI);
     WorkingMI.setDesc(get(Opc));
     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
                                                    OpIdx1, OpIdx2);
   }
   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
+  case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV):
+  case CASE_VFMA_OPCODE_LMULS(MADD, VV):
+  case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
     // If one of the operands, is the addend we need to change opcode.
     // Otherwise we're just swapping 2 of the multiplicands.
     if (OpIdx1 == 3 || OpIdx2 == 3) {
       unsigned Opc;
       switch (MI.getOpcode()) {
         default:
           llvm_unreachable("Unexpected opcode");
         CASE_VFMA_CHANGE_OPCODE_LMULS(FMADD, FMACC, VV)
         CASE_VFMA_CHANGE_OPCODE_LMULS(FMSUB, FMSAC, VV)
         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMADD, FNMACC, VV)
         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSUB, FNMSAC, VV)
+        CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV)
+        CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VV)
       }
 
       auto &WorkingMI = cloneIfNew(MI);
       WorkingMI.setDesc(get(Opc));
       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
                                                      OpIdx1, OpIdx2);
     }
     // Let the default code handle it.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList.m in
     defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
 multiclass VPseudoTernaryV_VV_VX_AAXA<string Constraint = ""> {
   defm "" : VPseudoTernaryV_VV<Constraint>;
   defm "" : VPseudoTernaryV_VX_AAXA<Constraint>;
+
+  foreach m = MxList.m in {
+    // Add a commutable version for use by IR fma.
+    // NOTE: We need this because we use a tail undisturbed policy on the
+    // intrinsic version so we can't commute those instructions since it would
+    // change which input operand is tied to the destination. That would
+    // remove user control of the tail elements.
+    let isCommutable = 1, ForceTailAgnostic = true, VLMul = m.value in {
+      def "_VV_" # m.MX # "_COMMUTABLE" : VPseudoTernaryNoMask<m.vrclass,
+                                                               m.vrclass,
+                                                               m.vrclass,
+                                                               Constraint>;
+      def "_VX_" # m.MX # "_COMMUTABLE" :
+         VPseudoTernaryNoMask<m.vrclass, GPR, m.vrclass, Constraint>;
+    }
+  }
 }
 
 multiclass VPseudoTernaryV_VV_VF_AAXA<string Constraint = ""> {
   defm "" : VPseudoTernaryV_VV<Constraint>;
   defm "" : VPseudoTernaryV_VF_AAXA<Constraint>;
 
   foreach m = MxList.m in {
     // Add a commutable version for use by IR fma.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
 def SplatPat_simm5_plus1
     : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1",
                      [splat_vector, rv32_splat_i64], [], 2>;
 def SplatPat_simm5_plus1_nonzero
     : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero",
                      [splat_vector, rv32_splat_i64], [], 2>;
 
+def mul_oneuse : PatFrag<(ops node:$A, node:$B), (mul node:$A, node:$B), [{
+  return N->hasOneUse();
+}]>;
+
+
 class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
    dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
 }
 
 multiclass VPatUSLoadStoreSDNode<ValueType type,
                                  int log2sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,

 defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
 
 // 12.11. Vector Integer Divide Instructions
 defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
 defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
 defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
 defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
 
+// 12.13 Vector Single-Width Integer Multiply-Add Instructions.
+foreach vti = AllIntegerVectors in {
+  // NOTE: We choose VMADD because it has the most commuting freedom. So it
+  // works best with how TwoAddressInstructionPass tries commuting.
+  defvar suffix = vti.LMul.MX # "_COMMUTABLE";
+  def : Pat<(vti.Vector (add vti.RegClass:$rs2,
+                              (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
+            (!cast<Instruction>("PseudoVMADD_VV_"# suffix)
+                 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW)>;
+  def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
+                              (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
+            (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix)
+                 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW)>;
+
+  // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
+  // commutable.
+  def : Pat<(vti.Vector (add vti.RegClass:$rs2,
+                              (mul_oneuse (SplatPat XLenVT:$rs1),
+                                          vti.RegClass:$rd))),
+            (!cast<Instruction>("PseudoVMADD_VX_" # suffix)
+                 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW)>;
+  def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
+                              (mul_oneuse (SplatPat XLenVT:$rs1),
+                                          vti.RegClass:$rd))),
+            (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
+                 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW)>;
+}
+
 // 12.15. Vector Integer Merge Instructions
 foreach vti = AllIntegerVectors in {
   def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
                                                       vti.RegClass:$rs2)),
             (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
                  vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
                  vti.AVL, vti.Log2SEW)>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL",
                                                         SDTCVecEltisVT<2, i1>,
                                                         SDTCisVT<3, XLenVT>]>>;
 
 def SDTRVVVecReduce : SDTypeProfile<1, 4, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
   SDTCisSameNumEltsAs<1, 3>, SDTCisVT<4, XLenVT>
 ]>;
 
+def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D),
+                                  (riscv_mul_vl node:$A, node:$B, node:$C,
+                                                node:$D), [{
+  return N->hasOneUse();
+}]>;
+
 foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR",
                 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in
   def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>;
 
 // Ignore the vl operand.
 def SplatFPOp : PatFrag<(ops node:$op),
                         (riscv_vfmv_v_f_vl node:$op, srcvalue)>;
 

 defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">;
 
 // 12.11. Vector Integer Divide Instructions
 defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">;
 defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
 defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
 defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
 
+// 12.13 Vector Single-Width Integer Multiply-Add Instructions
+foreach vti = AllIntegerVectors in {
+  // NOTE: We choose VMADD because it has the most commuting freedom. So it
+  // works best with how TwoAddressInstructionPass tries commuting.
+  defvar suffix = vti.LMul.MX # "_COMMUTABLE";
+  def : Pat<(vti.Vector
+             (riscv_add_vl vti.RegClass:$rs2,
+                           (riscv_mul_vl_oneuse vti.RegClass:$rs1,
+                                                vti.RegClass:$rd,
+                                                (vti.Mask true_mask), VLOpFrag),
+                           (vti.Mask true_mask), VLOpFrag)),
+            (!cast<Instruction>("PseudoVMADD_VV_"# suffix)
+                 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 GPR:$vl, vti.Log2SEW)>;
+  def : Pat<(vti.Vector
+             (riscv_sub_vl vti.RegClass:$rs2,
+                           (riscv_mul_vl_oneuse vti.RegClass:$rs1,
+                                                vti.RegClass:$rd,
+                                                (vti.Mask true_mask), VLOpFrag),
+                           (vti.Mask true_mask), VLOpFrag)),
+            (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix)
+                 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 GPR:$vl, vti.Log2SEW)>;
+
+  // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
+  // commutable.
+  def : Pat<(vti.Vector
+             (riscv_add_vl vti.RegClass:$rs2,
+                           (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
+                                                vti.RegClass:$rd,
+                                                (vti.Mask true_mask), VLOpFrag),
+                           (vti.Mask true_mask), VLOpFrag)),
+            (!cast<Instruction>("PseudoVMADD_VX_" # suffix)
+                 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 GPR:$vl, vti.Log2SEW)>;
+  def : Pat<(vti.Vector
+             (riscv_sub_vl vti.RegClass:$rs2,
+                           (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
+                                                vti.RegClass:$rd,
+                                                (vti.Mask true_mask),
+                                                VLOpFrag),
+                           (vti.Mask true_mask), VLOpFrag)),
+            (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
+                 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 GPR:$vl, vti.Log2SEW)>;
+}
+
 // 12.15. Vector Integer Merge Instructions
 foreach vti = AllIntegerVectors in {
   def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm),
                                           vti.RegClass:$rs1,
                                           vti.RegClass:$rs2,
                                           VLOpFrag)),
             (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
                  vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 ; RV32-NEXT:    vmulh.vv v26, v25, v26
 ; RV32-NEXT:    addi a1, zero, 3
 ; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; RV32-NEXT:    vmv.v.i v27, -1
 ; RV32-NEXT:    vmerge.vim v27, v27, 0, v0
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT:    vmul.vv v25, v25, v27
-; RV32-NEXT:    vadd.vv v25, v26, v25
+; RV32-NEXT:    vmadd.vv v27, v25, v26
 ; RV32-NEXT:    addi a1, zero, 63
-; RV32-NEXT:    vsrl.vx v26, v25, a1
+; RV32-NEXT:    vsrl.vx v25, v27, a1
 ; RV32-NEXT:    addi a1, zero, 1
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT:    vmv.s.x v27, a1
+; RV32-NEXT:    vmv.s.x v26, a1
 ; RV32-NEXT:    vmv.v.i v28, 0
 ; RV32-NEXT:    vsetivli zero, 3, e32, m1, tu, mu
-; RV32-NEXT:    vslideup.vi v28, v27, 2
+; RV32-NEXT:    vslideup.vi v28, v26, 2
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT:    vsra.vv v25, v25, v28
-; RV32-NEXT:    vadd.vv v25, v25, v26
+; RV32-NEXT:    vsra.vv v26, v27, v28
+; RV32-NEXT:    vadd.vv v25, v26, v25
 ; RV32-NEXT:    vse64.v v25, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhs_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.v.i v26, -1
 ; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
 ; RV64-NEXT:    vmv.s.x v26, zero
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmul.vv v26, v25, v26
 ; RV64-NEXT:    lui a1, 21845
 ; RV64-NEXT:    addiw a1, a1, 1365
 ; RV64-NEXT:    slli a1, a1, 12
 ; RV64-NEXT:    addi a1, a1, 1365
 ; RV64-NEXT:    slli a1, a1, 12
 ; RV64-NEXT:    addi a1, a1, 1365
 ; RV64-NEXT:    slli a1, a1, 12
 ; RV64-NEXT:    addi a2, a1, 1365
+; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.v.x v27, a2
 ; RV64-NEXT:    addi a1, a1, 1366
 ; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
 ; RV64-NEXT:    vmv.s.x v27, a1
 ; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulh.vv v25, v25, v27
-; RV64-NEXT:    vadd.vv v25, v25, v26
+; RV64-NEXT:    vmulh.vv v27, v25, v27
+; RV64-NEXT:    vmacc.vv v27, v25, v26
 ; RV64-NEXT:    addi a1, zero, 63
-; RV64-NEXT:    vsrl.vx v26, v25, a1
-; RV64-NEXT:    vid.v v27
-; RV64-NEXT:    vsra.vv v25, v25, v27
-; RV64-NEXT:    vadd.vv v25, v25, v26
+; RV64-NEXT:    vsrl.vx v25, v27, a1
+; RV64-NEXT:    vid.v v26
+; RV64-NEXT:    vsra.vv v26, v27, v26
+; RV64-NEXT:    vadd.vv v25, v26, v25
 ; RV64-NEXT:    vse64.v v25, (a0)
 ; RV64-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = sdiv <2 x i64> %a, <i64 3, i64 -3>
   store <2 x i64> %b, <2 x i64>* %x
   ret void
 }
 
; LMULMAX1-RV64-NEXT:    ret
   ret void
 }
 
 define void @mulhs_v4i64(<4 x i64>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhs_v4i64:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
-; LMULMAX2-RV32-NEXT:    addi a1, zero, 51
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v28, -1
-; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vmul.vv v28, v26, v28
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 17
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a2, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a2
+; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a2
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1366
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a1, v0
+; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vmulh.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT:    vmulh.vv v28, v26, v28
+; LMULMAX2-RV32-NEXT:    addi a1, zero, 51
+; LMULMAX2-RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
+; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
+; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; LMULMAX2-RV32-NEXT:    vmv.v.i v30, -1
+; LMULMAX2-RV32-NEXT:    vmerge.vim v30, v30, 0, v0
+; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
+; LMULMAX2-RV32-NEXT:    vmadd.vv v30, v26, v28
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 63
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a1
+; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v30, a1
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 68
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
-; LMULMAX2-RV32-NEXT:    vmerge.vim v30, v30, 1, v0
+; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 0
+; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT:    vsra.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT:    vsra.vv v28, v30, v28
+; LMULMAX2-RV32-NEXT:    vadd.vv v26, v28, v26
 ; LMULMAX2-RV32-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhs_v4i64:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; LMULMAX2-RV64-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 5
 ; LMULMAX2-RV64-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a1
 ; LMULMAX2-RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, -1
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 0, v0
-; LMULMAX2-RV64-NEXT:    vmul.vv v28, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 21845
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a2, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vmv.v.x v30, a2
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1366
 ; LMULMAX2-RV64-NEXT:    vmerge.vxm v30, v30, a1, v0
-; LMULMAX2-RV64-NEXT:    vmulh.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT:    vmulh.vv v30, v26, v30
+; LMULMAX2-RV64-NEXT:    vmacc.vv v30, v26, v28
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 63
-; LMULMAX2-RV64-NEXT:    vsrl.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT:    vmv.v.i v30, 1
-; LMULMAX2-RV64-NEXT:    vmerge.vim v30, v30, 0, v0
-; LMULMAX2-RV64-NEXT:    vsra.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT:    vsrl.vx v26, v30, a1
+; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 1
+; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 0, v0
+; LMULMAX2-RV64-NEXT:    vsra.vv v28, v30, v28
+; LMULMAX2-RV64-NEXT:    vadd.vv v26, v28, v26
 ; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: mulhs_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16

 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV64-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV64-NEXT:    vle64.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v27, -1
 ; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
 ; LMULMAX1-RV64-NEXT:    vmv.s.x v27, zero
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vmul.vv v28, v26, v27
 ; LMULMAX1-RV64-NEXT:    lui a2, 21845
 ; LMULMAX1-RV64-NEXT:    addiw a2, a2, 1365
 ; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
 ; LMULMAX1-RV64-NEXT:    addi a2, a2, 1365
 ; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
 ; LMULMAX1-RV64-NEXT:    addi a2, a2, 1365
 ; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
 ; LMULMAX1-RV64-NEXT:    addi a3, a2, 1365
-; LMULMAX1-RV64-NEXT:    vmv.v.x v29, a3
+; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v28, a3
 ; LMULMAX1-RV64-NEXT:    addi a2, a2, 1366
 ; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT:    vmv.s.x v29, a2
+; LMULMAX1-RV64-NEXT:    vmv.s.x v28, a2
 ; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vmulh.vv v26, v26, v29
-; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX1-RV64-NEXT:    vmulh.vv v29, v26, v28
+; LMULMAX1-RV64-NEXT:    vmacc.vv v29, v27, v26
 ; LMULMAX1-RV64-NEXT:    addi a2, zero, 63
-; LMULMAX1-RV64-NEXT:    vsrl.vx v28, v26, a2
+; LMULMAX1-RV64-NEXT:    vsrl.vx v26, v29, a2
 ; LMULMAX1-RV64-NEXT:    vid.v v30
-; LMULMAX1-RV64-NEXT:    vsra.vv v26, v26, v30
-; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v28
-; LMULMAX1-RV64-NEXT:    vmul.vv v27, v25, v27
-; LMULMAX1-RV64-NEXT:    vmulh.vv v25, v25, v29
-; LMULMAX1-RV64-NEXT:    vadd.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT:    vsrl.vx v27, v25, a2
-; LMULMAX1-RV64-NEXT:    vsra.vv v25, v25, v30
-; LMULMAX1-RV64-NEXT:    vadd.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT:    vsra.vv v29, v29, v30
+; LMULMAX1-RV64-NEXT:    vadd.vv v26, v29, v26
+; LMULMAX1-RV64-NEXT:    vmulh.vv v28, v25, v28
+; LMULMAX1-RV64-NEXT:    vmacc.vv v28, v25, v27
+; LMULMAX1-RV64-NEXT:    vsrl.vx v25, v28, a2
+; LMULMAX1-RV64-NEXT:    vsra.vv v27, v28, v30
+; LMULMAX1-RV64-NEXT:    vadd.vv v25, v27, v25
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    vse64.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
+; This tests a mix of vmacc and vmadd by using different operand orders to
+; trigger commuting in TwoAddressInstructionPass.
+
+define <vscale x 1 x i8> @vmadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i8> %va, %vb
+  %y = add <vscale x 1 x i8> %x, %vc
+  ret <vscale x 1 x i8> %y
+}
+
+define <vscale x 1 x i8> @vmadd_vx_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i8> %va, %splat
+  %y = add <vscale x 1 x i8> %x, %vb
+  ret <vscale x 1 x i8> %y
+}
+
+define <vscale x 2 x i8> @vmadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i8> %va, %vc
+  %y = add <vscale x 2 x i8> %x, %vb
+  ret <vscale x 2 x i8> %y
+}
+
+define <vscale x 2 x i8> @vmadd_vx_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i8> %vb, %splat
+  %y = add <vscale x 2 x i8> %x, %va
+  ret <vscale x 2 x i8> %y
+}
+
+define <vscale x 4 x i8> @vmadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i8> %vb, %va
+  %y = add <vscale x 4 x i8> %x, %vc
+  ret <vscale x 4 x i8> %y
+}
+
+define <vscale x 4 x i8> @vmadd_vx_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i8> %va, %splat
+  %y = add <vscale x 4 x i8> %x, %vb
+  ret <vscale x 4 x i8> %y
+}
+
+define <vscale x 8 x i8> @vmadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i8> %vb, %vc
+  %y = add <vscale x 8 x i8> %x, %va
+  ret <vscale x 8 x i8> %y
+}
+
+define <vscale x 8 x i8> @vmadd_vx_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i8> %vb, %splat
+  %y = add <vscale x 8 x i8> %x, %va
+  ret <vscale x 8 x i8> %y
+}
+
+define <vscale x 16 x i8> @vmadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i8> %vc, %va
+  %y = add <vscale x 16 x i8> %x, %vb
+  ret <vscale x 16 x i8> %y
+}
+
+define <vscale x 16 x i8> @vmadd_vx_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i8> %va, %splat
+  %y = add <vscale x 16 x i8> %x, %vb
+  ret <vscale x 16 x i8> %y
+}
+
+define <vscale x 32 x i8> @vmadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 32 x i8> %vc, %vb
+  %y = add <vscale x 32 x i8> %x, %va
+  ret <vscale x 32 x i8> %y
+}
+
+define <vscale x 32 x i8> @vmadd_vx_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %x = mul <vscale x 32 x i8> %vb, %splat
+  %y = add <vscale x 32 x i8> %x, %va
+  ret <vscale x 32 x i8> %y
+}
+
+define <vscale x 64 x i8> @vmadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i8> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 64 x i8> %vc, %vb
+  %y = add <vscale x 64 x i8> %x, %va
+  ret <vscale x 64 x i8> %y
+}
+
+define <vscale x 64 x i8> @vmadd_vx_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vmadd_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %x = mul <vscale x 64 x i8> %vb, %splat
+  %y = add <vscale x 64 x i8> %x, %va
+  ret <vscale x 64 x i8> %y
+}
+
+define <vscale x 1 x i16> @vmadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i16> %va, %vb
+  %y = add <vscale x 1 x i16> %x, %vc
+  ret <vscale x 1 x i16> %y
+}
+
+define <vscale x 1 x i16> @vmadd_vx_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i16> %va, %splat
+  %y = add <vscale x 1 x i16> %x, %vb
+  ret <vscale x 1 x i16> %y
+}
+
+define <vscale x 2 x i16> @vmadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i16> %va, %vc
+  %y = add <vscale x 2 x i16> %x, %vb
+  ret <vscale x 2 x i16> %y
+}
+
+define <vscale x 2 x i16> @vmadd_vx_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i16> %vb, %splat
+  %y = add <vscale x 2 x i16> %x, %va
+  ret <vscale x 2 x i16> %y
+}
+
+define <vscale x 4 x i16> @vmadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i16> %vb, %va
+  %y = add <vscale x 4 x i16> %x, %vc
+  ret <vscale x 4 x i16> %y
+}
+
+define <vscale x 4 x i16> @vmadd_vx_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i16> %va, %splat
+  %y = add <vscale x 4 x i16> %x, %vb
+  ret <vscale x 4 x i16> %y
+}
+
+define <vscale x 8 x i16> @vmadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i16> %vb, %vc
+  %y = add <vscale x 8 x i16> %x, %va
+  ret <vscale x 8 x i16> %y
+}
+
+define <vscale x 8 x i16> @vmadd_vx_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i16> %vb, %splat
+  %y = add <vscale x 8 x i16> %x, %va
+  ret <vscale x 8 x i16> %y
+}
+
+define <vscale x 16 x i16> @vmadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i16> %vc, %va
+  %y = add <vscale x 16 x i16> %x, %vb
+  ret <vscale x 16 x i16> %y
+}
+
+define <vscale x 16 x i16> @vmadd_vx_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i16> %va, %splat
+  %y = add <vscale x 16 x i16> %x, %vb
+  ret <vscale x 16 x i16> %y
+}
+
+define <vscale x 32 x i16> @vmadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i16> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 32 x i16> %vc, %vb
+  %y = add <vscale x 32 x i16> %x, %va
+  ret <vscale x 32 x i16> %y
+}
+
+define <vscale x 32 x i16> @vmadd_vx_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vmadd_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %x = mul <vscale x 32 x i16> %vb, %splat
+  %y = add <vscale x 32 x i16> %x, %va
+  ret <vscale x 32 x i16> %y
+}
+
+define <vscale x 1 x i32> @vmadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i32> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i32> %va, %vb
+  %y = add <vscale x 1 x i32> %x, %vc
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vmadd_vx_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vmadd_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i32> %va, %splat
+  %y = add <vscale x 1 x i32> %x, %vb
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vmadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i32> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i32> %va, %vc
+  %y = add <vscale x 2 x i32> %x, %vb
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vmadd_vx_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vmadd_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i32> %vb, %splat
+  %y = add <vscale x 2 x i32> %x, %va
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vmadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i32> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v10, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i32> %vb, %va
+  %y = add <vscale x 4 x i32> %x, %vc
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vmadd_vx_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vmadd_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i32> %va, %splat
+  %y = add <vscale x 4 x i32> %x, %vb
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vmadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i32> %vb, %vc
+  %y = add <vscale x 8 x i32> %x, %va
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vmadd_vx_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vmadd_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmacc.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i32> %vb, %splat
+  %y = add <vscale x 8 x i32> %x, %va
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 16 x i32> @vmadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i32> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v24, v16
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i32> %vc, %va
+  %y = add <vscale x 16 x i32> %x, %vb
+  ret <vscale x 16 x i32> %y
+}
+
+define <vscale x 16 x i32> @vmadd_vx_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vmadd_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmadd.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i32> %va, %splat
+  %y = add <vscale x 16 x i32> %x, %vb
+  ret <vscale x 16 x i32> %y
+}
+
+define <vscale x 1 x i64> @vmadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i64> %va, %vb
+  %y = add <vscale x 1 x i64> %x, %vc
+  ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vmadd_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) {
+; RV32-LABEL: vmadd_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v25, (a0), zero
+; RV32-NEXT:    vmadd.vv v8, v25, v9
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmadd_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vmadd.vx v8, a0, v9
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i64> %va, %splat
+  %y = add <vscale x 1 x i64> %x, %vb
+  ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 2 x i64> @vmadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i64> %va, %vc
+  %y = add <vscale x 2 x i64> %x, %vb
+  ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vmadd_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) {
+; RV32-LABEL: vmadd_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v26, (a0), zero
+; RV32-NEXT:    vmacc.vv v8, v10, v26
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmadd_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vmacc.vx v8, a0, v10
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i64> %vb, %splat
+  %y = add <vscale x 2 x i64> %x, %va
+  ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 4 x i64> @vmadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vmadd.vv v8, v12, v16
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i64> %vb, %va
+  %y = add <vscale x 4 x i64> %x, %vc
+  ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vmadd_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) {
+; RV32-LABEL: vmadd_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v28, (a0), zero
+; RV32-NEXT:    vmadd.vv v8, v28, v12
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmadd_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vmadd.vx v8, a0, v12
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i64> %va, %splat
+  %y = add <vscale x 4 x i64> %x, %vb
+  ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 8 x i64> @vmadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vmadd_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vmacc.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i64> %vb, %vc
+  %y = add <vscale x 8 x i64> %x, %va
+  ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vmadd_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) {
+; RV32-LABEL: vmadd_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v24, (a0), zero
+; RV32-NEXT:    vmacc.vv v8, v16, v24
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vmadd_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vmacc.vx v8, a0, v16
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i64> %vb, %splat
+  %y = add <vscale x 8 x i64> %x, %va
+  ret <vscale x 8 x i64> %y
+}

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that the prepareSREMEqFold optimization doesn't crash on scalable
 ; vector types.
 define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: srem_eq_fold_nxv4i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -85
-; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT:    vmul.vx v25, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 42
-; CHECK-NEXT:    vadd.vx v25, v25, a0
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a1, zero, -85
+; CHECK-NEXT:    vmacc.vx v25, a1, v8
 ; CHECK-NEXT:    vsll.vi v26, v25, 7
 ; CHECK-NEXT:    vsrl.vi v25, v25, 1
 ; CHECK-NEXT:    vor.vv v25, v25, v26
 ; CHECK-NEXT:    vmsleu.vx v0, v25, a0
 ; CHECK-NEXT:    ret
   %head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
   %splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %rem = srem <vscale x 4 x i8> %va, %splat_six
 
   %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
   ret <vscale x 4 x i1> %cc
 }

llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
+; This tests a mix of vmacc and vmsub by using different operand orders to
+; trigger commuting in TwosubressInstructionPass.
+
+define <vscale x 1 x i8> @vnmsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i8> %va, %vb
+  %y = sub <vscale x 1 x i8> %vc, %x
+  ret <vscale x 1 x i8> %y
+}
+
+define <vscale x 1 x i8> @vnmsub_vx_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i8> %va, %splat
+  %y = sub <vscale x 1 x i8> %vb, %x
+  ret <vscale x 1 x i8> %y
+}
+
+define <vscale x 2 x i8> @vnmsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i8> %va, %vc
+  %y = sub <vscale x 2 x i8> %vb, %x
+  ret <vscale x 2 x i8> %y
+}
+
+define <vscale x 2 x i8> @vnmsub_vx_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i8> %vb, %splat
+  %y = sub <vscale x 2 x i8> %va, %x
+  ret <vscale x 2 x i8> %y
+}
+
+define <vscale x 4 x i8> @vnmsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i8> %vb, %va
+  %y = sub <vscale x 4 x i8> %vc, %x
+  ret <vscale x 4 x i8> %y
+}
+
+define <vscale x 4 x i8> @vnmsub_vx_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i8> %va, %splat
+  %y = sub <vscale x 4 x i8> %vb, %x
+  ret <vscale x 4 x i8> %y
+}
+
+define <vscale x 8 x i8> @vnmsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i8> %vb, %vc
+  %y = sub <vscale x 8 x i8> %va, %x
+  ret <vscale x 8 x i8> %y
+}
+
+define <vscale x 8 x i8> @vnmsub_vx_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i8> %vb, %splat
+  %y = sub <vscale x 8 x i8> %va, %x
+  ret <vscale x 8 x i8> %y
+}
+
+define <vscale x 16 x i8> @vnmsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i8> %vc, %va
+  %y = sub <vscale x 16 x i8> %vb, %x
+  ret <vscale x 16 x i8> %y
+}
+
+define <vscale x 16 x i8> @vnmsub_vx_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i8> %va, %splat
+  %y = sub <vscale x 16 x i8> %vb, %x
+  ret <vscale x 16 x i8> %y
+}
+
+define <vscale x 32 x i8> @vnmsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 32 x i8> %vc, %vb
+  %y = sub <vscale x 32 x i8> %va, %x
+  ret <vscale x 32 x i8> %y
+}
+
+define <vscale x 32 x i8> @vnmsub_vx_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %x = mul <vscale x 32 x i8> %vb, %splat
+  %y = sub <vscale x 32 x i8> %va, %x
+  ret <vscale x 32 x i8> %y
+}
+
+define <vscale x 64 x i8> @vnmsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i8> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 64 x i8> %vc, %vb
+  %y = sub <vscale x 64 x i8> %va, %x
+  ret <vscale x 64 x i8> %y
+}
+
+define <vscale x 64 x i8> @vnmsub_vx_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, i8 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %c, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %x = mul <vscale x 64 x i8> %vb, %splat
+  %y = sub <vscale x 64 x i8> %va, %x
+  ret <vscale x 64 x i8> %y
+}
+
+define <vscale x 1 x i16> @vnmsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i16> %va, %vb
+  %y = sub <vscale x 1 x i16> %vc, %x
+  ret <vscale x 1 x i16> %y
+}
+
+define <vscale x 1 x i16> @vnmsub_vx_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i16> %va, %splat
+  %y = sub <vscale x 1 x i16> %vb, %x
+  ret <vscale x 1 x i16> %y
+}
+
+define <vscale x 2 x i16> @vnmsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i16> %va, %vc
+  %y = sub <vscale x 2 x i16> %vb, %x
+  ret <vscale x 2 x i16> %y
+}
+
+define <vscale x 2 x i16> @vnmsub_vx_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i16> %vb, %splat
+  %y = sub <vscale x 2 x i16> %va, %x
+  ret <vscale x 2 x i16> %y
+}
+
+define <vscale x 4 x i16> @vnmsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i16> %vb, %va
+  %y = sub <vscale x 4 x i16> %vc, %x
+  ret <vscale x 4 x i16> %y
+}
+
+define <vscale x 4 x i16> @vnmsub_vx_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i16> %va, %splat
+  %y = sub <vscale x 4 x i16> %vb, %x
+  ret <vscale x 4 x i16> %y
+}
+
+define <vscale x 8 x i16> @vnmsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i16> %vb, %vc
+  %y = sub <vscale x 8 x i16> %va, %x
+  ret <vscale x 8 x i16> %y
+}
+
+define <vscale x 8 x i16> @vnmsub_vx_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i16> %vb, %splat
+  %y = sub <vscale x 8 x i16> %va, %x
+  ret <vscale x 8 x i16> %y
+}
+
+define <vscale x 16 x i16> @vnmsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i16> %vc, %va
+  %y = sub <vscale x 16 x i16> %vb, %x
+  ret <vscale x 16 x i16> %y
+}
+
+define <vscale x 16 x i16> @vnmsub_vx_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i16> %va, %splat
+  %y = sub <vscale x 16 x i16> %vb, %x
+  ret <vscale x 16 x i16> %y
+}
+
+define <vscale x 32 x i16> @vnmsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i16> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 32 x i16> %vc, %vb
+  %y = sub <vscale x 32 x i16> %va, %x
+  ret <vscale x 32 x i16> %y
+}
+
+define <vscale x 32 x i16> @vnmsub_vx_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, i16 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %c, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %x = mul <vscale x 32 x i16> %vb, %splat
+  %y = sub <vscale x 32 x i16> %va, %x
+  ret <vscale x 32 x i16> %y
+}
+
+define <vscale x 1 x i32> @vnmsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i32> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i32> %va, %vb
+  %y = sub <vscale x 1 x i32> %vc, %x
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnmsub_vx_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i32> %va, %splat
+  %y = sub <vscale x 1 x i32> %vb, %x
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnmsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i32> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v10, v9
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i32> %va, %vc
+  %y = sub <vscale x 2 x i32> %vb, %x
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnmsub_vx_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i32> %vb, %splat
+  %y = sub <vscale x 2 x i32> %va, %x
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnmsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i32> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v10, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i32> %vb, %va
+  %y = sub <vscale x 4 x i32> %vc, %x
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnmsub_vx_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i32> %va, %splat
+  %y = sub <vscale x 4 x i32> %vb, %x
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnmsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v16, v12
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i32> %vb, %vc
+  %y = sub <vscale x 8 x i32> %va, %x
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnmsub_vx_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i32> %vb, %splat
+  %y = sub <vscale x 8 x i32> %va, %x
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 16 x i32> @vnmsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i32> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v24, v16
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 16 x i32> %vc, %va
+  %y = sub <vscale x 16 x i32> %vb, %x
+  ret <vscale x 16 x i32> %y
+}
+
+define <vscale x 16 x i32> @vnmsub_vx_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, i32 %c) {
+; CHECK-LABEL: vnmsub_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vnmsub.vx v8, a0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %c, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %x = mul <vscale x 16 x i32> %va, %splat
+  %y = sub <vscale x 16 x i32> %vb, %x
+  ret <vscale x 16 x i32> %y
+}
+
+define <vscale x 1 x i64> @vnmsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i64> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 1 x i64> %va, %vb
+  %y = sub <vscale x 1 x i64> %vc, %x
+  ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 1 x i64> @vnmsub_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) {
+; RV32-LABEL: vnmsub_vx_nxv1i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v25, (a0), zero
+; RV32-NEXT:    vnmsub.vv v8, v25, v9
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnmsub_vx_nxv1i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; RV64-NEXT:    vnmsub.vx v8, a0, v9
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %x = mul <vscale x 1 x i64> %va, %splat
+  %y = sub <vscale x 1 x i64> %vb, %x
+  ret <vscale x 1 x i64> %y
+}
+
+define <vscale x 2 x i64> @vnmsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i64> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v12, v10
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 2 x i64> %va, %vc
+  %y = sub <vscale x 2 x i64> %vb, %x
+  ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 2 x i64> @vnmsub_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) {
+; RV32-LABEL: vnmsub_vx_nxv2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v26, (a0), zero
+; RV32-NEXT:    vnmsac.vv v8, v10, v26
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnmsub_vx_nxv2i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; RV64-NEXT:    vnmsac.vx v8, a0, v10
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %x = mul <vscale x 2 x i64> %vb, %splat
+  %y = sub <vscale x 2 x i64> %va, %x
+  ret <vscale x 2 x i64> %y
+}
+
+define <vscale x 4 x i64> @vnmsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i64> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vnmsub.vv v8, v12, v16
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 4 x i64> %vb, %va
+  %y = sub <vscale x 4 x i64> %vc, %x
+  ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 4 x i64> @vnmsub_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) {
+; RV32-LABEL: vnmsub_vx_nxv4i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v28, (a0), zero
+; RV32-NEXT:    vnmsub.vv v8, v28, v12
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnmsub_vx_nxv4i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; RV64-NEXT:    vnmsub.vx v8, a0, v12
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %x = mul <vscale x 4 x i64> %va, %splat
+  %y = sub <vscale x 4 x i64> %vb, %x
+  ret <vscale x 4 x i64> %y
+}
+
+define <vscale x 8 x i64> @vnmsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i64> %vc) {
+; CHECK-LABEL: vnmsub_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vl8re64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vnmsac.vv v8, v16, v24
+; CHECK-NEXT:    ret
+  %x = mul <vscale x 8 x i64> %vb, %vc
+  %y = sub <vscale x 8 x i64> %va, %x
+  ret <vscale x 8 x i64> %y
+}
+
+define <vscale x 8 x i64> @vnmsub_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) {
+; RV32-LABEL: vnmsub_vx_nxv8i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    sw a1, 12(sp)
+; RV32-NEXT:    sw a0, 8(sp)
+; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vlse64.v v24, (a0), zero
+; RV32-NEXT:    vnmsac.vv v8, v16, v24
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vnmsub_vx_nxv8i64:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT:    vnmsac.vx v8, a0, v16
+; RV64-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %c, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %x = mul <vscale x 8 x i64> %vb, %splat
+  %y = sub <vscale x 8 x i64> %va, %x
+  ret <vscale x 8 x i64> %y
+}

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v12, v28, 15
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vsrl.vi v24, v16, 15
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {

 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsrl.vi v12, v28, 31
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsrl.vi v24, v16, 31
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vmulh.vv v25, v8, v25
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v26, v25, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 

 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v26, (a0), zero
 ; CHECK-NEXT:    vmulh.vv v26, v8, v26
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v28, v26, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 

 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v28, (a0), zero
 ; CHECK-NEXT:    vmulh.vv v28, v8, v28
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v12, v28, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 

 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v16, (a0), zero
 ; CHECK-NEXT:    vmulh.vv v16, v8, v16
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v24, v16, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v12, v28, 15
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vsrl.vi v24, v16, 15
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {

 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 31
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 31
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v26, v25, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v28, v26, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v12, v28, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 63
 ; CHECK-NEXT:    vsrl.vx v24, v16, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll

 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {

 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {

 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {

 ; CHECK-NEXT:    sw a0, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vmulhu.vv v25, v8, v25
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v25, v25, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 

 ; CHECK-NEXT:    sw a0, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v26, (a0), zero
 ; CHECK-NEXT:    vmulhu.vv v26, v8, v26
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v26, v26, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 

 ; CHECK-NEXT:    sw a0, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v28, (a0), zero
 ; CHECK-NEXT:    vmulhu.vv v28, v8, v28
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v28, v28, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 

 ; CHECK-NEXT:    sw a0, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v16, (a0), zero
 ; CHECK-NEXT:    vmulhu.vv v16, v8, v16
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v16, v16, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {

 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {

 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 5
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 13
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 29
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v25, v25, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v25, v25, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v25
+; CHECK-NEXT:    vnmsac.vx v8, a0, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v26, v26, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v26, v26, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v26
+; CHECK-NEXT:    vnmsac.vx v8, a0, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v28, v28, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v28, v28, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v28
+; CHECK-NEXT:    vnmsac.vx v8, a0, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {

 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v16, v16, a0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vmul.vx v16, v16, a0
-; CHECK-NEXT:    vsub.vv v8, v8, v16
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }