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[AArch64][SVE] Add unpredicated vector BIC ISD node
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Authored by bsmith on May 4 2021, 5:50 AM.

Details

Summary

Addition of this node allows us to better utilize the different forms of
the SVE BIC instructions, including using the alias to an AND (immediate).

Depends on D101828

Diff Detail

Event Timeline

bsmith created this revision.May 4 2021, 5:50 AM
bsmith requested review of this revision.May 4 2021, 5:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 4 2021, 5:50 AM
bsmith updated this revision to Diff 342986.May 5 2021, 3:59 AM
  • Fix clang format issues
Matt added a subscriber: Matt.May 5 2021, 4:59 AM
paulwalker-arm added inline comments.May 11 2021, 7:44 AM
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
3228

This looks to be the only difference to SelectSVELogicalImm so I wondered if it's better to extend SelectSVELogicalImm with an Invert parameter?

bsmith updated this revision to Diff 344832.May 12 2021, 8:15 AM
  • Merge SelectSVELogicalImmNot with SelectSVELogicalImm
paulwalker-arm accepted this revision.May 13 2021, 3:14 AM
This revision is now accepted and ready to land.May 13 2021, 3:14 AM
This revision was landed with ongoing or failed builds.May 14 2021, 8:12 AM
This revision was automatically updated to reflect the committed changes.