[RISCV] Add scalable offset under very large stack size.

[HsiangKai]

Summary

If the stack size is larger than 12 bits, we have to use a scratch
register to store the stack size. Before we introduce the scalable stack
offset, we could simplify

%0 = ADDI %stack.0, 0

>

%scratch = ... # sequence of instructions to move the offset into %scratch
%0 = ADD %fp, %scratch

However, if the offset contains scalable part, we need to consider it.

%0 = ADDI %stack.0, 0

>

%scratch = ... # sequence of instructions to move the offset into %scratch
%scratch = ADD %fp, %scratch
%scalable_offset = ... # sequence of instructions for vscaled-offset.
%0 = ADD/SUB %scratch, %scalable_offset

[frasercrmck]

I think it makes sense to me, but it would be good to pre-commit this test to better see the fix.

[HsiangKai]

In D100035#2673995, @frasercrmck wrote:

I think it makes sense to me, but it would be good to pre-commit this test to better see the fix.

D100084

[rogfer01]

LGTM. Thanks @HsiangKai.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MachineBasicBlock &MBB = *MI.getParent();
   bool FrameRegIsKill = false;
 
   if (!isInt<12>(Offset.getFixed())) {
     // The offset won't fit in an immediate, so use a scratch register instead
     // Modify Offset and FrameReg appropriately
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
-    if (MI.getOpcode() == RISCV::ADDI) {
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
       BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
         .addReg(FrameReg)
         .addReg(ScratchReg, RegState::Kill);
       MI.eraseFromParent();
       return;
     }
     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
         .addReg(FrameReg)
if (ScalableValue < 0) {
       Opc = RISCV::SUB;
     }
 
     // 1. Get vlenb && multiply vlen with number of vector register.
     Register FactorRegister =
         TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
 
     // 2. Calculate address: FrameReg + result of multiply
+    if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
+      BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg())
+          .addReg(FrameReg, getKillRegState(FrameRegIsKill))
+          .addReg(FactorRegister, RegState::Kill);
+      MI.eraseFromParent();
+      return;
+    }
     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(Opc), VL)
         .addReg(FrameReg, getKillRegState(FrameRegIsKill))
         .addReg(FactorRegister, RegState::Kill);
 
     if (isRVV && Offset.getFixed()) {
       // Scalable load/store has no immediate argument. We need to add the
       // fixed part into the load/store base address.

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

bb.0:
     ; CHECK: $x2 = frame-setup ADDI $x2, -240
     ; CHECK: $x12 = PseudoReadVLENB
     ; CHECK: $x2 = SUB $x2, killed $x12
     ; CHECK: dead renamable $x11 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype
     ; CHECK: renamable $v25 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
     ; CHECK: $x10 = LUI 1048575
     ; CHECK: $x10 = ADDIW killed $x10, 1824
     ; CHECK: $x10 = ADD $x8, killed $x10
+    ; CHECK: $x11 = PseudoReadVLENB
+    ; CHECK: $x10 = SUB killed $x10, killed $x11
     ; CHECK: VS1R_V killed renamable $v25, killed renamable $x10
     ; CHECK: $x10 = PseudoReadVLENB
     ; CHECK: $x2 = ADD $x2, killed $x10
     ; CHECK: $x2 = frame-destroy ADDI $x2, 240
     ; CHECK: $x8 = LD $x2, 2016 :: (load 8 from %stack.4)
     ; CHECK: $x1 = LD $x2, 2024 :: (load 8 from %stack.3)
     ; CHECK: $x2 = frame-destroy ADDI $x2, 2032
     ; CHECK: PseudoRET
     %1:gpr = COPY $x11
     %0:gpr = COPY $x10
     %2:vr = PseudoVLE64_V_M1 %0, %1, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
     %3:gpr = ADDI %stack.2, 0
     VS1R_V killed %2:vr, %3:gpr
     PseudoRET
 
 ...