[ARM] support symbolic expression as immediate in memory instructions

[jcai19]

Summary

Currently the ARM backend only accpets constant expressions as the
immediate operand in load and store instructions. This allows the
result of symbolic expressions to be used in memory instructions. For
example,

0:
.space 2048
strb r2, [r0, #(.-0b)]

would be assembled into the following instructions.

strb r2, [r0, #2048]

This only adds support to ldr, ldrb, str, and strb in arm mode to
address the build failure of Linux kernel for now, but should facilitate
adding support to similar instructions in the future if the need arises.

Link:
https://github.com/ClangBuiltLinux/linux/issues/1329

[DavidSpickett]

I'm not familiar with how fixups work so someone else should check that part. What you do with them looks fine but I don't know if those names are llvm internal or we have to match some published spec elsewhere.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

3013

Here we check that Memory.OffsetImm is non zero (non null?) and we don't after. Does that check get done later anyway?

Ditto for the other functions that look like this one.

5949

Nit: remove the newline

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

5

Unindent this or indent the .space line below.

Also could you add a comment describing the purpose? To make it clear this is looking at a specific kind of immediates.

[peter.smith]

The fixup code looks reasonable to me as it is mostly reusing the same logic as the pc-relative fixup. The names are internal to LLVM so there isn't any particular standard. I think this fixup would correspond to the relocation R_ARM_ABS12 https://github.com/ARM-software/abi-aa/blob/master/aaelf32/aaelf32.rst#relocation-codes so it may be worth using fixup_arm_ldst_abs_12 but that is only a suggestion. I wouldn't expect the assembler to use the relocation as the range is so short that any attempt to use it would likely result in an out of range error.

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

12

Could we add some test cases for negative and zero offsets. It looks like this is handled in the fixup code but it would be good to have some tests to make sure it isn't broken in the future.

[nickdesaulniers]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

2950

else if (const auto *CE = ...)

(Prefer auto when using dyn_cast; the type info is otherwise mostly redundant).

3003

else if (const auto *CE =...

3013

other functions have

if (!Memory.OffsetImm)
     Inst.addOperand(MCOperand::createImm(0));

if addExpr doesn't handle their more specific cases.

3061

const auto *CE =...

3090–3091

const auto *CE = ...

3140–3141

const auto *CE =

3233–3234

const auto *CE

3245

const auto *CE

3262–3263

const auto *CE

5938–5951

const auto *CE

5947–5952

The tails of these two branches match, other than the second operand. Can you declare a local const MCExpr *, simply assign to it from both branches, then sink the call to push_back to be executed after both branches merge?

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

983–984

can you sink the subexpression MO.getExpr() into the argument list for MCFixup::create here, so that it matches below?

983–1018

seeing:

if !x:

foo()

else:

bar()

is a code smell. We should prefer:

if x:

bar()

else:

foo()

There seems like a fair amount of duplication between sub branches of these nested conditionals, at least handling an operand that is an expression. I wonder if we could reduce the duplication somehow?

1003–1004

What if we're in Thumb2 mode? I think we need a different fixup kind, like L991-996.

Do we need to increment MCNumCPRelocations?

[jcai19]

Address comments so far.

[jcai19]

In D98916#2637305, @peter.smith wrote:

The fixup code looks reasonable to me as it is mostly reusing the same logic as the pc-relative fixup. The names are internal to LLVM so there isn't any particular standard. I think this fixup would correspond to the relocation R_ARM_ABS12 https://github.com/ARM-software/abi-aa/blob/master/aaelf32/aaelf32.rst#relocation-codes so it may be worth using fixup_arm_ldst_abs_12 but that is only a suggestion. I wouldn't expect the assembler to use the relocation as the range is so short that any attempt to use it would likely result in an out of range error.

Thanks for the suggestion, I've updated the name.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

3013

Yes addExpr would take care of the non-null case. For the cases I could not call addExpr directly, I've handled the case separately.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

1003–1004

What if we're in Thumb2 mode? I think we need a different fixup kind, like L991-996.

This patch is only intended for some memory instructions in arm mode. I will look into the thumb mode but do we care about it at this moment?

Do we need to increment MCNumCPRelocations?

The expressions of interest here are really those would produce immediate values, so I'm not sure if I should count them as relocation. WDYT?

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

12

Ah yes. I did test negative numbers locally but forgot to add it here, thanks for the reminder.

[nickdesaulniers]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

983–984

I wonder why we aren't consistent about the use of getEncodingValue when assigning to Reg? Are these actually different values? (I recognize your change doesn't introduce this, just curious).

983–1018

(I'm tempted to go and pre-commit the previous change as that code smell is pervasive throughout this file).

Looks better, now I see:

if MO.isReg():
  foo()
else:
  if MO.isExpr():
    bar()
  else:
    baz()

should be

if MO.isReg():
  foo()
else if MO.isExpr():
  bar()
else: # MO.isImm
  baz()

Then it's obvious that the MCOperand is an immediate, and removes one level of unnecessary indentation.

1003–1004

I will look into the thumb mode but do we care about it at this moment?

We don't have a pressing need for THUMB2 support, but I worry that someone using clang may find the wrong fixup(relocation?) applied in the event they are assembling a THUMB2 source with a symbolic operand, due to this change. Perhaps a check for isThumb2(STI) then assert if thumb, or skip generating the fixup? (Or maybe another reviewer has thoughts?)

The expressions of interest here are really those would produce immediate values, so I'm not sure if I should count them as relocation.

Looks like it's just a stat (so probably doesn't really matter too much):

STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");

Since it's an immediate, it's encoded in the instruction; not a constant pool. But seeing how it's incremented elsewhere throughout this TU, it looks like everytime we have an Expr MCOperand, we bump it. So I think you should here, too. Maybe other reviewers can help clarify?

Seeing how similar the users of MCNumCPRelocations makes me think there's a whole lot of other instruction formats with this issue that you're fixing. Though I think it's fine that we start with ldr/str.

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

26

if you add .thumb you can repeat some tests for THUMB (I would then add .arm before the initial group of instructions to clearly delineate between ARM mode and THUMB. getAddrModeImm12OpValue has pre-existing checks for THUMB, so I suspect we should be able to add coverage for your additions with THUMB.

[MaskRay]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

985

Nit: https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements If you use braces for else, use braces for then as well.

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

2

You can omit <

[jcai19]

Address comments.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

983–984

Yeah I had the same question, so I changed the original code a little bit to make it more obvious for others to notice. I wonder if this is a typo?

1003–1004

We don't have a pressing need for THUMB2 support, but I worry that someone using clang may find the wrong fixup(relocation?) applied in the event they are assembling a THUMB2 source with a symbolic operand, due to this change. Perhaps a check for isThumb2(STI) then assert if thumb, or skip generating the fixup? (Or maybe another reviewer has thoughts?)

I did some more digging and the thumb mode of these instructions are actually handled by different functions, so right now comping them in thumb mode (either with thumbv7 in the target triple or .thumb) will crash the compiler with assertion failures. I have been looking into supporting thumb mode a little bit, and found extra complexity: while the instructions supported by this patch (ldr/ldrb, str/strb) have one encoding in arm mode, they have multiple encodings in thumb mode, depending on the value of the immediate operand, or if it is (un)signed. Some of these encodings are 16 bits while the others 32. IAS associate each encoding with a different opcode and tries to decide the opcode before the fixups are resolved, so it is difficult to decide the precise encoding when expressions are present. One solution I could think of right now is to always match such instructions to the shortest encoding so they don't unnecessarily generate 32-bit instructions when 16-bit version can be used, at the cost of not being able to support expressions with a result outside of the range. WDYT? Also I think it may be easier to implement the thumb mode support in a different CL so we don't have to deal with two complications at the same time.

PS: I re-examined my CL for supporting expressions in b.w instructions (https://reviews.llvm.org/D97568). b.w has two encoding in thumb mode but both are 32-bit instructions and they do not look that differently, so IAS somehow has only one opcode for both of them (verified with --debug-only=asm-matcher). So b.w probably don't have this issue.

Looks like it's just a stat (so probably doesn't really matter too much):

STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");

Since it's an immediate, it's encoded in the instruction; not a constant pool. But seeing how it's incremented elsewhere throughout this TU, it looks like everytime we have an Expr MCOperand, we bump it. So I think you should here, too. Maybe other reviewers can help clarify?

+1.

Seeing how similar the users of MCNumCPRelocations makes me think there's a whole lot of other instruction formats with this issue that you're fixing. Though I think it's fine that we start with ldr/str.

Yes there are other memory operations with similar issues but hopefully once we have this checked in it would be much easier to fix those.

[nickdesaulniers]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1099–1117

Something still really bugs me about these is* functions; perhaps I'm still hung up on D97568.

I understand that we can't validate immediates when expressions are used until post fixup; doing such validation of operands before fixups are performs seems like a major phase ordering issue in LLVM's assemblers.

So for a lot of these is* functions, if we don't have an immediate operand, we can't tell if it fits whatever constraints we're checking. This change makes these functions return true as in "maybe." Rather than return a type that's a tri-state for "definitely yes," "definitely no," or "can't tell until post fixups." Then other is* functions don't have that added logic, like isFPImm below, isLEOffset and isSignedOffset above, etc. I'm very concerned about isARMBranchTarget/isThumbBranchTarget.

I almost wonder if fixing the phase ordering in LLVM will fix this more generally for all instructions/operands or even additional ISAs. Perhaps let's hold onto this change, but see how feasible it would be to validate instructions post fixups in LLVM? Then we can keep these is functions more strict about only accepting immediate operands.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

1003–1004

think it may be easier to implement the thumb mode support in a different CL so we don't have to deal with two complications at the same time.

Got it, thanks for the due diligence. Sounds good. Sounds like "relaxation" might be needed to efficiently select the encoding when expressions are used.

[jcai19]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1099–1117

I almost wonder if fixing the phase ordering in LLVM will fix this more generally for all instructions/operands or even additional ISAs. Perhaps let's hold onto this change, but see how feasible it would be to validate instructions post fixups in LLVM? Then we can keep these is functions more strict about only accepting immediate operands.

I realized that resolving some of these fixups also depends on the chose encoding of the instructions between the symbols, i.e. whether it is 16 or 32 bits. So it may be difficult to switch the order of the two phases. Maybe we can add different an option to allow users to decide if size is a major concern, which would allow us to choose a better encoding. It's suboptimal but I suspect such code is not dominant in most code bases, so maybe it's acceptable. WDYT?

[nickdesaulniers]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1099–1117

It's not the size of the chosen instruction (relaxation) I'm concerned with. It's the lack of symmetry between considering whether an operand is a MCConstantExpr or not between these ARMAsmParser::is* methods.

So the relevant call chains look like:

AsmParser::Run ->
  AsmParser::parseStatement ->
    ARMAsmParser::MatchAndEmitInstruction ->
      ARMAsmParser::validateInstruction ->
        is*
  MCStreamer::Finish ->
    MCObjectStreamer::finishImpl ->
      MCAssembler::Finish -> 
        MCAssembler::layout ->
          ARMAsmBackend::applyFixup ->
            ARMAsmBackend::adjustFixupValue

Where the is* methods of ARMAsmParser assume they have immediates that can validated eagerly, which for expression operands we can't validate until after ARMAsmBackend::adjustFixupValue. ARMAsmBackend::adjustFixupValue does some checking/diagnostic emission, but I wonder if we can rerun ARMAsmParser::validateInstruction immediately upon applying a fixup?

I wonder whether the is* methods should have a "strict mode" check (boolean parameter, perhaps); in the case of !MCConstantExpr operands, we check once less strict (don't consider that the operand is not a MCConstantExpr a failure), then after fixups immediately call validateInstruction again but do consider !MCConstantExpr a failure. I don't know if it's possible to get the MCInst from the MCFixup so that ARMAsmBackend::adjustFixupValue could call ARMAsmParser::validateInstruction. Seems the MCAsmBackends and the backend parsers don't have references to one another....

I'm very concerned about isARMBranchTarget/isThumbBranchTarget.

Nevermind that comment, they optimistically return true in the case of !MCConstantExpr.

If not, I do like how ARMAsmParser::isAdrLabel has comments like

// If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup.

I think adding those elsewhere in this CL would go a long way in clarifying the intent of these is* methods, maybe without strictly copying the part about "a label."

[jcai19]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1099–1117

I see. Thanks for the clarification. Will investigate.

[jcai19]

Only accept MCExpr in the affected instructions.

[jcai19]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1099–1117

Where the is* methods of ARMAsmParser assume they have immediates that can validated eagerly, which for expression operands we can't validate until after ARMAsmBackend::adjustFixupValue. ARMAsmBackend::adjustFixupValue does some checking/diagnostic emission, but I wonder if we can rerun ARMAsmParser::validateInstruction immediately upon applying a fixup?

I wonder whether the is* methods should have a "strict mode" check (boolean parameter, perhaps); in the case of !MCConstantExpr operands, we check once less strict (don't consider that the operand is not a MCConstantExpr a failure), then after fixups immediately call validateInstruction again but do consider !MCConstantExpr a failure. I don't know if it's possible to get the MCInst from the MCFixup so that ARMAsmBackend::adjustFixupValue could call ARMAsmParser::validateInstruction. Seems the MCAsmBackends and the backend parsers don't have references to one another....

I looked into the code, but couldn't find a way to convert the MCExpr in a MCFixup to a MCInst. It might be possible to call ARMAsmParser::validateInstruction after MCFixups are resolved, by adding the arguments (MCInst &Inst, const OperandVector &Ops) needed as additional members when creating MCFixups, but that would require significantly more changes to the code and raise memory usage. Also having two copies of code seemed to not be unique to ARM backend, for example, we have two copies of code to decide maximum NOP length in emitNop of X86MCInstLower.cpp and X86AsmBackend::getMaximumNopSize in . I wonder if there is any rationale behind the redundancy?

If not, I do like how ARMAsmParser::isAdrLabel has comments like

// If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup.

I think adding those elsewhere in this CL would go a long way in clarifying the intent of these is* methods, maybe without strictly copying the part about "a label."

I limited this patch to only accept MCExpr in the affected instructions, and added comments.

[nickdesaulniers]

In D98916#2669915, @jcai19 wrote:

Only accept MCExpr in the affected instructions.

Yeah, I think the conservative approach is the way to go here; that way your only functional change is the one you add tests for (ie. isMemImm12Offset). Another thing we could do to be more concise is simply return false if (!isa<MCConstExpr>(Memory.OffsetImm)) for the majority of cases, but return true for such a case in isMemImm12Offset. That would avoid the added dyn_casts and resulting indentation. But in effect it's the same as what you have, so it doesn't matter to me.

I'm ok with this, and thanks for taking the time to work on it. It would be good to collect another LGTM from another reviewer before submitting.

[jcai19]

I'm ok with this, and thanks for taking the time to work on it. It would be good to collect another LGTM from another reviewer before submitting.

Thanks for reviewing the patches! Will definitely wait for additional inputs before I submit.

[peter.smith]

I have a one major concern, and a number of minor nits that could easily be addressed prior to commit if necessary.

The major concern is that if the intent is to just permit expressions for Arm state LDR instructions (addition of one fixup) then a lot of code in the AsmParser looks like it is permitting expressions for Thumb and Thumb2 LDR instructions that wouldn't use the one new fixup. Can you double check the predicates to make sure that they apply to the instructions you want to permit expressions on? It is possible I've got something wrong though. If I'm right then where we would have had errors had someone use an expression then we may get an internal error or crash as the backend won't be able to handle the expression. My suggestion would be to take out from ARMAsmParser all the code permitting exceptions except for the ARM instructions that support the fixup. Adding support for expressions to all the ARM and Thumb instructions is possible but that would probably be better done over several patches. If I'm wrong please ignore me and sorry for the noise.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1110–1113

This predicate is only called for the ThumbMemPC class (see ARMInstrThumb.td) if the intent is to allow expressions only in certain Arm load and store instructions then I think this may be letting through expressions where the backend won't support them. It is highly possible that there are no tests that fail because there may be no expect fail tests written.

1502–1507

I think this is Thumb2 t2ldr_pcrel_imm12_asmoperand in ARMInstrThumb2.td

3007

Looks like a few changes are just formatting (clang-format?) While it doesn't bother me personally, I have seen some people prefer that pure formatting changes are committed separately with a [NFC] tag as it minimises the diff when trying to bisect a problem. Maybe worth committing these bits first in a separate [NFC]

3058–3072

I think this comment makes more sense when it immediately precedes CE->getValue() / 4; on line 3062

3137–3143

Same as before, can the comment be moved to immediately before line 3141?

3234

To be consistent I suppose we ought to add the "// The lower two bits are always zero and as such are not encoded."

3263

Another opportunity for // The lower two bits are always zero and as such are not encoded.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

991

One thing that could be confusing is that there is only an Arm fixup here, whereas in the else if (MO.isExpr()) { ... } there are both Arm and Thumb fixups.

If it is only possible to be here for an Arm Instruction, my apologies I haven't had time to double check the reference manual to see if Thumb has more restricted addressing modes than Arm, can we put a comment here? Possibly an assert that the STI is Arm state?

[jcai19]

Address comments.

[jcai19]

In D98916#2673445, @peter.smith wrote:

I have a one major concern, and a number of minor nits that could easily be addressed prior to commit if necessary.

The major concern is that if the intent is to just permit expressions for Arm state LDR instructions (addition of one fixup) then a lot of code in the AsmParser looks like it is permitting expressions for Thumb and Thumb2 LDR instructions that wouldn't use the one new fixup. Can you double check the predicates to make sure that they apply to the instructions you want to permit expressions on? It is possible I've got something wrong though. If I'm right then where we would have had errors had someone use an expression then we may get an internal error or crash as the backend won't be able to handle the expression. My suggestion would be to take out from ARMAsmParser all the code permitting exceptions except for the ARM instructions that support the fixup. Adding support for expressions to all the ARM and Thumb instructions is possible but that would probably be better done over several patches. If I'm wrong please ignore me and sorry for the noise.

So the current patch only accepts symbolic expressions in isMemImm12Offset, so only instructions that call this function would be able to accept symbolic expressions, namely, ldr, ldrb, str and strb in ARM mode. All the other is* function would return false when symbolic expressions are spotted, including the thumb mode of the support instructions.

$ cat foo.s 
.syntax unified
.thumb
0:
.space 2048
1:
.space 20
2:
str r0, [r1, #(2b-1b)]

llvm-mc -triple=armv7a -filetype=obj foo.s -o ias.o
foo.s:8:1: error: invalid instruction, any one of the following would fix this:
str r0, [r1, #(2b-1b)]
^
foo.s:8:9: note: invalid operand for instruction
str r0, [r1, #(2b-1b)]
        ^
foo.s:8:1: note: instruction requires: arm-mode
str r0, [r1, #(2b-1b)]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1110–1113

This change here should not alter the semantics, i.e. only MCConstantExprs get through. Other types of MCExprs would trigger the following return false case.

1502–1507

Same as above.

[jcai19]

Fix a typo.

[jcai19]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

3007

This was actually part of the automatic linting done by arc diff. It seems I I can't use it without accepting the linting?

[peter.smith]

Thanks for the update LGTM. It sounds like you have all the cases covered. Apologies for the noise.

[jcai19]

In D98916#2678792, @peter.smith wrote:

Thanks for the update LGTM. It sounds like you have all the cases covered. Apologies for the noise.

No problem! Thank you for reviewing the patch!

[jcai19]

This broke the ppc64le-sanitizer builderr: https://lab.llvm.org/buildbot/#/builders/19/builds/3565. Will fix it.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

struct ImmOp {
     const MCExpr *Val;
   };
 
   /// Combined record for all forms of ARM address expressions.
   struct MemoryOp {
     unsigned BaseRegNum;
     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
     // was specified.
-    const MCConstantExpr *OffsetImm;  // Offset immediate value
+    const MCExpr *OffsetImm;  // Offset immediate value
     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
     unsigned ShiftImm;        // shift for OffsetReg.
     unsigned Alignment;       // 0 = no alignment specified
     // n = alignment in bytes (2, 4, 8, 16, or 32)
     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
   };
 
bool isLEOffset() const {
     }
     return false;
   }
 
   // checks whether this operand is a memory operand computed as an offset
   // applied to PC. the offset may have 8 bits of magnitude and is represented
   // with two bits of shift. textually it may be either [pc, #imm], #imm or
   // relocable expression...
   bool isThumbMemPC() const {
     int64_t Val = 0;
     if (isImm()) {
       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
       if (!CE) return false;
       Val = CE->getValue();
     }
     else if (isGPRMem()) {
       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
       if(Memory.BaseRegNum != ARM::PC) return false;
-      Val = Memory.OffsetImm->getValue();
+      if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+        Val = CE->getValue();
+      else
+        return false;
     }
     else return false;
     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
   }
 
   bool isFPImm() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
     return Val != -1;
   }
public:
   bool isMemPCRelImm12() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base register must be PC.
     if (Memory.BaseRegNum != ARM::PC)
       return false;
     // Immediate offset in range [-4095, 4095].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val > -4096 && Val < 4096) ||
              (Val == std::numeric_limits<int32_t>::min());
     }
+    return false;
+  }
 
   bool isAlignedMemory() const {
     return isMemNoOffset(true);
   }
 
   bool isAlignedMemoryNone() const {
     return isMemNoOffset(false, 0);
   }
public:
   }
 
   bool isAddrMode2() const {
     if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return true;
     // Immediate offset in range [-4095, 4095].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val > -4096 && Val < 4096;
     }
+    return false;
+  }
 
   bool isAM2OffsetImm() const {
     if (!isImm()) return false;
     // Immediate offset in range [-4095, 4095].
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
     int64_t Val = CE->getValue();
     return (Val == std::numeric_limits<int32_t>::min()) ||
            (Val > -4096 && Val < 4096);
   }
 
   bool isAddrMode3() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
     if (!isGPRMem() || Memory.Alignment != 0) return false;
     // No shifts are legal for AM3.
     if (Memory.ShiftType != ARM_AM::no_shift) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return true;
     // Immediate offset in range [-255, 255].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
-    // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
-    // have to check for this too.
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
+      // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
+      // we have to check for this too.
       return (Val > -256 && Val < 256) ||
              Val == std::numeric_limits<int32_t>::min();
     }
+    return false;
+  }
 
   bool isAM3Offset() const {
     if (isPostIdxReg())
       return true;
     if (!isImm())
       return false;
     // Immediate offset in range [-255, 255].
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
bool isAddrMode5() const {
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
     if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return false;
     // Immediate offset in range [-1020, 1020] and a multiple of 4.
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
              Val == std::numeric_limits<int32_t>::min();
     }
+    return false;
+  }
 
   bool isAddrMode5FP16() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
     if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return false;
     // Immediate offset in range [-510, 510] and a multiple of 2.
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
              Val == std::numeric_limits<int32_t>::min();
     }
+    return false;
+  }
 
   bool isMemTBB() const {
     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
       return false;
     return true;
   }
 
public:
   }
 
   bool isMemThumbRIs4() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 124].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val <= 124 && (Val % 4) == 0;
     }
+    return false;
+  }
 
   bool isMemThumbRIs2() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 62].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val <= 62 && (Val % 2) == 0;
     }
+    return false;
+  }
 
   bool isMemThumbRIs1() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 31].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val <= 31;
     }
+    return false;
+  }
 
   bool isMemThumbSPI() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 1020].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
     }
+    return false;
+  }
 
   bool isMemImm8s4Offset() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset a multiple of 4 in range [-1020, 1020].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       // Special case, #-0 is std::numeric_limits<int32_t>::min().
       return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
              Val == std::numeric_limits<int32_t>::min();
     }
+    return false;
+  }
+
   bool isMemImm7s4Offset() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
         !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
             Memory.BaseRegNum))
       return false;
     // Immediate offset a multiple of 4 in range [-508, 508].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       // Special case, #-0 is INT32_MIN.
       return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
     }
+    return false;
+  }
+
   bool isMemImm0_1020s4Offset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset a multiple of 4 in range [0, 1020].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
     }
+    return false;
+  }
 
   bool isMemImm8Offset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base reg of PC isn't allowed for these encodings.
     if (Memory.BaseRegNum == ARM::PC) return false;
     // Immediate offset in range [-255, 255].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val == std::numeric_limits<int32_t>::min()) ||
              (Val > -256 && Val < 256);
     }
+    return false;
+  }
 
   template<unsigned Bits, unsigned RegClassID>
   bool isMemImm7ShiftedOffset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
         !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
       return false;
 
     // Expect an immediate offset equal to an element of the range
     // [-127, 127], shifted left by Bits.
 
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
 
       // INT32_MIN is a special-case value (indicating the encoding with
       // zero offset and the subtract bit set)
       if (Val == INT32_MIN)
         return true;
 
       unsigned Divisor = 1U << Bits;
 
       // Check that the low bits are zero
       if (Val % Divisor != 0)
         return false;
 
       // Check that the remaining offset is within range.
       Val /= Divisor;
       return (Val >= -127 && Val <= 127);
     }
+    return false;
+  }
 
   template <int shift> bool isMemRegRQOffset() const {
     if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
       return false;
 
     if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
             Memory.BaseRegNum))
       return false;
public:
   template <int shift> bool isMemRegQOffset() const {
     if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
 
     if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
             Memory.BaseRegNum))
       return false;
 
-    if(!Memory.OffsetImm) return true;
+    if (!Memory.OffsetImm)
+      return true;
     static_assert(shift < 56,
                   "Such that we dont shift by a value higher than 62");
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
 
       // The value must be a multiple of (1 << shift)
       if ((Val & ((1U << shift) - 1)) != 0)
         return false;
 
       // And be in the right range, depending on the amount that it is shifted
       // by.  Shift 0, is equal to 7 unsigned bits, the sign bit is set
       // separately.
-    int64_t Range = (1U << (7+shift)) - 1;
+      int64_t Range = (1U << (7 + shift)) - 1;
       return (Val == INT32_MIN) || (Val > -Range && Val < Range);
     }
+    return false;
+  }
 
   bool isMemPosImm8Offset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 255].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return Val >= 0 && Val < 256;
     }
+    return false;
+  }
 
   bool isMemNegImm8Offset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base reg of PC isn't allowed for these encodings.
     if (Memory.BaseRegNum == ARM::PC) return false;
     // Immediate offset in range [-255, -1].
     if (!Memory.OffsetImm) return false;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val == std::numeric_limits<int32_t>::min()) ||
              (Val > -256 && Val < 0);
     }
+    return false;
+  }
 
   bool isMemUImm12Offset() const {
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 4095].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val >= 0 && Val < 4096);
     }
+    return false;
+  }
 
   bool isMemImm12Offset() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
 
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
 
     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [-4095, 4095].
     if (!Memory.OffsetImm) return true;
-    int64_t Val = Memory.OffsetImm->getValue();
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int64_t Val = CE->getValue();
       return (Val > -4096 && Val < 4096) ||
              (Val == std::numeric_limits<int32_t>::min());
     }
+    // If we have an immediate that's not a constant, treat it as a
+    // symbolic expression needing a fixup.
+    return true;
+  }
 
   bool isConstPoolAsmImm() const {
     // Delay processing of Constant Pool Immediate, this will turn into
     // a constant. Match no other operand
     return (isConstantPoolImm());
   }
 
   bool isPostIdxImm8() const {
if (isImm()) {
       }
       const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
       Inst.addOperand(MCOperand::createExpr(SR));
       return;
     }
 
     assert(isGPRMem()  && "Unknown value type!");
     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
-    Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      Inst.addOperand(MCOperand::createImm(CE->getValue()));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
   }
 
   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {

 
   void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
   }
 
   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    int32_t Imm = Memory.OffsetImm->getValue();
-    Inst.addOperand(MCOperand::createImm(Imm));
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      Inst.addOperand(MCOperand::createImm(CE->getValue()));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     assert(isImm() && "Not an immediate!");
 
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup.

   }
 
   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
     addAlignedMemoryOperands(Inst, N);
   }
 
   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
     assert(N == 3 && "Invalid number of operands!");
-    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
     if (!Memory.OffsetRegNum) {
+      if (!Memory.OffsetImm)
+        Inst.addOperand(MCOperand::createImm(0));
+      else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+        int32_t Val = CE->getValue();
         ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
         // Special case for #-0
-      if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
-      if (Val < 0) Val = -Val;
+        if (Val == std::numeric_limits<int32_t>::min())
+          Val = 0;
+        if (Val < 0)
+          Val = -Val;
         Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
+        Inst.addOperand(MCOperand::createImm(Val));
+      } else
+        Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
     } else {
       // For register offset, we encode the shift type and negation flag
       // here.
-      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
-                              Memory.ShiftImm, Memory.ShiftType);
-    }
-    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+      int32_t Val =
+          ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
       Inst.addOperand(MCOperand::createImm(Val));
     }
+  }
 
   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     assert(CE && "non-constant AM2OffsetImm operand!");
     int32_t Val = CE->getValue();
     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
     // Special case for #-0
void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
     // and we reject it.
     if (isImm()) {
       Inst.addOperand(MCOperand::createExpr(getImm()));
       Inst.addOperand(MCOperand::createReg(0));
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
-    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
     if (!Memory.OffsetRegNum) {
+      if (!Memory.OffsetImm)
+        Inst.addOperand(MCOperand::createImm(0));
+      else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+        int32_t Val = CE->getValue();
         ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
         // Special case for #-0
-      if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
-      if (Val < 0) Val = -Val;
+        if (Val == std::numeric_limits<int32_t>::min())
+          Val = 0;
+        if (Val < 0)
+          Val = -Val;
         Val = ARM_AM::getAM3Opc(AddSub, Val);
+        Inst.addOperand(MCOperand::createImm(Val));
+      } else
+        Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
     } else {
       // For register offset, we encode the shift type and negation flag
       // here.
-      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
-    }
-    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+      int32_t Val =
+          ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
       Inst.addOperand(MCOperand::createImm(Val));
     }
+  }
 
   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     if (Kind == k_PostIndexRegister) {
       int32_t Val =
         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
       Inst.addOperand(MCOperand::createImm(Val));
void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm()) {
       Inst.addOperand(MCOperand::createExpr(getImm()));
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
       // The lower two bits are always zero and as such are not encoded.
-    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
+      int32_t Val = CE->getValue() / 4;
       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
       // Special case for #-0
-    if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
-    if (Val < 0) Val = -Val;
+      if (Val == std::numeric_limits<int32_t>::min())
+        Val = 0;
+      if (Val < 0)
+        Val = -Val;
       Val = ARM_AM::getAM5Opc(AddSub, Val);
-    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
       Inst.addOperand(MCOperand::createImm(Val));
+    } else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm()) {
       Inst.addOperand(MCOperand::createExpr(getImm()));
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
     // The lower bit is always zero and as such is not encoded.
-    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
+      int32_t Val = CE->getValue() / 2;
       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
       // Special case for #-0
-    if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
-    if (Val < 0) Val = -Val;
+      if (Val == std::numeric_limits<int32_t>::min())
+        Val = 0;
+      if (Val < 0)
+        Val = -Val;
       Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
-    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
       Inst.addOperand(MCOperand::createImm(Val));
+    } else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm()) {
       Inst.addOperand(MCOperand::createExpr(getImm()));
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
-    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
     // and we reject it.
     if (isImm()) {
       Inst.addOperand(MCOperand::createExpr(getImm()));
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
-    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    // The lower two bits are always zero and as such are not encoded.
-    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      // The lower two bits are always zero and as such are not encoded.
+      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
   }
 
   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If this is an immediate, it's a label reference.
     if (isImm()) {
       addExpr(Inst, getImm());
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
     // Otherwise, it's a normal memory reg+offset.
-    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If this is an immediate, it's a label reference.
     if (isImm()) {
       addExpr(Inst, getImm());
       Inst.addOperand(MCOperand::createImm(0));
       return;
     }
 
     // Otherwise, it's a normal memory reg+offset.
-    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // This is container for the immediate that we will create the constant
     // pool from
     addExpr(Inst, getConstantPoolImm());
   }

   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
   }
 
   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      // The lower two bits are always zero and as such are not encoded.
+      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      Inst.addOperand(MCOperand::createImm(CE->getValue() / 2));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    addExpr(Inst, Memory.OffsetImm);
   }
 
   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
-    Inst.addOperand(MCOperand::createImm(Val));
+    if (!Memory.OffsetImm)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
+      // The lower two bits are always zero and as such are not encoded.
+      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
+    else
+      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
   }
 
   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     assert(CE && "non-constant post-idx-imm8 operand!");
     int Imm = CE->getValue();
     bool isAdd = Imm >= 0;
static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
     auto Op = std::make_unique<ARMOperand>(k_Immediate);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
   static std::unique_ptr<ARMOperand>
-  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
-            unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
-            unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
-            SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
+  CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
+            ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
+            bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
     auto Op = std::make_unique<ARMOperand>(k_Memory);
     Op->Memory.BaseRegNum = BaseRegNum;
     Op->Memory.OffsetImm = OffsetImm;
     Op->Memory.OffsetRegNum = OffsetRegNum;
     Op->Memory.ShiftType = ShiftType;
     Op->Memory.ShiftImm = ShiftImm;
     Op->Memory.Alignment = Alignment;
     Op->Memory.isNegative = isNegative;
if (Parser.getTok().is(AsmToken::Hash) ||
       Parser.getTok().is(AsmToken::LParen) ||
       Parser.getTok().is(AsmToken::Integer)) {
     if (Parser.getTok().is(AsmToken::Hash) ||
         Parser.getTok().is(AsmToken::Dollar))
       Parser.Lex(); // Eat '#' or '$'
     E = Parser.getTok().getLoc();
 
     bool isNegative = getParser().getTok().is(AsmToken::Minus);
-    const MCExpr *Offset;
+    const MCExpr *Offset, *AdjustedOffset;
     if (getParser().parseExpression(Offset))
      return true;
 
-    // The expression has to be a constant. Memory references with relocations
-    // don't come through here, as they use the <label> forms of the relevant
-    // instructions.
-    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
-    if (!CE)
-      return Error (E, "constant expression expected");
-
+    if (const auto *CE = dyn_cast<MCConstantExpr>(Offset)) {
       // If the constant was #-0, represent it as
       // std::numeric_limits<int32_t>::min().
       int32_t Val = CE->getValue();
       if (isNegative && Val == 0)
         CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
                                     getContext());
+      // Don't worry about range checking the value here. That's handled by
+      // the is*() predicates.
+      AdjustedOffset = CE;
+    } else
+      AdjustedOffset = Offset;
+    Operands.push_back(ARMOperand::CreateMem(
+        BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E));
 
     // Now we should have the closing ']'
     if (Parser.getTok().isNot(AsmToken::RBrac))
       return Error(Parser.getTok().getLoc(), "']' expected");
     E = Parser.getTok().getEndLoc();
     Parser.Lex(); // Eat right bracket token.
 
-    // Don't worry about range checking the value here. That's handled by
-    // the is*() predicates.
-    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
-                                             ARM_AM::no_shift, 0, 0,
-                                             false, S, E));
-
     // If there's a pre-indexing writeback marker, '!', just add it as a token
     // operand.
     if (Parser.getTok().is(AsmToken::Exclaim)) {
       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
       Parser.Lex(); // Eat the '!'.
     }
 
     return false;

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
       {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
       {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
       {"fixup_t2_pcrel_10", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_pcrel_9", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+      {"fixup_arm_ldst_abs_12", 0, 32},
       {"fixup_thumb_adr_pcrel_10", 0, 8,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
       {"fixup_t2_adr_pcrel_12", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
       {"fixup_arm_mod_imm", 0, 12, 0},
       {"fixup_t2_so_imm", 0, 26, 0},
       {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfcsel_else_target", 0, 32, 0},
       {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
-  };
+      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
   const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // ARMFixupKinds.h.
       //
       // Name                      Offset (bits) Size (bits)     Flags
       {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
       {"fixup_t2_ldst_pcrel_12", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
       {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
       {"fixup_t2_pcrel_10", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_pcrel_9", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+      {"fixup_arm_ldst_abs_12", 0, 32},
       {"fixup_thumb_adr_pcrel_10", 8, 8,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
       {"fixup_t2_adr_pcrel_12", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
       {"fixup_arm_mod_imm", 20, 12, 0},
       {"fixup_t2_so_imm", 26, 6, 0},
       {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfcsel_else_target", 0, 32, 0},
       {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
-  };
+      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
 
   // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
   // any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
case ARM::fixup_t2_movw_lo16: {
     // inst{7-0} = Lo8;
     Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
     return swapHalfWords(Value, Endian == support::little);
   }
   case ARM::fixup_arm_ldst_pcrel_12:
     // ARM PC-relative values are offset by 8.
     Value -= 4;
     LLVM_FALLTHROUGH;
-  case ARM::fixup_t2_ldst_pcrel_12: {
+  case ARM::fixup_t2_ldst_pcrel_12:
     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     Value -= 4;
+    LLVM_FALLTHROUGH;
+  case ARM::fixup_arm_ldst_abs_12: {
     bool isAdd = true;
     if ((int64_t)Value < 0) {
       Value = -Value;
       isAdd = false;
     }
     if (Value >= 4096) {
       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
       return 0;
static unsigned getFixupKindNumBytes(unsigned Kind) {
   case ARM::fixup_arm_thumb_cb:
   case ARM::fixup_arm_mod_imm:
     return 2;
 
   case ARM::fixup_arm_pcrel_10_unscaled:
   case ARM::fixup_arm_ldst_pcrel_12:
   case ARM::fixup_arm_pcrel_10:
   case ARM::fixup_arm_pcrel_9:
+  case ARM::fixup_arm_ldst_abs_12:
   case ARM::fixup_arm_adr_pcrel_12:
   case ARM::fixup_arm_uncondbl:
   case ARM::fixup_arm_condbl:
   case ARM::fixup_arm_blx:
   case ARM::fixup_arm_condbranch:
   case ARM::fixup_arm_uncondbranch:
     return 3;
 

llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h

enum Fixups {
   // of Thumb2 instructions.
   fixup_t2_pcrel_10,
   // 9-bit PC relative relocation for symbol addresses used in VFP instructions
   // where bit 0 not encoded (so it's encoded as an 8-bit immediate).
   fixup_arm_pcrel_9,
   // Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
   // of Thumb2 instructions.
   fixup_t2_pcrel_9,
+  // 12-bit immediate value.
+  fixup_arm_ldst_abs_12,
   // 10-bit PC relative relocation for symbol addresses where the lower 2 bits
   // are not encoded (so it's encoded as an 8-bit immediate).
   fixup_thumb_adr_pcrel_10,
   // 12-bit PC relative relocation for the ADR instruction.
   fixup_arm_adr_pcrel_12,
   // 12-bit PC relative relocation for the ADR instruction.
   fixup_t2_adr_pcrel_12,
   // 24-bit PC relative relocation for conditional branch instructions.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
 uint32_t ARMMCCodeEmitter::
 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
                         SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI) const {
   // {17-13} = reg
   // {12}    = (U)nsigned (add == '1', sub == '0')
   // {11-0}  = imm12
-  unsigned Reg, Imm12;
+  unsigned Reg = 0, Imm12 = 0;
   bool isAdd = true;
   // If The first operand isn't a register, we have a label reference.
   const MCOperand &MO = MI.getOperand(OpIdx);
-  if (!MO.isReg()) {
-    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
-    Imm12 = 0;
-
-    if (MO.isExpr()) {
-      const MCExpr *Expr = MO.getExpr();
-      isAdd = false ; // 'U' bit is set as part of the fixup.
-
-      MCFixupKind Kind;
-      if (isThumb2(STI))
-        Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
-      else
-        Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
-      Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+  if (MO.isReg()) {
+    const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
+    if (MO1.isImm()) {
+      isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
+    } else if (MO1.isExpr()) {
+      assert(!isThumb(STI) && !isThumb2(STI) &&
+             "Thumb mode requires different encoding");
+      Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
+      isAdd = false; // 'U' bit is set as part of the fixup.
+      MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
+      Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
+    }
+  } else if (MO.isExpr()) {
+    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
+    isAdd = false; // 'U' bit is set as part of the fixup.
+    Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
 
-      ++MCNumCPRelocations;
-    } else {
-      Reg = ARM::PC;
-      int32_t Offset = MO.getImm();
-      if (Offset == INT32_MIN) {
-        Offset = 0;
-        isAdd = false;
-      } else if (Offset < 0) {
-        Offset *= -1;
-        isAdd = false;
-      }
-      Imm12 = Offset;
-    }
-  } else
-    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
-
   uint32_t Binary = Imm12 & 0xfff;
   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
   if (isAdd)
     Binary |= (1 << 12);
   Binary |= (Reg << 13);
   return Binary;
 }
 

llvm/test/MC/ARM/arm-memory-instructions-immediate.s

+// RUN: llvm-mc -triple=armv7 -filetype=obj %s | llvm-objdump --triple=armv7 -d - | FileCheck %s
+// RUN: not llvm-mc -triple=armv7 -filetype=obj --defsym=ERR=1 < %s -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
+
+    .syntax unified
+// Check that the assembler accepts the result of symbolic expressions as the
+// immediate operand in load and stores.
+0:
+// CHECK-LABEL: foo
+    .space 1024
+1:
+foo:
+    ldr r0, [r1, #(1b - 0b)]
+// CHECK-NEXT: ldr r0, [r1, #1024]
+    ldr r0, [r1, #(0b - 1b)]
+// CHECK-NEXT: ldr r0, [r1, #-1024]
+    ldrb r0, [r1, #(1b-0b)]
+// CHECK-NEXT: ldrb r0, [r1, #1024]
+    str r0, [r1, #(1b-0b)]
+// CHECK-NEXT: str r0, [r1, #1024]
+    strb r0, [r1, #(1b-0b)]
+// CHECK-NEXT: strb r0, [r1, #1024]
+.ifdef ERR
+    str r0, [r1, 1b]
+// ERR:[[#@LINE-1]]:5: error: unsupported relocation on symbol
+.endif