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[RISCV] Add isel patterns to handle vrsub intrinsic with 2 vector operands.

Authored by craig.topper on Apr 1 2021, 2:07 PM.

Description

[RISCV] Add isel patterns to handle vrsub intrinsic with 2 vector operands.

This occurs when we type legalize an i64 scalar input on RV32. We
need to manually splat, which requires a vector input. Rather
than special case this in lowering just pattern match it.

Details

Committed
craig.topperApr 1 2021, 2:10 PM
Parents
rG17800f900dca: [tests] Add tests for forthcoming funcattrs nosync inference improvement
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