[AArch64] Enable UseAA globally in the AArch64 backend

[dmgreen]

Summary

This is similar to D69796 from the ARM backend. We remove the UseAA feature, enabling it globally in the AArch64 backend. This should in general be an improvement allowing the backend to reorder more instructions in scheduling and codegen, and enabling it by default helps to improve the testing of the feature, not making it cpu-specific. A debugging option is added instead for testing.

[david-arm]

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

135

This looks like there is potentially a regression here? We've gone from a ldp to two 'ldr instructions here.

[dmgreen]

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

135

There are already a lot of command lines added to this test, presumably to attempt to get it to work in the same way as it did in the past. -pre-RA-sched=linearize -enable-misched=false -disable-post-ra. Without those flags this performs the same with and without UseAA.

In general, UseAA can give more scheduling freedom and the compiler is perfectly able to shoot itself in the foot with that extra freedom. The opposite can be true too though, where it does help things, and it should help more than it hinders. And it's already enabled for certain CPU's. This just makes it global.

[david-arm]

LGTM! Thanks for explaining - I think the change looks sensible to me.

[dmgreen]

Thanks. Lets see if the buildbots/everyone else agrees..

llvm/lib/Target/AArch64/AArch64.td

foreach i = {1-7,9-15,18,20-28,30} in
     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
                                              "Reserve X"#i#", making it unavailable "
                                              "as a GPR">;
 
 foreach i = {8-15,18} in
     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 
-def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
-                                    "Use alias analysis during codegen">;
-
 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
     "true",
     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 
 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
     "Prefer likely predicted branches over selects">;
 
def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureCustomCheapAsMoveHandling,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,
                                    FeatureNEON,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
-                                   FeatureUseAA
                                    ]>;
 
 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
                                    "Cortex-A55 ARM processors", [
                                    HasV8_2aOps,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,
                                    FeatureNEON,
                                    FeatureFullFP16,
                                    FeatureDotProd,
                                    FeatureRCPC,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
-                                   FeatureUseAA
                                    ]>;
 
 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
                                    "Cortex-A57 ARM processors", [
                                    FeatureBalanceFPOps,
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureCustomCheapAsMoveHandling,
def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
                                 FeatureRCPC,
                                 FeatureSPE,
                                 FeatureSSBS]>;
 
 def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
                                "CortexR82",
                                "Cortex-R82 ARM Processors", [
                                FeaturePostRAScheduler,
-                               FeatureUseAA,
                                // All other features are implied by v8_0r ops:
                                HasV8_0rOps,
                                ]>;
 
 def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
                                   "Cortex-X1 ARM processors", [
                                   HasV8_2aOps,
                                   FeatureCmpBccFusion,
def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
                                       FeatureCrypto,
                                       FeatureDotProd,
                                       FeatureFPARMv8,
                                       FeatureFullFP16,
                                       FeatureNEON,
                                       FeatureRCPC,
                                       FeatureSSBS,
                                       FeaturePostRAScheduler,
-                                      FeatureUseAA,
                                       FeatureFuseAES,
                                       ]>;
 
 def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
                                       "NeoverseN1",
                                       "Neoverse N1 ARM processors", [
                                       HasV8_2aOps,
                                       FeatureCrypto,
                                       FeatureDotProd,
                                       FeatureFPARMv8,
                                       FeatureFullFP16,
                                       FeatureNEON,
                                       FeatureRCPC,
                                       FeatureSPE,
                                       FeatureSSBS,
                                       FeaturePostRAScheduler,
-                                      FeatureUseAA,
                                       FeatureFuseAES,
                                       ]>;
 
 def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
                                       "NeoverseN2",
                                       "Neoverse N2 ARM processors", [
                                       HasV8_5aOps,
                                       FeatureBF16,
                                       FeatureETE,
                                       FeatureMatMulInt8,
                                       FeatureMTE,
                                       FeatureSVE2,
                                       FeatureSVE2BitPerm,
                                       FeatureTRBE,
                                       FeaturePostRAScheduler,
-                                      FeatureUseAA,
                                       FeatureCrypto,
                                       FeatureFuseAES,
                                       ]>;
 
 def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
                                       "NeoverseV1",
                                       "Neoverse V1 ARM processors", [
                                       HasV8_4aOps,
                                       FeatureBF16,
                                       FeatureCacheDeepPersist,
                                       FeatureCrypto,
                                       FeatureFPARMv8,
                                       FeatureFP16FML,
                                       FeatureFullFP16,
                                       FeatureFuseAES,
                                       FeatureMatMulInt8,
                                       FeatureNEON,
                                       FeaturePerfMon,
                                       FeaturePostRAScheduler,
-                                      FeatureUseAA,
                                       FeatureRandGen,
                                       FeatureSPE,
                                       FeatureSSBS,
                                       FeatureSVE]>;
 
 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
                                    "Qualcomm Saphira processors", [
                                    FeatureCrypto,
def ProcThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
                                           FeatureCrypto,
                                           FeatureFPARMv8,
                                           FeatureArithmeticBccFusion,
                                           FeatureNEON,
                                           FeaturePostRAScheduler,
                                           FeaturePredictableSelectIsExpensive,
                                           FeatureLSE,
                                           FeaturePAuth,
-                                          FeatureUseAA,
                                           FeatureBalanceFPOps,
                                           FeaturePerfMon,
                                           FeatureStrictAlign,
                                           HasV8_3aOps]>;
 
 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
                                     "Cavium ThunderX processors", [
                                     FeatureCRC,

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
 
   // NegativeImmediates - transform instructions with negative immediates
   bool NegativeImmediates = true;
 
   // Enable 64-bit vectorization in SLP.
   unsigned MinVectorRegisterBitWidth = 64;
 
   bool OutlineAtomics = false;
-  bool UseAA = false;
   bool PredictableSelectIsExpensive = false;
   bool BalanceFPOps = false;
   bool CustomAsCheapAsMove = false;
   bool ExynosAsCheapAsMove = false;
   bool UsePostRAScheduler = false;
   bool Misaligned128StoreIsSlow = false;
   bool Paired128IsSlow = false;
   bool STRQroIsSlow = false;
public:
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool isTargetILP32() const {
     return TargetTriple.isArch32Bit() ||
            TargetTriple.getEnvironment() == Triple::GNUILP32;
   }
 
-  bool useAA() const override { return UseAA; }
+  bool useAA() const override;
 
   bool outlineAtomics() const { return OutlineAtomics; }
 
   bool hasVH() const { return HasVH; }
   bool hasPAN() const { return HasPAN; }
   bool hasLOR() const { return HasLOR; }
 
   bool hasPsUAO() const { return HasPsUAO; }

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

static cl::opt<unsigned> SVEVectorBitsMax(
     cl::init(0), cl::Hidden);
 
 static cl::opt<unsigned> SVEVectorBitsMin(
     "aarch64-sve-vector-bits-min",
     cl::desc("Assume SVE vector registers are at least this big, "
              "with zero meaning no minimum size is assumed."),
     cl::init(0), cl::Hidden);
 
+static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
+                           cl::desc("Enable the use of AA during codegen."));
+
 AArch64Subtarget &
 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
                                                   StringRef CPUString) {
   // Determine default and user-specified characteristics
 
   if (CPUString.empty())
     CPUString = "generic";
 
if (SVEVectorBitsMax == 0)
     return (SVEVectorBitsMin / 128) * 128;
   return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128;
 }
 
 bool AArch64Subtarget::useSVEForFixedLengthVectors() const {
   // Prefer NEON unless larger SVE registers are available.
   return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
 }
+
+bool AArch64Subtarget::useAA() const { return UseAA; }

llvm/test/CodeGen/AArch64/aarch64-gep-opt.ll

 ; RUN: llc -O3 -aarch64-enable-gep-opt=true -verify-machineinstrs %s -o - | FileCheck %s
-; RUN: llc -O3 -aarch64-enable-gep-opt=true -mattr=-use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
-; RUN: llc -O3 -aarch64-enable-gep-opt=true -mattr=+use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
-; RUN: llc -O3 -aarch64-enable-gep-opt=true -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
-; RUN: llc -O3 -aarch64-enable-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
+; RUN: llc -O3 -aarch64-enable-gep-opt=true -print-after=codegenprepare < %s 2>&1 | FileCheck --check-prefix=CHECK-UseAA %s
+; RUN: llc -O3 -aarch64-enable-gep-opt=true -aarch64-use-aa=false -print-after=codegenprepare < %s 2>&1 | FileCheck --check-prefix=CHECK-NoAA %s
+; RUN: llc -O3 -aarch64-enable-gep-opt=true -print-after=codegenprepare -mcpu=cyclone < %s 2>&1 | FileCheck --check-prefix=CHECK-UseAA %s
+; RUN: llc -O3 -aarch64-enable-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s 2>&1 | FileCheck --check-prefix=CHECK-UseAA %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnueabi"
 
 ; Following test cases test enabling SeparateConstOffsetFromGEP pass in AArch64
 ; backend. If useAA() returns true, it will lower a GEP with multiple indices
 ; into GEPs with a single index, otherwise it will lower it into a
 ; "ptrtoint+arithmetics+inttoptr" form.
 
 %struct = type { i32, i32, i32, i32, [20 x i32] }
 
 ; Check that when two complex GEPs are used in two basic blocks, LLVM can
-; elimilate the common subexpression for the second use.
+; eliminate the common subexpression for the second use.
 define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) {
   %liberties = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
   %1 = load i32, i32* %liberties, align 4
   %cmp = icmp eq i32 %1, %lib
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %origin = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

 define dso_local void @test_va_copy() {
 ; CHECK-LABEL: test_va_copy:
   %srcaddr = bitcast %va_list* @var to i8*
   %dstaddr = bitcast %va_list* @second_list to i8*
   call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
 
 ; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
-; CHECK: ldp [[BLOCK:q[0-9]+]], [[BLOCK:q[0-9]+]], [x[[SRC]]]
+; CHECK: ldr [[BLOCKB:q[0-9]+]], [x[[SRC]], #16]
 ; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
-; CHECK: stp [[BLOCK:q[0-9]+]], [[BLOCK:q[0-9]+]], [x[[DST]]]
+; CHECK: ldr [[BLOCKA:q[0-9]+]], [x[[SRC]]]
+; CHECK: stp [[BLOCKA]], [[BLOCKB]], [x[[DST]]]
   ret void
 ; CHECK: ret
 }

llvm/test/CodeGen/AArch64/arm64-virtual_base.ll

 %struct.Ray_Struct = type { [3 x double], [3 x double], i32, [100 x %struct.Interior_Struct*] }
 %struct.istack_struct = type { %struct.istack_struct*, %struct.istk_entry*, i32 }
 %struct.istk_entry = type { double, [3 x double], [3 x double], %struct.Object_Struct*, i32, i32, double, double, i8* }
 %struct.Transform_Struct = type { [4 x [4 x double]], [4 x [4 x double]] }
 %struct.Bezier_Node_Struct = type { i32, [3 x double], double, i32, i8* }
 
 define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) {
 ; CHECK: Precompute_Patch_Values
-; CHECK: ldr [[VAL:x[0-9]+]], [x0, #288]
-; CHECK-NEXT: ldr [[VAL2:q[0-9]+]], [x0, #272]
-; CHECK-NEXT: str [[VAL]], [sp, #232]
+; CHECK: ldr [[VAL2:q[0-9]+]], [x0, #272]
+; CHECK-NEXT: ldr [[VAL:x[0-9]+]], [x0, #288]
 ; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216]
+; CHECK-NEXT: str [[VAL]], [sp, #232]
 entry:
   %Control_Points = alloca [16 x [3 x double]], align 8
   %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]], [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
   %tmp14 = bitcast double* %arraydecay5.3.1 to i8*
   %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct, %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
   %tmp15 = bitcast double* %arraydecay11.3.1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1)

llvm/test/CodeGen/AArch64/ilp32-va.ll

 define dso_local void @test_va_copy() {
 ; CHECK-LABEL: test_va_copy:
   %srcaddr = bitcast %va_list* @var to i8*
   %dstaddr = bitcast %va_list* @second_list to i8*
   call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
 
 ; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
-; CHECK: ldr [[BLOCK:q[0-9]+]], [x[[SRC]]]
-; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
 ; CHECK: ldr [[BLOCK:w[0-9]+]], [x[[SRC]], #16]
-; CHECK: str [[BLOCK:q[0-9]+]], [x[[DST]]]
+; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
 ; CHECK: str [[BLOCK:w[0-9]+]], [x[[DST]], #16]
+; CHECK: ldr [[BLOCK:q[0-9]+]], [x[[SRC]]]
+; CHECK: str [[BLOCK:q[0-9]+]], [x[[DST]]]
   ret void
 ; CHECK: ret
 }

llvm/test/CodeGen/AArch64/misched-stp.ll

 ; REQUIRES: asserts
-; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa,+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s
 
 ; Tests to check that the scheduler dependencies derived from alias analysis are
 ; correct when we have loads that have been split up so that they can later be
 ; merged into STP.
 
 ; Now that overwritten stores are elided in SelectionDAG, dependencies
 ; are resolved and removed before MISCHED. Check that we have
 ; equivalent pair of stp calls as a baseline.

llvm/test/CodeGen/AArch64/seh-finally.ll

ehcleanup:                                        ; preds = %entry
   cleanupret from %2 unwind to caller
 }
 
 define void @fin_simple_seh(i8 %abnormal_termination, i8* %frame_pointer) {
 entry:
 ; CHECK-LABEL: fin_simple_seh
 ; CHECK: movz    x8, #:abs_g1_s:.Lsimple_seh$frame_escape_0
 ; CHECK: movk    x8, #:abs_g0_nc:.Lsimple_seh$frame_escape_0
+; CHECK: ldr     w8, [x1, x8]
 ; CHECK: strb    w0, [sp, #15]
-; CHECK: ldr     w0, [x1, x8]
 ; CHECK: bl      foo
 
   %frame_pointer.addr = alloca i8*, align 8
   %abnormal_termination.addr = alloca i8, align 1
   %0 = call i8* @llvm.localrecover(i8* bitcast (void ()* @simple_seh to i8*), i8* %frame_pointer, i32 0)
   %o = bitcast i8* %0 to %struct.S*
   store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
   store i8 %abnormal_termination, i8* %abnormal_termination.addr, align 1
ehcleanup:                                        ; preds = %entry
   cleanupret from %2 unwind to caller
 }
 
 define void @fin_stack_realign(i8 %abnormal_termination, i8* %frame_pointer) {
 entry:
 ; CHECK-LABEL: fin_stack_realign
 ; CHECK: movz    x8, #:abs_g1_s:.Lstack_realign$frame_escape_0
 ; CHECK: movk    x8, #:abs_g0_nc:.Lstack_realign$frame_escape_0
+; CHECK: ldr     w8, [x1, x8]
 ; CHECK: strb    w0, [sp, #15]
-; CHECK: ldr     w0, [x1, x8]
 ; CHECK: bl      foo
 
   %frame_pointer.addr = alloca i8*, align 8
   %abnormal_termination.addr = alloca i8, align 1
   %0 = call i8* @llvm.localrecover(i8* bitcast (void ()* @stack_realign to i8*), i8* %frame_pointer, i32 0)
   %o = bitcast i8* %0 to %struct.S*
   store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
   store i8 %abnormal_termination, i8* %abnormal_termination.addr, align 1
ehcleanup:                                        ; preds = %entry
   cleanupret from %6 unwind to caller
 }
 
 define void @fin_vla_present(i8 %abnormal_termination, i8* %frame_pointer) {
 entry:
 ; CHECK-LABEL: fin_vla_present
 ; CHECK: movz    x8, #:abs_g1_s:.Lvla_present$frame_escape_0
 ; CHECK: movk    x8, #:abs_g0_nc:.Lvla_present$frame_escape_0
+; CHECK: ldr     w8, [x1, x8]
 ; CHECK: strb    w0, [sp, #15]
-; CHECK: ldr     w0, [x1, x8]
 ; CHECK: bl      foo
 
   %frame_pointer.addr = alloca i8*, align 8
   %abnormal_termination.addr = alloca i8, align 1
   %0 = call i8* @llvm.localrecover(i8* bitcast (void (i32)* @vla_present to i8*), i8* %frame_pointer, i32 0)
   %n.addr = bitcast i8* %0 to i32*
   store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
   store i8 %abnormal_termination, i8* %abnormal_termination.addr, align 1
ehcleanup:                                        ; preds = %entry
   cleanupret from %6 unwind to caller
 }
 
 define void @fin_vla_and_realign(i8 %abnormal_termination, i8* %frame_pointer) {
 entry:
 ; CHECK-LABEL: fin_vla_and_realign
 ; CHECK: movz    x8, #:abs_g1_s:.Lvla_and_realign$frame_escape_0
 ; CHECK: movk    x8, #:abs_g0_nc:.Lvla_and_realign$frame_escape_0
+; CHECK: ldr     w8, [x1, x8]
 ; CHECK: strb    w0, [sp, #15]
-; CHECK: ldr     w0, [x1, x8]
 ; CHECK: bl      foo
 
   %frame_pointer.addr = alloca i8*, align 8
   %abnormal_termination.addr = alloca i8, align 1
   %0 = call i8* @llvm.localrecover(i8* bitcast (void (i32)* @vla_and_realign to i8*), i8* %frame_pointer, i32 0)
   %o = bitcast i8* %0 to %struct.S*
   store i8* %frame_pointer, i8** %frame_pointer.addr, align 8
   store i8 %abnormal_termination, i8* %abnormal_termination.addr, align 1