[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)

[craig.topper]

Summary

This pattern occurs when lowering for overflow operations
introduce an xor after select_cc has already been formed.

I had to rework another combine that looked for select_cc of an xor
with 1. That xor will now get combined away so we just need to
look for the RHS of the select_cc being 1.

[luismarques]

Seems correct.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (auto GREV = combineORToGREV(SDValue(N, 0), DCI.DAG, Subtarget))
       return GREV;
     if (auto GORC = combineORToGORC(SDValue(N, 0), DCI.DAG, Subtarget))
       return GORC;
     if (auto SHFL = combineORToSHFL(SDValue(N, 0), DCI.DAG, Subtarget))
       return SHFL;
     break;
   case RISCVISD::SELECT_CC: {
     // Transform
-    // (select_cc (xor X, 1), 0, setne, trueV, falseV) ->
-    // (select_cc X, 0, seteq, trueV, falseV) if we can prove X is 0/1.
-    // This can occur when legalizing some floating point comparisons.
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
     auto CCVal = static_cast<ISD::CondCode>(N->getConstantOperandVal(2));
+    if (!ISD::isIntEqualitySetCC(CCVal))
+      break;
+    // Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) ->
+    //      (select_cc X, Y, eq/ne, trueV, falseV)
+    if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS))
+      return DAG.getNode(RISCVISD::SELECT_CC, SDLoc(N), N->getValueType(0),
+                         {LHS.getOperand(0), LHS.getOperand(1),
+                          N->getOperand(2), N->getOperand(3),
+                          N->getOperand(4)});
+    // (select_cc X, 1, setne, trueV, falseV) ->
+    // (select_cc X, 0, seteq, trueV, falseV) if we can prove X is 0/1.
+    // This can occur when legalizing some floating point comparisons.
     APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
-    if (ISD::isIntEqualitySetCC(CCVal) && isNullConstant(RHS) &&
-        LHS.getOpcode() == ISD::XOR && isOneConstant(LHS.getOperand(1)) &&
-        DAG.MaskedValueIsZero(LHS.getOperand(0), Mask)) {
+    if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) {
       SDLoc DL(N);
       CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
       SDValue TargetCC = DAG.getConstant(CCVal, DL, Subtarget.getXLenVT());
-      return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0),
-                         {LHS.getOperand(0), RHS, TargetCC, N->getOperand(3),
-                          N->getOperand(4)});
+      RHS = DAG.getConstant(0, DL, LHS.getValueType());
+      return DAG.getNode(
+          RISCVISD::SELECT_CC, DL, N->getValueType(0),
+          {LHS, RHS, TargetCC, N->getOperand(3), N->getOperand(4)});
     }
+
     break;
   }
   case ISD::SETCC: {
     // (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
     // Comparing with 0 may allow us to fold into bnez/beqz.
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
     if (LHS.getValueType().isScalableVector())

llvm/test/CodeGen/RISCV/sadd_sat.ll

 ; RV32I-NEXT:    add a3, a0, a1
 ; RV32I-NEXT:    lui a0, 524288
 ; RV32I-NEXT:    bgez a3, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    slt a2, a3, a2
 ; RV32I-NEXT:    slti a1, a1, 0
-; RV32I-NEXT:    xor a1, a1, a2
-; RV32I-NEXT:    bnez a1, .LBB0_4
+; RV32I-NEXT:    bne a1, a2, .LBB0_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a0, a1

 ; RV32IZbb-NEXT:    add a3, a0, a1
 ; RV32IZbb-NEXT:    lui a0, 524288
 ; RV32IZbb-NEXT:    bgez a3, .LBB0_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    addi a0, a0, -1
 ; RV32IZbb-NEXT:  .LBB0_2:
 ; RV32IZbb-NEXT:    slt a2, a3, a2
 ; RV32IZbb-NEXT:    slti a1, a1, 0
-; RV32IZbb-NEXT:    xor a1, a1, a2
-; RV32IZbb-NEXT:    bnez a1, .LBB0_4
+; RV32IZbb-NEXT:    bne a1, a2, .LBB0_4
 ; RV32IZbb-NEXT:  # %bb.3:
 ; RV32IZbb-NEXT:    mv a0, a3
 ; RV32IZbb-NEXT:  .LBB0_4:
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    add a0, a0, a1

 ; RV64I-NEXT:    addi a0, zero, -1
 ; RV64I-NEXT:    slli a0, a0, 63
 ; RV64I-NEXT:    bgez a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    slt a2, a3, a2
 ; RV64I-NEXT:    slti a1, a1, 0
-; RV64I-NEXT:    xor a1, a1, a2
-; RV64I-NEXT:    bnez a1, .LBB1_4
+; RV64I-NEXT:    bne a1, a2, .LBB1_4
 ; RV64I-NEXT:  # %bb.3:
 ; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a4, a1

 ; RV64IZbb-NEXT:    addi a0, zero, -1
 ; RV64IZbb-NEXT:    slli a0, a0, 63
 ; RV64IZbb-NEXT:    bgez a3, .LBB1_2
 ; RV64IZbb-NEXT:  # %bb.1:
 ; RV64IZbb-NEXT:    addi a0, a0, -1
 ; RV64IZbb-NEXT:  .LBB1_2:
 ; RV64IZbb-NEXT:    slt a2, a3, a2
 ; RV64IZbb-NEXT:    slti a1, a1, 0
-; RV64IZbb-NEXT:    xor a1, a1, a2
-; RV64IZbb-NEXT:    bnez a1, .LBB1_4
+; RV64IZbb-NEXT:    bne a1, a2, .LBB1_4
 ; RV64IZbb-NEXT:  # %bb.3:
 ; RV64IZbb-NEXT:    mv a0, a3
 ; RV64IZbb-NEXT:  .LBB1_4:
 ; RV64IZbb-NEXT:    ret
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.sadd.sat.i4(i4, i4)
 declare i8 @llvm.sadd.sat.i8(i8, i8)
 declare i16 @llvm.sadd.sat.i16(i16, i16)
 declare i32 @llvm.sadd.sat.i32(i32, i32)
 declare i64 @llvm.sadd.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    mul a2, a1, a2
 ; RV32I-NEXT:    add a1, a0, a2
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    slti a2, a2, 0
-; RV32I-NEXT:    xor a2, a2, a0
 ; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    bltz a1, .LBB0_3
+; RV32I-NEXT:    bgez a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a2, .LBB0_4
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    bnez a2, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    slt a3, a1, a3
+; RV32I-NEXT:    slti a2, a2, 0
+; RV32I-NEXT:    bne a2, a3, .LBB0_4
+; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:  .LBB0_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    mulw a1, a1, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addiw a2, a1, -1
 ; RV64I-NEXT:    bge a0, a2, .LBB0_3
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    bge a1, a0, .LBB0_4
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB0_3:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    blt a1, a0, .LBB0_2
 ; RV64I-NEXT:  .LBB0_4:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
+; RV32IZbb-NEXT:    mv a3, a0
 ; RV32IZbb-NEXT:    mul a2, a1, a2
 ; RV32IZbb-NEXT:    add a1, a0, a2
-; RV32IZbb-NEXT:    slt a0, a1, a0
-; RV32IZbb-NEXT:    slti a2, a2, 0
-; RV32IZbb-NEXT:    xor a2, a2, a0
 ; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bltz a1, .LBB0_3
+; RV32IZbb-NEXT:    bgez a1, .LBB0_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    beqz a2, .LBB0_4
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB0_3:
 ; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:    bnez a2, .LBB0_2
-; RV32IZbb-NEXT:  .LBB0_4:
+; RV32IZbb-NEXT:  .LBB0_2:
+; RV32IZbb-NEXT:    slt a3, a1, a3
+; RV32IZbb-NEXT:    slti a2, a2, 0
+; RV32IZbb-NEXT:    bne a2, a3, .LBB0_4
+; RV32IZbb-NEXT:  # %bb.3:
 ; RV32IZbb-NEXT:    mv a0, a1
+; RV32IZbb-NEXT:  .LBB0_4:
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    sext.w a0, a0
 ; RV64IZbb-NEXT:    mulw a1, a1, a2
 ; RV64IZbb-NEXT:    add a0, a0, a1
 ; RV64IZbb-NEXT:    lui a1, 524288

 ; RV64I-NEXT:    addi a0, zero, -1
 ; RV64I-NEXT:    slli a0, a0, 63
 ; RV64I-NEXT:    bgez a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    slt a1, a3, a1
 ; RV64I-NEXT:    slti a2, a2, 0
-; RV64I-NEXT:    xor a1, a2, a1
-; RV64I-NEXT:    bnez a1, .LBB1_4
+; RV64I-NEXT:    bne a2, a1, .LBB1_4
 ; RV64I-NEXT:  # %bb.3:
 ; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a2, a1

 ; RV64IZbb-NEXT:    addi a0, zero, -1
 ; RV64IZbb-NEXT:    slli a0, a0, 63
 ; RV64IZbb-NEXT:    bgez a3, .LBB1_2
 ; RV64IZbb-NEXT:  # %bb.1:
 ; RV64IZbb-NEXT:    addi a0, a0, -1
 ; RV64IZbb-NEXT:  .LBB1_2:
 ; RV64IZbb-NEXT:    slt a1, a3, a1
 ; RV64IZbb-NEXT:    slti a2, a2, 0
-; RV64IZbb-NEXT:    xor a1, a2, a1
-; RV64IZbb-NEXT:    bnez a1, .LBB1_4
+; RV64IZbb-NEXT:    bne a2, a1, .LBB1_4
 ; RV64IZbb-NEXT:  # %bb.3:
 ; RV64IZbb-NEXT:    mv a0, a3
 ; RV64IZbb-NEXT:  .LBB1_4:
 ; RV64IZbb-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp
 }

llvm/test/CodeGen/RISCV/ssub_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.ssub.sat.i4(i4, i4)
 declare i8 @llvm.ssub.sat.i8(i8, i8)
 declare i16 @llvm.ssub.sat.i16(i16, i16)
 declare i32 @llvm.ssub.sat.i32(i32, i32)
 declare i64 @llvm.ssub.sat.i64(i64, i64)
 
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    sgtz a2, a1
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xor a2, a2, a0
+; RV32I-NEXT:    mv a2, a0
+; RV32I-NEXT:    sub a3, a0, a1
 ; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    bltz a1, .LBB0_3
+; RV32I-NEXT:    bgez a3, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a2, .LBB0_4
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    sgtz a1, a1
+; RV32I-NEXT:    slt a2, a3, a2
+; RV32I-NEXT:    bne a1, a2, .LBB0_4
+; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_4:
-; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addiw a2, a1, -1
 ; RV64I-NEXT:    bge a0, a2, .LBB0_3
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    bge a1, a0, .LBB0_4
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB0_3:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    blt a1, a0, .LBB0_2
 ; RV64I-NEXT:  .LBB0_4:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
 ; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    sgtz a2, a1
-; RV32IZbb-NEXT:    sub a1, a0, a1
-; RV32IZbb-NEXT:    slt a0, a1, a0
-; RV32IZbb-NEXT:    xor a2, a2, a0
+; RV32IZbb-NEXT:    mv a2, a0
+; RV32IZbb-NEXT:    sub a3, a0, a1
 ; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bltz a1, .LBB0_3
+; RV32IZbb-NEXT:    bgez a3, .LBB0_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    beqz a2, .LBB0_4
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB0_3:
 ; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:    bnez a2, .LBB0_2
+; RV32IZbb-NEXT:  .LBB0_2:
+; RV32IZbb-NEXT:    sgtz a1, a1
+; RV32IZbb-NEXT:    slt a2, a3, a2
+; RV32IZbb-NEXT:    bne a1, a2, .LBB0_4
+; RV32IZbb-NEXT:  # %bb.3:
+; RV32IZbb-NEXT:    mv a0, a3
 ; RV32IZbb-NEXT:  .LBB0_4:
-; RV32IZbb-NEXT:    mv a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    lui a1, 524288
 ; RV64IZbb-NEXT:    addiw a2, a1, -1
 ; RV64IZbb-NEXT:    min a0, a0, a2

 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a5, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sgtz a2, a1
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    xor a2, a2, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    sub a3, a0, a1
 ; RV64I-NEXT:    addi a0, zero, -1
 ; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bltz a1, .LBB1_3
+; RV64I-NEXT:    bgez a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a2, .LBB1_4
-; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB1_3:
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    sgtz a1, a1
+; RV64I-NEXT:    slt a2, a3, a2
+; RV64I-NEXT:    bne a1, a2, .LBB1_4
+; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB1_4:
-; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a4, a1
 ; RV32IZbb-NEXT:    sltu a1, a0, a2
 ; RV32IZbb-NEXT:    sub a5, a4, a3
 ; RV32IZbb-NEXT:    sub a5, a5, a1

 ; RV32IZbb-NEXT:    mv a1, a5
 ; RV32IZbb-NEXT:    ret
 ; RV32IZbb-NEXT:  .LBB1_4:
 ; RV32IZbb-NEXT:    srai a0, a5, 31
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func2:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    sgtz a2, a1
-; RV64IZbb-NEXT:    sub a1, a0, a1
-; RV64IZbb-NEXT:    slt a0, a1, a0
-; RV64IZbb-NEXT:    xor a2, a2, a0
+; RV64IZbb-NEXT:    mv a2, a0
+; RV64IZbb-NEXT:    sub a3, a0, a1
 ; RV64IZbb-NEXT:    addi a0, zero, -1
 ; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bltz a1, .LBB1_3
+; RV64IZbb-NEXT:    bgez a3, .LBB1_2
 ; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    beqz a2, .LBB1_4
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    ret
-; RV64IZbb-NEXT:  .LBB1_3:
 ; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:    bnez a2, .LBB1_2
+; RV64IZbb-NEXT:  .LBB1_2:
+; RV64IZbb-NEXT:    sgtz a1, a1
+; RV64IZbb-NEXT:    slt a2, a3, a2
+; RV64IZbb-NEXT:    bne a1, a2, .LBB1_4
+; RV64IZbb-NEXT:  # %bb.3:
+; RV64IZbb-NEXT:    mv a0, a3
 ; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    mv a0, a1
 ; RV64IZbb-NEXT:    ret
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
 ; RV32I-LABEL: func16:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.ssub.sat.i4(i4, i4)
 declare i8 @llvm.ssub.sat.i8(i8, i8)
 declare i16 @llvm.ssub.sat.i16(i16, i16)
 declare i32 @llvm.ssub.sat.i32(i32, i32)
 declare i64 @llvm.ssub.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    sgtz a2, a1
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xor a2, a2, a0
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    mul a2, a1, a2
+; RV32I-NEXT:    sub a1, a0, a2
 ; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    bltz a1, .LBB0_3
+; RV32I-NEXT:    bgez a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a2, .LBB0_4
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    bnez a2, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    sgtz a2, a2
+; RV32I-NEXT:    slt a3, a1, a3
+; RV32I-NEXT:    bne a2, a3, .LBB0_4
+; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:  .LBB0_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    mulw a1, a1, a2
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addiw a2, a1, -1
 ; RV64I-NEXT:    bge a0, a2, .LBB0_3
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    bge a1, a0, .LBB0_4
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB0_3:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    blt a1, a0, .LBB0_2
 ; RV64I-NEXT:  .LBB0_4:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mul a1, a1, a2
-; RV32IZbb-NEXT:    sgtz a2, a1
-; RV32IZbb-NEXT:    sub a1, a0, a1
-; RV32IZbb-NEXT:    slt a0, a1, a0
-; RV32IZbb-NEXT:    xor a2, a2, a0
+; RV32IZbb-NEXT:    mv a3, a0
+; RV32IZbb-NEXT:    mul a2, a1, a2
+; RV32IZbb-NEXT:    sub a1, a0, a2
 ; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bltz a1, .LBB0_3
+; RV32IZbb-NEXT:    bgez a1, .LBB0_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    beqz a2, .LBB0_4
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB0_3:
 ; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:    bnez a2, .LBB0_2
-; RV32IZbb-NEXT:  .LBB0_4:
+; RV32IZbb-NEXT:  .LBB0_2:
+; RV32IZbb-NEXT:    sgtz a2, a2
+; RV32IZbb-NEXT:    slt a3, a1, a3
+; RV32IZbb-NEXT:    bne a2, a3, .LBB0_4
+; RV32IZbb-NEXT:  # %bb.3:
 ; RV32IZbb-NEXT:    mv a0, a1
+; RV32IZbb-NEXT:  .LBB0_4:
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    sext.w a0, a0
 ; RV64IZbb-NEXT:    mulw a1, a1, a2
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    lui a1, 524288

 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a3, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sgtz a3, a2
-; RV64I-NEXT:    sub a1, a0, a2
-; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    xor a2, a3, a0
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    sub a3, a0, a2
 ; RV64I-NEXT:    addi a0, zero, -1
 ; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bltz a1, .LBB1_3
+; RV64I-NEXT:    bgez a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a2, .LBB1_4
-; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB1_3:
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    sgtz a2, a2
+; RV64I-NEXT:    slt a1, a3, a1
+; RV64I-NEXT:    bne a2, a1, .LBB1_4
+; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB1_4:
-; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a2, a1
 ; RV32IZbb-NEXT:    sltu a1, a0, a4
 ; RV32IZbb-NEXT:    sub a3, a2, a5
 ; RV32IZbb-NEXT:    sub a3, a3, a1

 ; RV32IZbb-NEXT:    mv a1, a3
 ; RV32IZbb-NEXT:    ret
 ; RV32IZbb-NEXT:  .LBB1_4:
 ; RV32IZbb-NEXT:    srai a0, a3, 31
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func64:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    sgtz a3, a2
-; RV64IZbb-NEXT:    sub a1, a0, a2
-; RV64IZbb-NEXT:    slt a0, a1, a0
-; RV64IZbb-NEXT:    xor a2, a3, a0
+; RV64IZbb-NEXT:    mv a1, a0
+; RV64IZbb-NEXT:    sub a3, a0, a2
 ; RV64IZbb-NEXT:    addi a0, zero, -1
 ; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bltz a1, .LBB1_3
+; RV64IZbb-NEXT:    bgez a3, .LBB1_2
 ; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    beqz a2, .LBB1_4
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    ret
-; RV64IZbb-NEXT:  .LBB1_3:
 ; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:    bnez a2, .LBB1_2
+; RV64IZbb-NEXT:  .LBB1_2:
+; RV64IZbb-NEXT:    sgtz a2, a2
+; RV64IZbb-NEXT:    slt a1, a3, a1
+; RV64IZbb-NEXT:    bne a2, a1, .LBB1_4
+; RV64IZbb-NEXT:  # %bb.3:
+; RV64IZbb-NEXT:    mv a0, a3
 ; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    mv a0, a1
 ; RV64IZbb-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp
 }
 
 define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
 ; RV32I-LABEL: func16:

llvm/test/CodeGen/RISCV/xaluo.ll

 ; Check the use of the overflow bit in combination with a select instruction.
 ;
 define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: saddo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    slt a2, a2, a0
 ; RV32-NEXT:    slti a3, a1, 0
-; RV32-NEXT:    xor a2, a3, a2
-; RV32-NEXT:    bnez a2, .LBB22_2
+; RV32-NEXT:    bne a3, a2, .LBB22_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB22_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1

 ; RV32-NEXT:  .LBB24_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a2, a2, a0
 ; RV64-NEXT:    slti a3, a1, 0
-; RV64-NEXT:    xor a2, a3, a2
-; RV64-NEXT:    bnez a2, .LBB24_2
+; RV64-NEXT:    bne a3, a2, .LBB24_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB24_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2

 }
 
 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sgtz a2, a1
 ; RV32-NEXT:    sub a3, a0, a1
 ; RV32-NEXT:    slt a3, a3, a0
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    bnez a2, .LBB30_2
+; RV32-NEXT:    bne a2, a3, .LBB30_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB30_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1

 ; RV32-NEXT:  .LBB32_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    slt a3, a3, a0
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    bnez a2, .LBB32_2
+; RV64-NEXT:    bne a2, a3, .LBB32_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB32_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2