[VPlan] Add plain text (not DOT's digraph) dumps

[a.elovikov]

Summary

I foresee two uses for this:

1. It's easier to use those in debugger.
2. Once we start implementing more VPlan-to-VPlan transformations (especially inner loop massaging stuff), using the vectorized LLVM IR as CHECK targets in LIT test would become too obscure. I can imagine that we'd want to CHECK against VPlan dumps after multiple transformations instead. That would be easier with plain text dumps than with DOT format.

[a.elovikov]

Ping

[fhahn]

Thanks for working on this! Could you split off the changes not directly related to printing in non-DOT mode (like respecting Indent in the individual print() implementations)? Then we can focus the review here on the details how to move to support non-DOT printing, which is very valuable IMO and should probably become the default in the long run.

llvm/lib/Transforms/Vectorize/VPlan.cpp

921

Could you split off the changes not directly related to printing in non-DOT mode (like respecting Indent in the individual print() implementations)?

[a.elovikov]

Rebased on top of D97787.

[a.elovikov]

Ping.

[fhahn]

llvm/lib/Transforms/Vectorize/VPlan.cpp

53

I think having an option to just print the plans make sense, but as a first step, should we start with an option to just toggle between dot printing and regular printing for when using -debug?

864

Could you add a comment explaining that we first print the block and then split up/reconstruct the output with the .dot syntax>

[fhahn]

llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll

41

Did the value here change because the plan gets printed later?

[a.elovikov]

llvm/lib/Transforms/Vectorize/VPlan.cpp

53

I preferred dedicated option for several reasons:

1. Toggling is harder to implement, especially when caring about consistent interfaces. For example, I think that VPBasicBlock|VPValue|VPDef::print should be dedicated for text prints only (and VPBasicBlock can't even be printed as a digraph before this patch), so the only logical place for triggering would be operator<<(ostream&). On the other hand, there is no guarantees that none of the LLVM_DEBUG prints call the print method directly (and not via stream operator).

2. I personally don't like using -debug/-debug-only for LIT testing purposes. Having a more limited/specific output is, IMO, preferable. I'm hoping that option(s) to print VPlan at a given place in the pipeline would be convenient tools for writing LIT tests. As such, I think having this option from the very first plain dump patch makes sense.

If going through the toggling approach, do you expect existing LIT tests (non-unittest) to continue using digraph output or be switched to plain dumps in the first patch? If the former, what would be your suggestion to test the plain dumps?

864

Sure, will update in the next patch set.

llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll

41

I didn't study in details, but I'd expect it to be so. Is that something expected for you, or do you want me to study that change in details (my knowledge of the VPlan pipeline is still limited)?

[a.elovikov]

• Improve comments.
• Don't add a new dump point via cl::opt. Instead, add cl::opt to toggle behavior (dot/plain dumps) for the LVP::printPlans method.

[a.elovikov]

llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll

41

Yes, it gets changed in the middle of InnerLoopVectorizer::createVectorizedLoopSkeleton/InnerLoopVectorizer::createInductionResumeValues.

We seem to be using original LLVM IR value through VPlanIngredient when printing VPWidenIntOrFpInductionRecipe, so modifying original loop when creating the skeleton changes printing.

[fhahn]

Thanks for the latest updates!

I just have a few remaining comments. After those, I think this is good to go. If there are any concerns with the direction by others, it would be great to hear them soon.

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

7829

I think it would make sense to flip things here, as in have the operator for raw_ostream use the non-dot style (because that's what most useful in debuggers too) and then have a Plan::printWithDot() or soemthing for the DOT logic.

llvm/lib/Transforms/Vectorize/VPlan.cpp

406

I think it would be good to separate the block names by a comma or something like that. You could either use join_items or ListSeparator from StringExtras.h

llvm/lib/Transforms/Vectorize/VPlan.h

1749

nit: comment, something like /// Print the plan to \p O.. Some for other instances.

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

3

I think we should have at least a LIT test that also checks -vplan-print-in-dot-format=true. Perhaps this file would a good candidate to do so?

[a.elovikov]

Address review comments.

llvm/lib/Transforms/Vectorize/VPlan.cpp

406

ListSeparator is great! Wasn't aware of it before.

[fhahn]

LGTM, thanks! Please wait a day or 2 with committing, in case there are any remaining concerns with the direction. But I think it is a nice improvement to the user experience.

llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll

3

-prefer-inloop-reductions should not be needed

26

Nit: it would be good to at least one additional BB in the loop, to make sure the edges between blocks are still printed.

[a.elovikov]

llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll

26

This functionality is being tested in unittests already, so I'm only using this file to target the toggle switch, not the digraph dump by itself.

[mehdi_amini]

Push a revert, it seems like it broke the link of clang itself:

FAILED: bin/clang-13
: && /usr/bin/clang++-8 -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -ffunction-sections -fdata-sections -fno-common -Woverloaded-virtual -Wno-nested-anon-types -O3 -DNDEBUG -fuse-ld=lld -Wl,--color-diagnostics   -Wl,--export-dynamic  -Wl,-O3 tools/clang/tools/driver/CMakeFiles/clang.dir/driver.cpp.o tools/clang/tools/driver/CMakeFiles/clang.dir/cc1_main.cpp.o tools/clang/tools/driver/CMakeFiles/clang.dir/cc1as_main.cpp.o tools/clang/tools/driver/CMakeFiles/clang.dir/cc1gen_reproducer_main.cpp.o -o bin/clang-13  -Wl,-rpath,"\$ORIGIN/../lib"  lib/libLLVMX86CodeGen.a  lib/libLLVMX86AsmParser.a  lib/libLLVMX86Desc.a  lib/libLLVMX86Disassembler.a  lib/libLLVMX86Info.a  lib/libLLVMNVPTXCodeGen.a  lib/libLLVMNVPTXDesc.a  lib/libLLVMNVPTXInfo.a  lib/libLLVMAMDGPUCodeGen.a  lib/libLLVMAMDGPUAsmParser.a  lib/libLLVMAMDGPUDesc.a  lib/libLLVMAMDGPUDisassembler.a  lib/libLLVMAMDGPUInfo.a  lib/libLLVMAMDGPUUtils.a  lib/libLLVMAnalysis.a  lib/libLLVMCodeGen.a  lib/libLLVMCore.a  lib/libLLVMipo.a  lib/libLLVMAggressiveInstCombine.a  lib/libLLVMInstCombine.a  lib/libLLVMInstrumentation.a  lib/libLLVMMC.a  lib/libLLVMMCParser.a  lib/libLLVMObjCARCOpts.a  lib/libLLVMOption.a  lib/libLLVMScalarOpts.a  lib/libLLVMSupport.a  lib/libLLVMTransformUtils.a  lib/libLLVMVectorize.a  -lpthread  lib/libclangBasic.a  lib/libclangCodeGen.a  lib/libclangDriver.a  lib/libclangFrontend.a  lib/libclangFrontendTool.a  lib/libclangSerialization.a  lib/libLLVMCFGuard.a  lib/libLLVMAsmPrinter.a  lib/libLLVMDebugInfoDWARF.a  lib/libLLVMDebugInfoMSF.a  lib/libLLVMGlobalISel.a  lib/libLLVMSelectionDAG.a  lib/libLLVMMIRParser.a  lib/libLLVMAMDGPUDesc.a  lib/libLLVMAMDGPUInfo.a  lib/libLLVMAMDGPUUtils.a  lib/libLLVMMCDisassembler.a  lib/libclangCodeGen.a  lib/libLLVMCoverage.a  lib/libLLVMLTO.a  lib/libLLVMCodeGen.a  lib/libLLVMPasses.a  lib/libLLVMObjCARCOpts.a  lib/libLLVMTarget.a  lib/libLLVMCoroutines.a  lib/libLLVMipo.a  lib/libLLVMInstrumentation.a  lib/libLLVMVectorize.a  lib/libLLVMIRReader.a  lib/libLLVMAsmParser.a  lib/libLLVMScalarOpts.a  lib/libLLVMAggressiveInstCombine.a  lib/libLLVMInstCombine.a  lib/libLLVMBitWriter.a  lib/libLLVMLinker.a  lib/libLLVMExtensions.a  lib/libclangRewriteFrontend.a  lib/libclangARCMigrate.a  lib/libclangStaticAnalyzerFrontend.a  lib/libclangStaticAnalyzerCheckers.a  lib/libclangStaticAnalyzerCore.a  lib/libclangCrossTU.a  lib/libclangIndex.a  lib/libclangFrontend.a  lib/libclangDriver.a  lib/libLLVMOption.a  lib/libclangParse.a  lib/libclangSerialization.a  lib/libclangSema.a  lib/libclangAnalysis.a  lib/libclangASTMatchers.a  lib/libclangEdit.a  lib/libclangAST.a  lib/libLLVMFrontendOpenMP.a  lib/libLLVMTransformUtils.a  lib/libLLVMAnalysis.a  lib/libLLVMProfileData.a  lib/libLLVMObject.a  lib/libLLVMMCParser.a  lib/libLLVMBitReader.a  lib/libLLVMTextAPI.a  lib/libclangFormat.a  lib/libclangToolingInclusions.a  lib/libclangToolingCore.a  lib/libclangRewrite.a  lib/libclangLex.a  lib/libclangBasic.a  lib/libLLVMCore.a  lib/libLLVMRemarks.a  lib/libLLVMBitstreamReader.a  lib/libLLVMMC.a  lib/libLLVMBinaryFormat.a  lib/libLLVMDebugInfoCodeView.a  lib/libLLVMSupport.a  -lrt  -ldl  -lpthread  -lm  /usr/lib/x86_64-linux-gnu/libz.so  /usr/lib/x86_64-linux-gnu/libtinfo.so  lib/libLLVMDemangle.a && :
ld.lld: error: undefined symbol: llvm::VPlan::printDOT(llvm::raw_ostream&) const
>>> referenced by LoopVectorize.cpp
>>>               LoopVectorize.cpp.o:(llvm::LoopVectorizationPlanner::printPlans(llvm::raw_ostream&)) in archive lib/libLLVMVectorize.a
 
ld.lld: error: undefined symbol: llvm::VPlan::print(llvm::raw_ostream&) const
>>> referenced by LoopVectorize.cpp
>>>               LoopVectorize.cpp.o:(llvm::LoopVectorizationPlanner::printPlans(llvm::raw_ostream&)) in archive lib/libLLVMVectorize.a
clang: error: linker command failed with exit code 1 (use -v to see invocation)

[antiagainst]

FYI: this seems to break the Clang target when building MLIR: https://buildkite.com/mlir/mlir-core/builds/12351#2ce52a15-5694-4dac-b661-bf77b3348461

[antiagainst]

Reading the logic a bit more, it looks to me that we need to put #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) inside LoopVectorizationPlanner::printPlans.

[a.elovikov]

Sorry for the troubles and thanks for reverting that for me - I didn't receive notifications from buildbots for it. Yes, it's probably related to those #ifs. I'm starting a Release build to reproduce and create a fix.

[mehdi_amini]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

7832

I think this ought to be guarded by #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) as well

[a.elovikov]

It seems the code wasn't properly guarded before this change, and the proper fix would require changing too many places. I'd prefer to do it in separate patch.

I see two options:

1. "Unguard" the print routines here and commit, work on the cleanup as the next patch.
2. Delay this patch, develop cleanup first, rebase/reland this patch once cleanup is committed. Note that this patch doesn't make things worse - we had all operator<< accessible in release builds before it.

I'd prefer to go with the first one, but I can understand if some people would prefer two. What do you think?

[mehdi_amini]

In D96628#2635549, @a.elovikov wrote:

I'd prefer to go with the first one, but I can understand if some people would prefer two. What do you think?

Whichever order works for you seems reasonable to me.

llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h

 //===- LoopVectorizationPlanner.h - Planner for LoopVectorization ---------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
public:
 
   /// Finalize the best decision and dispose of all other VPlans.
   void setBestPlan(ElementCount VF, unsigned UF);
 
   /// Generate the IR code for the body of the vectorized loop according to the
   /// best selected VPlan.
   void executePlan(InnerLoopVectorizer &LB, DominatorTree *DT);
 
-  void printPlans(raw_ostream &O) {
-    for (const auto &Plan : VPlans)
-      O << *Plan;
-  }
+  void printPlans(raw_ostream &O);
 
   /// Look through the existing plans and return true if we have one with all
   /// the vectorization factors in question.
   bool hasPlanWithVFs(const ArrayRef<ElementCount> VFs) const {
     return any_of(VPlans, [&](const VPlanPtr &Plan) {
       return all_of(VFs, [&](const ElementCount &VF) {
         return Plan->hasVF(VF);
       });

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

 //===- LoopVectorize.cpp - A Loop Vectorizer ------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 cl::opt<bool> llvm::EnableLoopInterleaving(
     "interleave-loops", cl::init(true), cl::Hidden,
     cl::desc("Enable loop interleaving in Loop vectorization passes"));
 cl::opt<bool> llvm::EnableLoopVectorization(
     "vectorize-loops", cl::init(true), cl::Hidden,
     cl::desc("Run the Loop vectorization passes"));
 
+cl::opt<bool> PrintVPlansInDotFormat(
+    "vplan-print-in-dot-format", cl::init(false), cl::Hidden,
+    cl::desc("Use dot format instead of plain text when dumping VPlans"));
+
 /// A helper function that returns the type of loaded or stored value.
 static Type *getMemInstValueType(Value *I) {
   assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&
          "Expected Load or Store instruction");
   if (auto *LI = dyn_cast<LoadInst>(I))
     return LI->getType();
   return cast<StoreInst>(I)->getValueOperand()->getType();
 }
void LoopVectorizationPlanner::executePlan(InnerLoopVectorizer &ILV,
 
   // 3. Fix the vectorized code: take care of header phi's, live-outs,
   //    predication, updating analyses.
   ILV.fixVectorizedLoop(State);
 
   ILV.printDebugTracesAtEnd();
 }
 
+void LoopVectorizationPlanner::printPlans(raw_ostream &O) {
+  for (const auto &Plan : VPlans)
+    if (PrintVPlansInDotFormat)
+      Plan->printDOT(O);
+    else
+      Plan->print(O);
+}
+
 void LoopVectorizationPlanner::collectTriviallyDeadInstructions(
     SmallPtrSetImpl<Instruction *> &DeadInstructions) {
 
   // We create new control-flow for the vectorized loop, so the original exit
   // conditions will be dead after vectorization if it's only used by the
   // terminator
   SmallVector<BasicBlock*> ExitingBlocks;
   OrigLoop->getExitingBlocks(ExitingBlocks);
for (Instruction *R : ReductionOperations) {
       }
       Chain = R;
     }
   }
 }
 
 void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
                                VPSlotTracker &SlotTracker) const {
-  O << Indent << "\"INTERLEAVE-GROUP with factor " << IG->getFactor() << " at ";
+  O << Indent << "INTERLEAVE-GROUP with factor " << IG->getFactor() << " at ";
   IG->getInsertPos()->printAsOperand(O, false);
   O << ", ";
   getAddr()->printAsOperand(O, SlotTracker);
   VPValue *Mask = getMask();
   if (Mask) {
     O << ", ";
     Mask->printAsOperand(O, SlotTracker);
   }
   for (unsigned i = 0; i < IG->getFactor(); ++i)
     if (Instruction *I = IG->getMember(i))
-      O << "\\l\" +\n" << Indent << "\"  " << VPlanIngredient(I) << " " << i;
+      O << "\n" << Indent << "  " << VPlanIngredient(I) << " " << i;
 }
 
 void VPWidenCallRecipe::execute(VPTransformState &State) {
   State.ILV->widenCallInstruction(*cast<CallInst>(getUnderlyingInstr()), this,
                                   *this, State);
 }
 
 void VPWidenSelectRecipe::execute(VPTransformState &State) {

llvm/lib/Transforms/Vectorize/VPlan.h

 //===- VPlan.h - Represent A Vectorizer Plan --------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
 
   /// Delete all blocks reachable from a given VPBlockBase, inclusive.
   static void deleteCFG(VPBlockBase *Entry);
 
   void printAsOperand(raw_ostream &OS, bool PrintType) const {
     OS << getName();
   }
 
-  void print(raw_ostream &OS) const {
-    // TODO: Only printing VPBB name for now since we only have dot printing
-    // support for VPInstructions/Recipes.
-    printAsOperand(OS, false);
-  }
-
   /// Return true if it is legal to hoist instructions into this block.
   bool isLegalToHoistInto() {
     // There are currently no constraints that prevent an instruction to be
     // hoisted into a VPBlockBase.
     return true;
   }
 
   /// Replace all operands of VPUsers in the block with \p NewValue and also
   /// replaces all uses of VPValues defined in the block with NewValue.
   virtual void dropAllReferences(VPValue *NewValue) = 0;
+
+  /// Print plain-text dump of this VPBlockBase to \p O, prefixing all lines
+  /// with \p Indent. \p SlotTracker is used to print unnamed VPValue's using
+  /// consequtive numbers.
+  ///
+  /// Note that the numbering is applied to the whole VPlan, so printing
+  /// individual blocks is consistent with the whole VPlan printing.
+  virtual void print(raw_ostream &O, const Twine &Indent,
+                     VPSlotTracker &SlotTracker) const = 0;
+
+  /// Print plain-text dump of this VPlan to \p O.
+  void print(raw_ostream &O) const {
+    VPSlotTracker SlotTracker(getPlan());
+    print(O, "", SlotTracker);
+  }
+
+  /// Dump this VPBlockBase to dbgs().
+  void dump() const { print(dbgs()); }
 };
 
 /// VPRecipeBase is a base class modeling a sequence of one or more output IR
 /// instructions. VPRecipeBase owns the the VPValues it defines through VPDef
 /// and is responsible for deleting its defined values. Single-value
 /// VPRecipeBases that also inherit from VPValue must make sure to inherit from
 /// VPRecipeBase before VPValue.
 class VPRecipeBase : public ilist_node_with_parent<VPRecipeBase, VPBasicBlock>,
public:
 
   /// Generate the extraction of the appropriate bit from the block mask and the
   /// conditional branch.
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
   void print(raw_ostream &O, const Twine &Indent,
              VPSlotTracker &SlotTracker) const override {
-    O << " +\n" << Indent << "\"BRANCH-ON-MASK ";
+    O << Indent << "BRANCH-ON-MASK ";
     if (VPValue *Mask = getMask())
       Mask->printAsOperand(O, SlotTracker);
     else
       O << " All-One";
-    O << "\\l\"";
   }
 
   /// Return the mask used by this recipe. Note that a full mask is represented
   /// by a nullptr.
   VPValue *getMask() const {
     assert(getNumOperands() <= 1 && "should have either 0 or 1 operands");
     // Mask is optional.
     return getNumOperands() == 1 ? getOperand(0) : nullptr;
public:
   /// this VPBasicBlock, thereby "executing" the VPlan.
   void execute(struct VPTransformState *State) override;
 
   /// Return the position of the first non-phi node recipe in the block.
   iterator getFirstNonPhi();
 
   void dropAllReferences(VPValue *NewValue) override;
 
+  /// Print this VPBsicBlock to \p O, prefixing all lines with \p Indent. \p
+  /// SlotTracker is used to print unnamed VPValue's using consequtive numbers.
+  ///
+  /// Note that the numbering is applied to the whole VPlan, so printing
+  /// individual blocks is consistent with the whole VPlan printing.
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
+  using VPBlockBase::print; // Get the print(raw_stream &O) version.
+
 private:
   /// Create an IR BasicBlock to hold the output instructions generated by this
   /// VPBasicBlock, and return it. Update the CFGState accordingly.
   BasicBlock *createEmptyBasicBlock(VPTransformState::CFGState &CFG);
 };
 
 /// VPRegionBlock represents a collection of VPBasicBlocks and VPRegionBlocks
 /// which form a Single-Entry-Single-Exit subgraph of the output IR CFG.
public:
   /// instances of output IR corresponding to its VPBlockBases.
   bool isReplicator() const { return IsReplicator; }
 
   /// The method which generates the output IR instructions that correspond to
   /// this VPRegionBlock, thereby "executing" the VPlan.
   void execute(struct VPTransformState *State) override;
 
   void dropAllReferences(VPValue *NewValue) override;
+
+  /// Print this VPRegionBlock to \p O (recursively), prefixing all lines with
+  /// \p Indent. \p SlotTracker is used to print unnamed VPValue's using
+  /// consequtive numbers.
+  ///
+  /// Note that the numbering is applied to the whole VPlan, so printing
+  /// individual regions is consistent with the whole VPlan printing.
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
+  using VPBlockBase::print; // Get the print(raw_stream &O) version.
 };
 
 //===----------------------------------------------------------------------===//
 // GraphTraits specializations for VPlan Hierarchical Control-Flow Graphs     //
 //===----------------------------------------------------------------------===//
 
 // The following set of template specializations implement GraphTraits to treat
 // any VPBlockBase as a node in a graph of VPBlockBases. It's important to note
public:
   }
 
   void removeVPValueFor(Value *V) { Value2VPValue.erase(V); }
 
   /// Return the VPLoopInfo analysis for this VPlan.
   VPLoopInfo &getVPLoopInfo() { return VPLInfo; }
   const VPLoopInfo &getVPLoopInfo() const { return VPLInfo; }
 
+  /// Print this VPlan to \p O.
+  void print(raw_ostream &O) const;
+
+  /// Print this VPlan in DOT format to \p O.
+  void printDOT(raw_ostream &O) const;
+
   /// Dump the plan to stderr (for debugging).
   void dump() const;
 
   /// Returns a range mapping the values the range \p Operands to their
   /// corresponding VPValues.
   iterator_range<mapped_iterator<Use *, std::function<VPValue *(Value *)>>>
   mapToVPValues(User::op_range Operands) {
     std::function<VPValue *(Value *)> Fn = [this](Value *Op) {
       return getOrAddVPValue(Op);
     };
     return map_range(Operands, Fn);
   }
 
 private:
   /// Add to the given dominator tree the header block and every new basic block
   /// that was created between it and the latch block, inclusive.
   static void updateDominatorTree(DominatorTree *DT, BasicBlock *LoopLatchBB,
                                   BasicBlock *LoopPreHeaderBB,
                                   BasicBlock *LoopExitBB);
 };
 
 /// VPlanPrinter prints a given VPlan to a given output stream. The printing is
 /// indented and follows the dot format.
 class VPlanPrinter {
-  friend inline raw_ostream &operator<<(raw_ostream &OS, const VPlan &Plan);
-  friend inline raw_ostream &operator<<(raw_ostream &OS,
-                                        const struct VPlanIngredient &I);
-
-private:
   raw_ostream &OS;
   const VPlan &Plan;
   unsigned Depth = 0;
   unsigned TabWidth = 2;
   std::string Indent;
   unsigned BID = 0;
   SmallDenseMap<const VPBlockBase *, unsigned> BlockID;
 
   VPSlotTracker SlotTracker;
 
-  VPlanPrinter(raw_ostream &O, const VPlan &P)
-      : OS(O), Plan(P), SlotTracker(&P) {}
-
   /// Handle indentation.
   void bumpIndent(int b) { Indent = std::string((Depth += b) * TabWidth, ' '); }
 
   /// Print a given \p Block of the Plan.
   void dumpBlock(const VPBlockBase *Block);
 
   /// Print the information related to the CFG edges going out of a given
   /// \p Block, followed by printing the successor blocks themselves.
class VPlanPrinter {
   const Twine getOrCreateName(const VPBlockBase *Block);
 
   const Twine getUID(const VPBlockBase *Block);
 
   /// Print the information related to a CFG edge between two VPBlockBases.
   void drawEdge(const VPBlockBase *From, const VPBlockBase *To, bool Hidden,
                 const Twine &Label);
 
-  void dump();
+public:
+  VPlanPrinter(raw_ostream &O, const VPlan &P)
+      : OS(O), Plan(P), SlotTracker(&P) {}
 
-  static void printAsIngredient(raw_ostream &O, const Value *V);
+  void dump();
 };
 
 struct VPlanIngredient {
   const Value *V;
 
   VPlanIngredient(const Value *V) : V(V) {}
+
+  void print(raw_ostream &O) const;
 };
 
 inline raw_ostream &operator<<(raw_ostream &OS, const VPlanIngredient &I) {
-  VPlanPrinter::printAsIngredient(OS, I.V);
+  I.print(OS);
   return OS;
 }
 
 inline raw_ostream &operator<<(raw_ostream &OS, const VPlan &Plan) {
-  VPlanPrinter Printer(OS, Plan);
-  Printer.dump();
+  Plan.print(OS);
   return OS;
 }
 
 //===----------------------------------------------------------------------===//
 // VPlan Utilities
 //===----------------------------------------------------------------------===//
 
 /// Class that provides utilities for VPBlockBases in VPlan.

llvm/lib/Transforms/Vectorize/VPlan.cpp

 //===- VPlan.cpp - Vectorizer Plan ----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///

 #include <string>
 #include <vector>
 
 using namespace llvm;
 extern cl::opt<bool> EnableVPlanNativePath;
 
 #define DEBUG_TYPE "vplan"
 
 raw_ostream &llvm::operator<<(raw_ostream &OS, const VPValue &V) {
   const VPInstruction *Instr = dyn_cast<VPInstruction>(&V);
   VPSlotTracker SlotTracker(
       (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
   V.print(OS, SlotTracker);
   return OS;
 }
 
 VPValue::VPValue(const unsigned char SC, Value *UV, VPDef *Def)
for (VPRecipeBase &R : Recipes) {
     for (auto *Def : R.definedValues())
       Def->replaceAllUsesWith(NewValue);
 
     for (unsigned I = 0, E = R.getNumOperands(); I != E; I++)
       R.setOperand(I, NewValue);
   }
 }
 
+void VPBasicBlock::print(raw_ostream &O, const Twine &Indent,
+                         VPSlotTracker &SlotTracker) const {
+  O << Indent << getName() << ":\n";
+  if (const VPValue *Pred = getPredicate()) {
+    O << Indent << "BlockPredicate:";
+    Pred->printAsOperand(O, SlotTracker);
+    if (const auto *PredInst = dyn_cast<VPInstruction>(Pred))
+      O << " (" << PredInst->getParent()->getName() << ")";
+    O << '\n';
+  }
+
+  auto RecipeIndent = Indent + "  ";
+  for (const VPRecipeBase &Recipe : *this) {
+    Recipe.print(O, RecipeIndent, SlotTracker);
+    O << '\n';
+  }
+
+  if (getSuccessors().empty()) {
+    O << Indent << "No successors\n";
+  } else {
+    O << Indent << "Successor(s): ";
+    ListSeparator LS;
+    for (auto *Succ : getSuccessors())
+      O << LS << Succ->getName();
+    O << '\n';
+  }
+
+  if (const VPValue *CBV = getCondBit()) {
+    O << Indent << "CondBit: ";
+    CBV->printAsOperand(O, SlotTracker);
+    if (const auto *CBI = dyn_cast<VPInstruction>(CBV))
+      O << " (" << CBI->getParent()->getName() << ")";
+    O << '\n';
+  }
+}
+
 void VPRegionBlock::dropAllReferences(VPValue *NewValue) {
   for (VPBlockBase *Block : depth_first(Entry))
     // Drop all references in VPBasicBlocks and replace all uses with
     // DummyValue.
     Block->dropAllReferences(NewValue);
 }
 
 void VPRegionBlock::execute(VPTransformState *State) {
for (unsigned Lane = 0, VF = State->VF.getKnownMinValue(); Lane < VF;
       }
     }
   }
 
   // Exit replicating mode.
   State->Instance.reset();
 }
 
+void VPRegionBlock::print(raw_ostream &O, const Twine &Indent,
+                          VPSlotTracker &SlotTracker) const {
+  O << Indent << (isReplicator() ? "<xVFxUF> " : "<x1> ") << getName() << ": {";
+  auto NewIndent = Indent + "  ";
+  for (auto *BlockBase : depth_first(Entry)) {
+    O << '\n';
+    BlockBase->print(O, NewIndent, SlotTracker);
+  }
+  O << Indent << "}\n";
+}
+
 void VPRecipeBase::insertBefore(VPRecipeBase *InsertPos) {
   assert(!Parent && "Recipe already in some VPBasicBlock");
   assert(InsertPos->getParent() &&
          "Insertion position not in any VPBasicBlock");
   Parent = InsertPos->getParent();
   Parent->getRecipeList().insert(InsertPos->getIterator(), this);
 }
 
 void VPRecipeBase::insertAfter(VPRecipeBase *InsertPos) {
   assert(!Parent && "Recipe already in some VPBasicBlock");
   assert(InsertPos->getParent() &&
          "Insertion position not in any VPBasicBlock");
   Parent = InsertPos->getParent();
   Parent->getRecipeList().insertAfter(InsertPos->getIterator(), this);
 }
 
void VPlan::execute(VPTransformState *State) {
   // We do not attempt to preserve DT for outer loop vectorization currently.
   if (!EnableVPlanNativePath)
     updateDominatorTree(State->DT, VectorPreHeaderBB, VectorLatchBB,
                         L->getExitBlock());
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
-void VPlan::dump() const { dbgs() << *this << '\n'; }
+void VPlan::print(raw_ostream &O) const {
+  VPSlotTracker SlotTracker(this);
+
+  O << "VPlan {";
+  for (const VPBlockBase *Block : depth_first(getEntry())) {
+    O << '\n';
+    Block->print(O, "", SlotTracker);
+  }
+  O << "}\n";
+}
+
+LLVM_DUMP_METHOD
+void VPlan::printDOT(raw_ostream &O) const {
+  VPlanPrinter Printer(O, *this);
+  Printer.dump();
+}
+
+LLVM_DUMP_METHOD
+void VPlan::dump() const { print(dbgs()); }
 #endif
 
 void VPlan::updateDominatorTree(DominatorTree *DT, BasicBlock *LoopPreHeaderBB,
                                 BasicBlock *LoopLatchBB,
                                 BasicBlock *LoopExitBB) {
   BasicBlock *LoopHeaderBB = LoopPreHeaderBB->getSingleSuccessor();
   assert(LoopHeaderBB && "Loop preheader does not have a single successor.");
   // The vector body may be more than a single basic-block by this point.
void VPlanPrinter::dumpEdges(const VPBlockBase *Block) {
   } else {
     unsigned SuccessorNumber = 0;
     for (auto *Successor : Successors)
       drawEdge(Block, Successor, false, Twine(SuccessorNumber++));
   }
 }
 
 void VPlanPrinter::dumpBasicBlock(const VPBasicBlock *BasicBlock) {
+  // Implement dot-formatted dump by performing plain-text dump into the
+  // temporary storage followed by some post-processing.
   OS << Indent << getUID(BasicBlock) << " [label =\n";
   bumpIndent(1);
-  OS << Indent << "\"" << DOT::EscapeString(BasicBlock->getName()) << ":\\n\"";
-  bumpIndent(1);
+  std::string Str;
+  raw_string_ostream SS(Str);
+  // Use no indentation as we need to wrap the lines into quotes ourselves.
+  BasicBlock->print(SS, "", SlotTracker);
+
+  // We need to process each line of the output separately, so split
+  // single-string plain-text dump.
+  SmallVector<StringRef, 0> Lines;
+  StringRef(Str).rtrim('\n').split(Lines, "\n");
+
+  auto EmitLine = [&](StringRef Line, StringRef Suffix) {
+    OS << Indent << '"' << DOT::EscapeString(Line.str()) << "\\l\"" << Suffix;
+  };
+
+  // Don't need the "+" after the last line.
+  for (auto Line : make_range(Lines.begin(), Lines.end() - 1))
+    EmitLine(Line, " +\n");
+  EmitLine(Lines.back(), "\n");
 
-  // Dump the block predicate.
-  const VPValue *Pred = BasicBlock->getPredicate();
-  if (Pred) {
-    OS << " +\n" << Indent << " \"BlockPredicate: \"";
-    if (const VPInstruction *PredI = dyn_cast<VPInstruction>(Pred)) {
-      PredI->printAsOperand(OS, SlotTracker);
-      OS << " (" << DOT::EscapeString(PredI->getParent()->getName())
-         << ")\\l\"";
-    } else
-      Pred->printAsOperand(OS, SlotTracker);
-  }
-
-  for (const VPRecipeBase &Recipe : *BasicBlock) {
-    OS << " +\n" << Indent << "\"";
-    // Don't indent inside the recipe printer as we printed it before the
-    // opening quote already.
-    Recipe.print(OS, "", SlotTracker);
-    OS << "\\l\"";
-  }
-
-  // Dump the condition bit.
-  const VPValue *CBV = BasicBlock->getCondBit();
-  if (CBV) {
-    OS << " +\n" << Indent << " \"CondBit: ";
-    if (const VPInstruction *CBI = dyn_cast<VPInstruction>(CBV)) {
-      CBI->printAsOperand(OS, SlotTracker);
-      OS << " (" << DOT::EscapeString(CBI->getParent()->getName()) << ")\\l\"";
-    } else {
-      CBV->printAsOperand(OS, SlotTracker);
-      OS << "\"";
-    }
-  }
+  bumpIndent(-1);
+  OS << Indent << "]\n";
 
-  bumpIndent(-2);
-  OS << "\n" << Indent << "]\n";
   dumpEdges(BasicBlock);
 }
 
 void VPlanPrinter::dumpRegion(const VPRegionBlock *Region) {
   OS << Indent << "subgraph " << getUID(Region) << " {\n";
   bumpIndent(1);
   OS << Indent << "fontname=Courier\n"
      << Indent << "label=\""
      << DOT::EscapeString(Region->isReplicator() ? "<xVFxUF> " : "<x1> ")
      << DOT::EscapeString(Region->getName()) << "\"\n";
   // Dump the blocks of the region.
   assert(Region->getEntry() && "Region contains no inner blocks.");
   for (const VPBlockBase *Block : depth_first(Region->getEntry()))
     dumpBlock(Block);
   bumpIndent(-1);
   OS << Indent << "}\n";
   dumpEdges(Region);
 }
 
-void VPlanPrinter::printAsIngredient(raw_ostream &O, const Value *V) {
-  std::string IngredientString;
-  raw_string_ostream RSO(IngredientString);
+void VPlanIngredient::print(raw_ostream &O) const {
   if (auto *Inst = dyn_cast<Instruction>(V)) {
     if (!Inst->getType()->isVoidTy()) {
-      Inst->printAsOperand(RSO, false);
-      RSO << " = ";
+      Inst->printAsOperand(O, false);
+      O << " = ";
     }
-    RSO << Inst->getOpcodeName() << " ";
+    O << Inst->getOpcodeName() << " ";
     unsigned E = Inst->getNumOperands();
     if (E > 0) {
-      Inst->getOperand(0)->printAsOperand(RSO, false);
+      Inst->getOperand(0)->printAsOperand(O, false);
       for (unsigned I = 1; I < E; ++I)
-        Inst->getOperand(I)->printAsOperand(RSO << ", ", false);
+        Inst->getOperand(I)->printAsOperand(O << ", ", false);
     }
   } else // !Inst
-    V->printAsOperand(RSO, false);
-  RSO.flush();
-  O << DOT::EscapeString(IngredientString);
+    V->printAsOperand(O, false);
 }
 
 void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent,
                               VPSlotTracker &SlotTracker) const {
   O << Indent << "WIDEN-CALL ";
 
   auto *CI = cast<CallInst>(getUnderlyingInstr());
   if (CI->getType()->isVoidTy())
     O << "void ";
   else {
     printAsOperand(O, SlotTracker);
     O << " = ";
   }

llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll

for.body:
   br i1 %cond, label %for.body, label %for.end
 
 for.end:
   %tmp4 = phi i32 [ %tmp3, %for.body ]
   ret i32 %tmp4
 }
 
 ; Check for crash exposed by D76992.
-; CHECK:       N0 [label =
-; CHECK-NEXT:    "loop:\n" +
-; CHECK-NEXT:      "WIDEN-INDUCTION %iv = phi 0, %iv.next\l" +
-; CHECK-NEXT:      "WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>\l" +
-; CHECK-NEXT:      "WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>\l"
-; CHECK-NEXT:  ]
+; CHECK:      VPlan {
+; CHECK-NEXT: loop:
+; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
+; CHECK-NEXT:   WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>
+; CHECK-NEXT:   WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
+; CHECK-NEXT: No successor
+; CHECK-NEXT: }
 define void @test() {
 entry:
   br label %loop
 
 loop:                       ; preds = %loop, %entry
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
   %cond0 = icmp ult i64 %iv, 13
   %s = select i1 %cond0, i32 10, i32 20
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 14
   br i1 %exitcond, label %exit, label %loop
 
 exit:           ; preds = %loop
   ret void
 }

llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll

+; REQUIRES: asserts
+
+; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -vplan-print-in-dot-format -disable-output %s 2>&1 | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; Verify that -vplan-print-in-dot-format option works.
+
+define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
+; CHECK:       N0 [label =
+; CHECK-NEXT:    "for.body:\l" +
+; CHECK-NEXT:    "  WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
+; CHECK-NEXT:    "  CLONE ir\<%arrayidx\> = getelementptr ir\<%y\>, ir\<%iv\>\l" +
+; CHECK-NEXT:    "  WIDEN ir\<%lv\> = load ir\<%arrayidx\>\l" +
+; CHECK-NEXT:    "  WIDEN-CALL ir\<%call\> = call @llvm.sqrt.f32(ir\<%lv\>)\l" +
+; CHECK-NEXT:    "  CLONE ir\<%arrayidx2\> = getelementptr ir\<%x\>, ir\<%iv\>\l" +
+; CHECK-NEXT:    "  WIDEN store ir\<%arrayidx2\>, ir\<%call\>\l" +
+; CHECK-NEXT:    "No successors\l"
+; CHECK-NEXT:  ]
+;
+entry:
+  %cmp6 = icmp sgt i64 %n, 0
+  br i1 %cmp6, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %y, i64 %iv
+  %lv = load float, float* %arrayidx, align 4
+  %call = tail call float @llvm.sqrt.f32(float %lv) nounwind readnone
+  %arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv
+  store float %call, float* %arrayidx2, align 4
+  %iv.next = add i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+declare float @llvm.sqrt.f32(float) nounwind readnone

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

 ; REQUIRES: asserts
 
 ; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 ; Tests for printing VPlans.
 
 define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
-; CHECK: N0 [label =
-; CHECK-NEXT: "for.body:\n" +
-; CHECK-NEXT:       "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
-; CHECK-NEXT:       "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
-; CHECK-NEXT:       "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
-; CHECK-NEXT:       "WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>)\l" +
-; CHECK-NEXT:       "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" +
-; CHECK-NEXT:       "WIDEN store ir<%arrayidx2>, ir<%call>\l"
-; CHECK-NEXT:   ]
-
+; CHECK:      VPlan {
+; CHECK-NEXT: for.body:
+; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi %iv.next, 0
+; CHECK-NEXT:   CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
+; CHECK-NEXT:   WIDEN ir<%lv> = load ir<%arrayidx>
+; CHECK-NEXT:   WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>)
+; CHECK-NEXT:   CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>
+; CHECK-NEXT:   WIDEN store ir<%arrayidx2>, ir<%call>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+;
 entry:
   %cmp6 = icmp sgt i64 %n, 0
   br i1 %cmp6, label %for.body, label %for.end
 
 for.body:                                         ; preds = %entry, %for.body
   %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds float, float* %y, i64 %iv
   %lv = load float, float* %arrayidx, align 4
   %call = tail call float @llvm.sqrt.f32(float %lv) nounwind readnone
   %arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv
   store float %call, float* %arrayidx2, align 4
   %iv.next = add i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 define void @print_widen_gep_and_select(i64 %n, float* noalias %y, float* noalias %x, float* %z) nounwind uwtable {
-; CHECK: N0 [label =
-; CHECK-NEXT: "for.body:\n" +
-; CHECK-NEXT:      "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
-; CHECK-NEXT:      "WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
-; CHECK-NEXT:      "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
-; CHECK-NEXT:      "WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>\l" +
-; CHECK-NEXT:      "WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>\l" +
-; CHECK-NEXT:      "WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>\l" +
-; CHECK-NEXT:      "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" +
-; CHECK-NEXT:      "WIDEN store ir<%arrayidx2>, ir<%add>\l"
-; CHECK-NEXT:   ]
-
+; CHECK:      VPlan {
+; CHECK-NEXT: for.body:
+; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi %iv.next, 0
+; CHECK-NEXT:   WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
+; CHECK-NEXT:   WIDEN ir<%lv> = load ir<%arrayidx>
+; CHECK-NEXT:   WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>
+; CHECK-NEXT:   WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>
+; CHECK-NEXT:   WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>
+; CHECK-NEXT:   CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>
+; CHECK-NEXT:   WIDEN store ir<%arrayidx2>, ir<%add>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+;
 entry:
   %cmp6 = icmp sgt i64 %n, 0
   br i1 %cmp6, label %for.body, label %for.end
 
 for.body:                                         ; preds = %entry, %for.body
   %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds float, float* %y, i64 %iv
   %lv = load float, float* %arrayidx, align 4
   %cmp = icmp eq float* %arrayidx, %z
   %sel = select i1 %cmp, float 10.0, float 20.0
   %add = fadd float %lv, %sel
   %arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv
   store float %add, float* %arrayidx2, align 4
   %iv.next = add i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 define float @print_reduction(i64 %n, float* noalias %y) {
-; CHECK: N0 [label =
-; CHECK-NEXT: "for.body:\n" +
-; CHECK-NEXT:       "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
-; CHECK-NEXT:       "WIDEN-PHI %red = phi %red.next, 0.000000e+00\l" +
-; CHECK-NEXT:       "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
-; CHECK-NEXT:       "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
-; CHECK-NEXT:       "REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)\l"
-; CHECK-NEXT:   ]
-
+; CHECK:      VPlan {
+; CHECK-NEXT: for.body:
+; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi %iv.next, 0
+; CHECK-NEXT:   WIDEN-PHI %red = phi %red.next, 0.000000e+00
+; CHECK-NEXT:   CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
+; CHECK-NEXT:   WIDEN ir<%lv> = load ir<%arrayidx>
+; CHECK-NEXT:   REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+;
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.body
   %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
   %red = phi float [ %red.next, %for.body ], [ 0.0, %entry ]
   %arrayidx = getelementptr inbounds float, float* %y, i64 %iv
   %lv = load float, float* %arrayidx, align 4
   %red.next = fadd fast float %lv, %red
   %iv.next = add i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret float %red.next
 }
 
 define void @print_replicate_predicated_phi(i64 %n, i64* %x) {
-; CHECK:       N0 [label =
-; CHECK-NEXT:    "for.body:\n" +
-; CHECK-NEXT:      "WIDEN-INDUCTION %i = phi 0, %i.next\l" +
-; CHECK-NEXT:      "WIDEN ir<%cmp> = icmp ir<%i>, ir<5>\l"
-; CHECK-NEXT:  ]
-;
-; CHECK:       N2 [label =
-; CHECK-NEXT:    "pred.udiv.entry:\n" +
-; CHECK-NEXT:      +
-; CHECK-NEXT:      "BRANCH-ON-MASK ir<%cmp>\l"\l
-; CHECK-NEXT:         "CondBit: ir<%cmp>"
-; CHECK-NEXT:    ]
-;
-; CHECK:       N4 [label =
-; CHECK-NEXT:    "pred.udiv.if:\n" +
-; CHECK-NEXT:      "REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V)\l"
-; CHECK-NEXT:  ]
-;
-; CHECK:       N5 [label =
-; CHECK-NEXT:    "pred.udiv.continue:\n" +
-; CHECK-NEXT:      "PHI-PREDICATED-INSTRUCTION vp<%3> = ir<%tmp4>\l"
-; CHECK-NEXT:  ]
-;
-; CHECK:       N7 [label =
-; CHECK-NEXT:    "for.inc:\n" +
-; CHECK-NEXT:      "EMIT vp<%4> = not ir<%cmp>\l" +
-; CHECK-NEXT:      "BLEND %d = ir<0>/vp<%4> vp<%3>/ir<%cmp>\l" +
-; CHECK-NEXT:      "CLONE ir<%idx> = getelementptr ir<%x>, ir<%i>\l" +
-; CHECK-NEXT:      "WIDEN store ir<%idx>, ir<%d>\l"
-; CHECK-NEXT:  ]
+; CHECK:      VPlan {
+; CHECK-NEXT: for.body:
+; CHECK-NEXT:   WIDEN-INDUCTION %i = phi 0, %i.next
+; CHECK-NEXT:   WIDEN ir<%cmp> = icmp ir<%i>, ir<5>
+; CHECK-NEXT: Successor(s): if.then
+; CHECK-EMPTY:
+; CHECK-NEXT: if.then:
+; CHECK-NEXT: Successor(s): pred.udiv
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.udiv: {
+; CHECK-NEXT:   pred.udiv.entry:
+; CHECK-NEXT:     BRANCH-ON-MASK ir<%cmp>
+; CHECK-NEXT:   Successor(s): pred.udiv.if, pred.udiv.continue
+; CHECK-NEXT:   CondBit: ir<%cmp>
+; CHECK-EMPTY:
+; CHECK-NEXT:   pred.udiv.if:
+; CHECK-NEXT:     REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V)
+; CHECK-NEXT:   Successor(s): pred.udiv.continue
+; CHECK-EMPTY:
+; CHECK-NEXT:   pred.udiv.continue:
+; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<%3> = ir<%tmp4>
+; CHECK-NEXT:   No successors
+; CHECK-NEXT: }
+; CHECK-EMPTY:
+; CHECK-NEXT: if.then.0:
+; CHECK-NEXT: Successor(s): for.inc
+; CHECK-EMPTY:
+; CHECK-NEXT: for.inc:
+; CHECK-NEXT:   EMIT vp<%4> = not ir<%cmp>
+; CHECK-NEXT:   BLEND %d = ir<0>/vp<%4> vp<%3>/ir<%cmp>
+; CHECK-NEXT:   CLONE ir<%idx> = getelementptr ir<%x>, ir<%i>
+; CHECK-NEXT:   WIDEN store ir<%idx>, ir<%d>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
 ;
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.inc, %entry
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %cmp = icmp ult i64 %i, 5
   br i1 %cmp, label %if.then, label %for.inc

llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp

 //===- llvm/unittest/Transforms/Vectorize/VPlanHCFGTest.cpp ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoop) {
   EXPECT_EQ(2u, ICmp->getNumOperands());
   EXPECT_EQ(IndvarAdd, ICmp->getOperand(0));
   EXPECT_EQ(VecBB->getCondBit(), ICmp);
 
   // Add an external value to check we do not print the list of external values,
   // as this is not required with the new printing.
   Plan->addVPValue(&*F->arg_begin());
   std::string FullDump;
-  raw_string_ostream(FullDump) << *Plan;
+  raw_string_ostream OS(FullDump);
+  Plan->printDOT(OS);
   const char *ExpectedStr = R"(digraph VPlan {
 graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
 node [shape=rect, fontname=Courier, fontsize=30]
 edge [fontname=Courier, fontsize=30]
 compound=true
   subgraph cluster_N0 {
     fontname=Courier
     label="\<x1\> TopRegion"
     N1 [label =
-      "entry:\n"
+      "entry:\l" +
+      "Successor(s): for.body\l"
     ]
     N1 -> N2 [ label=""]
     N2 [label =
-      "for.body:\n" +
-        "WIDEN-PHI %indvars.iv = phi 0, %indvars.iv.next\l" +
-        "EMIT ir<%arr.idx> = getelementptr ir<%A> ir<%indvars.iv>\l" +
-        "EMIT ir<%l1> = load ir<%arr.idx>\l" +
-        "EMIT ir<%res> = add ir<%l1> ir<10>\l" +
-        "EMIT store ir<%res> ir<%arr.idx>\l" +
-        "EMIT ir<%indvars.iv.next> = add ir<%indvars.iv> ir<1>\l" +
-        "EMIT ir<%exitcond> = icmp ir<%indvars.iv.next> ir<%N>\l" +
-         "CondBit: ir<%exitcond> (for.body)\l"
+      "for.body:\l" +
+      "  WIDEN-PHI %indvars.iv = phi 0, %indvars.iv.next\l" +
+      "  EMIT ir\<%arr.idx\> = getelementptr ir\<%A\> ir\<%indvars.iv\>\l" +
+      "  EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" +
+      "  EMIT ir\<%res\> = add ir\<%l1\> ir\<10\>\l" +
+      "  EMIT store ir\<%res\> ir\<%arr.idx\>\l" +
+      "  EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\> ir\<1\>\l" +
+      "  EMIT ir\<%exitcond\> = icmp ir\<%indvars.iv.next\> ir\<%N\>\l" +
+      "Successor(s): for.body, for.end\l" +
+      "CondBit: ir\<%exitcond\> (for.body)\l"
     ]
     N2 -> N2 [ label="T"]
     N2 -> N3 [ label="F"]
     N3 [label =
-      "for.end:\n" +
-        "EMIT ret\l"
+      "for.end:\l" +
+      "  EMIT ret\l" +
+      "No successors\l"
     ]
   }
 }
 )";
   EXPECT_EQ(ExpectedStr, FullDump);
 
   LoopVectorizationLegality::InductionList Inductions;
   SmallPtrSet<Instruction *, 1> DeadInstructions;

llvm/unittests/Transforms/Vectorize/VPlanTest.cpp

 //===- llvm/unittests/Transforms/Vectorize/VPlanTest.cpp - VPlan tests ----===//
 //
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
TEST(VPBasicBlockTest, print) {
   VPInstruction *I1 = new VPInstruction(Instruction::Add, {});
   VPInstruction *I2 = new VPInstruction(Instruction::Sub, {I1});
   VPInstruction *I3 = new VPInstruction(Instruction::Br, {I1, I2});
 
   VPBasicBlock *VPBB1 = new VPBasicBlock();
   VPBB1->appendRecipe(I1);
   VPBB1->appendRecipe(I2);
   VPBB1->appendRecipe(I3);
+  VPBB1->setName("bb1");
 
   VPInstruction *I4 = new VPInstruction(Instruction::Mul, {I2, I1});
   VPInstruction *I5 = new VPInstruction(Instruction::Ret, {I4});
   VPBasicBlock *VPBB2 = new VPBasicBlock();
   VPBB2->appendRecipe(I4);
   VPBB2->appendRecipe(I5);
+  VPBB2->setName("bb2");
 
   VPBlockUtils::connectBlocks(VPBB1, VPBB2);
 
   // Check printing an instruction without associated VPlan.
   {
     std::string I3Dump;
     raw_string_ostream OS(I3Dump);
     VPSlotTracker SlotTracker;
     I3->print(OS, "", SlotTracker);
     OS.flush();
     EXPECT_EQ("EMIT br <badref> <badref>", I3Dump);
   }
 
   VPlan Plan;
   Plan.setEntry(VPBB1);
   std::string FullDump;
-  raw_string_ostream(FullDump) << Plan;
+  raw_string_ostream OS(FullDump);
+  Plan.printDOT(OS);
 
   const char *ExpectedStr = R"(digraph VPlan {
 graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
 node [shape=rect, fontname=Courier, fontsize=30]
 edge [fontname=Courier, fontsize=30]
 compound=true
   N0 [label =
-    ":\n" +
-      "EMIT vp<%0> = add\l" +
-      "EMIT vp<%1> = sub vp<%0>\l" +
-      "EMIT br vp<%0> vp<%1>\l"
+    "bb1:\l" +
+    "  EMIT vp\<%0\> = add\l" +
+    "  EMIT vp\<%1\> = sub vp\<%0\>\l" +
+    "  EMIT br vp\<%0\> vp\<%1\>\l" +
+    "Successor(s): bb2\l"
   ]
   N0 -> N1 [ label=""]
   N1 [label =
-    ":\n" +
-      "EMIT vp<%3> = mul vp<%1> vp<%0>\l" +
-      "EMIT ret vp<%3>\l"
+    "bb2:\l" +
+    "  EMIT vp\<%3\> = mul vp\<%1\> vp\<%0\>\l" +
+    "  EMIT ret vp\<%3\>\l" +
+    "No successors\l"
   ]
 }
 )";
   EXPECT_EQ(ExpectedStr, FullDump);
 
+  const char *ExpectedBlock1Str = R"(bb1:
+  EMIT vp<%0> = add
+  EMIT vp<%1> = sub vp<%0>
+  EMIT br vp<%0> vp<%1>
+Successor(s): bb2
+)";
+  std::string Block1Dump;
+  raw_string_ostream OS1(Block1Dump);
+  VPBB1->print(OS1);
+  EXPECT_EQ(ExpectedBlock1Str, Block1Dump);
+
+  // Ensure that numbering is good when dumping the second block in isolation.
+  const char *ExpectedBlock2Str = R"(bb2:
+  EMIT vp<%3> = mul vp<%1> vp<%0>
+  EMIT ret vp<%3>
+No successors
+)";
+  std::string Block2Dump;
+  raw_string_ostream OS2(Block2Dump);
+  VPBB2->print(OS2);
+  EXPECT_EQ(ExpectedBlock2Str, Block2Dump);
+
   {
     std::string I3Dump;
     raw_string_ostream OS(I3Dump);
     VPSlotTracker SlotTracker(&Plan);
     I3->print(OS, "", SlotTracker);
     OS.flush();
     EXPECT_EQ("EMIT br vp<%0> vp<%1>", I3Dump);
   }