Page MenuHomePhabricator

Ayal (Ayal Zaks)
User

Projects

User does not belong to any projects.

User Details

User Since
Jul 12 2015, 1:48 PM (310 w, 1 d)

Recent Activity

Today

Ayal added a comment to D104603: [LV] Fix crash when target instruction for sinking is dead..

Ahh, the culprit here is a chain of FOR phi-users all sinking after a Previous - the latter should never be dead, but any member of the chain may by dead.
In the test case: %rec.2 is the FOR phi, %rec.2.prev is Previous, and {%cmp, %C, %B2} is the chain of users, where %B2 is dead as it feeds the loop's conditional branch only.

Mon, Jun 21, 7:15 AM · Restricted Project

Yesterday

Ayal added inline comments to D100260: [VPlan] Merge predicated-triangle regions, after sinking..
Sun, Jun 20, 12:48 PM · Restricted Project

Wed, Jun 16

Ayal accepted D104188: [VPlan] Support PHIs as LastInst when inserting scalars in ::get()..

Good catch! Please remember to add a testcase along with D100260.

Wed, Jun 16, 1:35 PM · Restricted Project
Ayal added inline comments to D103514: [LV] Support sinking recipe in replicate region after another region..
Wed, Jun 16, 1:26 PM · Restricted Project

Tue, Jun 15

Ayal added inline comments to D104197: [VPlan] Track both incoming values for first-order recurrence phis..
Tue, Jun 15, 11:53 PM · Restricted Project
Ayal added a comment to D100260: [VPlan] Merge predicated-triangle regions, after sinking..

This looks good to me, adding final minor nits.

Tue, Jun 15, 12:12 AM · Restricted Project

Thu, Jun 10

Ayal added a comment to D103514: [LV] Support sinking recipe in replicate region after another region..

Minor comments and suggestions. This should compete the handling of sinking a recipe after another, thanks!

Thu, Jun 10, 6:47 AM · Restricted Project

Wed, Jun 9

Ayal added inline comments to D103255: [LV] Mark increment of main vector loop induction variable as NUW..
Wed, Jun 9, 3:03 PM · Restricted Project
Ayal added a comment to D75746: [LoopVectorizer] Simplify branch in the remainder loop for trivial cases.
Wed, Jun 9, 2:30 PM · Restricted Project

Mon, Jun 7

Ayal added inline comments to D103700: [LV] Fix bug when unrolling (only) a loop with non-latch exit.
Mon, Jun 7, 3:05 PM · Restricted Project

Sun, Jun 6

Ayal added inline comments to D103700: [LV] Fix bug when unrolling (only) a loop with non-latch exit.
Sun, Jun 6, 11:55 AM · Restricted Project

Thu, May 27

Ayal accepted D84951: [LV] Try to sink users recursively for first-order recurrences..

This looks good to me, thanks!
Title might emphasize "[LV] Try to sink multiple users ..."
Noting another couple of TODO thoughts.

Thu, May 27, 9:23 AM · Restricted Project
Ayal added inline comments to D84951: [LV] Try to sink users recursively for first-order recurrences..
Thu, May 27, 3:07 AM · Restricted Project

Wed, May 26

Ayal added inline comments to D84951: [LV] Try to sink users recursively for first-order recurrences..
Wed, May 26, 2:38 PM · Restricted Project
Ayal added inline comments to D84951: [LV] Try to sink users recursively for first-order recurrences..
Wed, May 26, 8:06 AM · Restricted Project
Ayal added inline comments to D100260: [VPlan] Merge predicated-triangle regions, after sinking..
Wed, May 26, 1:21 AM · Restricted Project

Tue, May 25

Ayal added a comment to D84951: [LV] Try to sink users recursively for first-order recurrences..

The instructions to sink reside inside the header block in the desired order. It should be possible to traverse them, once, from the FOR phi to the terminator or Previous, w/o sorting nor changing order, by maintaining the set of phi's (direct and indirect) users. When encountering such a user during the traversal, check if it is sunkable, append it to be moved after the last sunken user (or after Previous if this is the first user being sunk), and add its users to the set - those that belong to the header block, others need to be dominated by (and distinct from) Previous.
Perhaps this would also help support sinking memory instructions in the future.
Sounds reasonable?

IIUC your suggestion would require to iterate over the instructions in the header block compared to just traversing the def-use chains from the PHI we are analyzing as we do at the moment? That would work, as we would visit the candidates in the correct order. But requiring to potentially iterate over all instructions in the header block might be worse in practice than sorting the (probably few) instructions that require sinking?

It will be indeed required once we want to sink memory operations, but until then it seems to me that just traversing the def-use chains + sorting would probably be less work in general for the cases we currently support (also given the interface that requires us to analyze each FOR separately). Please let me know if I understood correctly. Happy to update the patch as suggested if you think it's beneficial on its own.

Tue, May 25, 11:46 PM · Restricted Project

Mon, May 24

Ayal added inline comments to D94892: [LV] Unconditionally branch from middle to scalar preheader if the scalar loop must execute.
Mon, May 24, 7:27 AM · Restricted Project
Ayal accepted D100258: [VPlan] Add first VPlan version of sinkScalarOperands..

Looks good to me, thanks!

Mon, May 24, 2:28 AM · Restricted Project

Sun, May 23

Ayal added a comment to D100258: [VPlan] Add first VPlan version of sinkScalarOperands..

Thanks for the changes!
Few remaining nits.

Sun, May 23, 1:41 PM · Restricted Project
Ayal added a comment to D84951: [LV] Try to sink users recursively for first-order recurrences..

Rebased, update to also avoid sinking instructions that may read from memory, as we cannot move them over ones with side-effects, move sort to isFirstOrderRecurrence.

How about making SinkAfter a MapVector instead of DenseMap (to have its iteration order match insertion order) and insert interdependent sink candidates in the desired order?
How about traversing all insns from phi to previous, in order, checking if any is using the phi or a prior insn that was sunk? E.g., by maintaining the set of their users.
This might be clearer, and avoid the sorting.

I'm not sure if it is possible to maintain the order by dominance in the map as we go along, because we an instruction could be used by multiple others and we may visit them in reverse dominance order (relative to each other), so we would miss the fact we need to 'fix' the order of the first instruction. I think it is also difficult & expensive to change the order of multiple entries in the map vector.

I added a few more interesting scenarios as tests in 68d52f0dbe2e and c62f984814c4.

I *think* however it should be enough to sort only sort the instructions to sink per FOR phi, as we currently allow sinking for each instruction only once. That should certainly be better, as we have less to sort overall and everything is contained in IVDescriptor.cpp. The new code already maintains a vector of instructions to sink, so the sort fits in quite nicely. WDYT?

Sun, May 23, 12:49 PM · Restricted Project
Ayal added a comment to D100260: [VPlan] Merge predicated-triangle regions, after sinking..

Nice optimization exercising VPlan capabilities!
Should always be a win, so ok to avoid cost-model considerations, although cost improvement is left unaccounted for.
An alternative may be to try and build larger replicating regions to begin with, but sinkScalarOperands may contribute as well.

Sun, May 23, 1:26 AM · Restricted Project

May 22 2021

Ayal added inline comments to D100258: [VPlan] Add first VPlan version of sinkScalarOperands..
May 22 2021, 1:51 PM · Restricted Project

May 12 2021

Ayal added a comment to D84951: [LV] Try to sink users recursively for first-order recurrences..

How about making SinkAfter a MapVector instead of DenseMap (to have its iteration order match insertion order) and insert interdependent sink candidates in the desired order?
How about traversing all insns from phi to previous, in order, checking if any is using the phi or a prior insn that was sunk? E.g., by maintaining the set of their users.
This might be clearer, and avoid the sorting.

May 12 2021, 5:34 AM · Restricted Project

May 10 2021

Ayal added inline comments to D100102: [VPlan] Use incoming VPValue to detect in-loop reductions (NFC)..
May 10 2021, 3:04 AM · Restricted Project

May 5 2021

Ayal added inline comments to D100751: [VPlan] Properly handle sinking of replicate regions..
May 5 2021, 1:26 PM · Restricted Project

May 4 2021

Ayal added inline comments to D99294: [VPlan] Representing backedge def-use feeding reduction phis..
May 4 2021, 9:23 AM · Restricted Project

May 3 2021

Ayal added a comment to D100257: [VPlan] Add VPUserID to distinguish between recipes and others..

The anticipated long-term need for non-recipe VPUsers is indeed to represent live-outs, along with their underlying IR Value, or rather Instruction; analogous to VPValue::getLiveInIRValue(). This would call for a derived VPLiveOut non-recipe subclass of VPUser.

VPUser class itself should probably be pure virtual, similar to User, to avoid having a potential kitchen sink of dangling opaque instances. Instead of representing arbitrary "other"/"non-recipe" instances, the current VPUsers of VPBasicBlock predicates and conditions could be represented as specific, concrete subclasses of VPUser, potentially until they are cleaned up. WDYT?

May 3 2021, 2:52 AM · Restricted Project
Ayal added inline comments to D100113: [LV] Move reduction PHI node fixup to VPlan::execute (NFC)..
May 3 2021, 12:47 AM · Restricted Project
Ayal added inline comments to D100102: [VPlan] Use incoming VPValue to detect in-loop reductions (NFC)..
May 3 2021, 12:44 AM · Restricted Project
Ayal accepted D100751: [VPlan] Properly handle sinking of replicate regions..

This looks good, thanks for fixing, adding a couple of nits.

May 3 2021, 12:41 AM · Restricted Project

May 2 2021

Ayal accepted D100101: [VPlan] Add VPBasicBlock::phis() helper (NFC)..

This is fine, thanks!

May 2 2021, 10:18 AM · Restricted Project

Apr 29 2021

Ayal added a comment to D100257: [VPlan] Add VPUserID to distinguish between recipes and others..

Non-recipe "other" VPUsers are quite exceptional ... would it suffice to have (native) VPlan hold all 'dangling' non-recipe VPUsers of its VPBasicBlocks, as an alternative, until these are cleaned up?

The blocks need to use the VPUsers to access the current value they hold I think, so I am not sure how the VPlan holding the VPUsers would look like unfortunately. It would be great if you could elaborate in a bit more detail, in case I am missing something.

Apr 29 2021, 2:07 AM · Restricted Project

Apr 28 2021

Ayal accepted D99293: [LV] Iterate over recipes in VPlan to fix PHI (NFC)..

Looks good to me, adding a minor nit; worth adding "NFC" to title.

Apr 28 2021, 11:52 PM · Restricted Project
Ayal added inline comments to D100102: [VPlan] Use incoming VPValue to detect in-loop reductions (NFC)..
Apr 28 2021, 2:29 PM · Restricted Project

Apr 27 2021

Ayal accepted D99294: [VPlan] Representing backedge def-use feeding reduction phis..

Adding a couple of related thoughts. Thanks!

Apr 27 2021, 1:28 PM · Restricted Project
Ayal added inline comments to D99294: [VPlan] Representing backedge def-use feeding reduction phis..
Apr 27 2021, 9:43 AM · Restricted Project
Ayal added a comment to D100102: [VPlan] Use incoming VPValue to detect in-loop reductions (NFC)..

Reducing the coupling with the cost model by using information directly in VPlan is great. Have a few comments.

Apr 27 2021, 6:20 AM · Restricted Project
Ayal added a comment to D100101: [VPlan] Add VPBasicBlock::phis() helper (NFC)..

Looks good to me!

Apr 27 2021, 12:43 AM · Restricted Project

Apr 26 2021

Ayal added a comment to D100257: [VPlan] Add VPUserID to distinguish between recipes and others..

Non-recipe "other" VPUsers are quite exceptional ... would it suffice to have (native) VPlan hold all 'dangling' non-recipe VPUsers of its VPBasicBlocks, as an alternative, until these are cleaned up?

Apr 26 2021, 10:47 PM · Restricted Project
Ayal added a comment to D99294: [VPlan] Representing backedge def-use feeding reduction phis..

Looks good to me!
Adding a couple of nits and thoughts.
Perhaps "[VPlan] Representing backedge def-use feeding reduction phi's" may be a more accurate title - "incoming" also (more-so?) applies to the operand from the preheader.

Apr 26 2021, 2:16 PM · Restricted Project

Mar 27 2021

Ayal added a comment to D98849: [LV] Compute ranges for plans up front (NFC)..

Thanks @fhahn for moving this forward!
Have mostly minor nits.

Mar 27 2021, 3:06 AM · Restricted Project

Jan 8 2021

Ayal added inline comments to D93629: [LV] Don't sink into replication regions.
Jan 8 2021, 4:52 AM · Restricted Project

Jan 5 2021

Ayal accepted D92129: [VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC)..

This looks good to me, thanks!

Jan 5 2021, 2:20 PM · Restricted Project
Ayal accepted D92281: [VPlan] Add getLiveInIRValue accessor to VPValue..

ok, please land independent changes separately, thanks!

Jan 5 2021, 2:17 PM · Restricted Project
Ayal added a comment to D92281: [VPlan] Add getLiveInIRValue accessor to VPValue..

(how) are the VPPredInstPHIRecipe changes related to the introduction of getLiveInIRValue()?

Jan 5 2021, 1:21 PM · Restricted Project
Ayal added a comment to D93317: [LV] Vectorize (some) early and multiple exit loops.

LGTM, thanks! I pushed a small fix for the crash discussed earlier in 0ea3749b3cde. It should be a very safe/straight-forward fix, but I would appreciate taking a look post-review.

Jan 5 2021, 8:35 AM · Restricted Project
Ayal added a comment to D92129: [VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC)..

Good step towards representing more Values, and in particular recording InductionDescriptor information, in VPlan!

Jan 5 2021, 4:43 AM · Restricted Project
Ayal added a comment to D92281: [VPlan] Add getLiveInIRValue accessor to VPValue..

This currently requires giving access to VPValue to those classes, so we
can call the protected constructor. But most of them can be removed in
the future, once the remaining single value def recipes inherit from
VPValue.

Jan 5 2021, 4:35 AM · Restricted Project

Dec 29 2020

Ayal added a comment to rG0ea3749b3cde: [LV] Set up branch from middle block earlier..

Good catch and fix! Minor post-commit comments.

Dec 29 2020, 2:31 AM

Dec 24 2020

Ayal added a comment to D93317: [LV] Vectorize (some) early and multiple exit loops.

I think there are some scenarios when we break some LCSSA PHIs that use PHIs created during SCEV expansion when we generate the runtime checks. After a first glance, it appears like an issue after we add the conditional branch from the middle block. The example below should cause a verifier failure with opt -loop-vectorize -force-vector-width=4. I tried to reduce it a bit, but unfortunately it is still quite ugly.

Dec 24 2020, 5:15 AM · Restricted Project

Dec 22 2020

Ayal accepted D93317: [LV] Vectorize (some) early and multiple exit loops.

This looks fine to me, thanks; would be good to get @fhahn approval too.

Dec 22 2020, 2:56 PM · Restricted Project

Dec 21 2020

Ayal added a comment to D93317: [LV] Vectorize (some) early and multiple exit loops.

Nice leverage of requiresScalarEpilogue!
Looks good to me, adding some minor comments.

Dec 21 2020, 4:53 PM · Restricted Project

Dec 12 2020

Ayal accepted D92066: [LAA] Relax restrictions on early exits in loop structure.

This looks good to me, adding some minor comments. Thanks!

Dec 12 2020, 3:23 PM · Restricted Project

Nov 24 2020

Ayal committed rG32d9a386bf8f: [LV] Keep Primary Induction alive when folding tail by masking (authored by Ayal).
[LV] Keep Primary Induction alive when folding tail by masking
Nov 24 2020, 5:37 AM
Ayal closed D92017: [LV] Keep Primary Induction alive when folding tail by masking.
Nov 24 2020, 5:37 AM · Restricted Project
Ayal added a comment to D66720: [LV] Fold tail by masking - handle reductions.

@Ayal Hi.
Found a problem caused by these changes.
Take a look, please. I posted about it here https://bugs.llvm.org/show_bug.cgi?id=47390

I attach the file here too, after the bug point:

Run like this:
opt -passes=loop-vectorize 'reduced-simplified.ll' -S

Could you take a look?
Thanks in advance.

Nov 24 2020, 5:07 AM · Restricted Project
Ayal requested review of D92017: [LV] Keep Primary Induction alive when folding tail by masking.
Nov 24 2020, 2:52 AM · Restricted Project

Nov 15 2020

Ayal accepted D90558: [VPlan] Add VPDef class..

This looks good to me, thanks!

Nov 15 2020, 9:08 AM · Restricted Project
Ayal added inline comments to D90558: [VPlan] Add VPDef class..
Nov 15 2020, 12:45 AM · Restricted Project

Nov 14 2020

Ayal added inline comments to D90558: [VPlan] Add VPDef class..
Nov 14 2020, 2:28 PM · Restricted Project

Nov 13 2020

Ayal added a comment to D88380: [VPlan] Extend VPValue to also model sub- & 'virtual' values..

OK sounds great. I did not know that MLIR could represent multiple values, that's good to see.

I still like honestly like a more "llvm" Value/User model more, but perhaps as I read the patches I will learn to like Defs too.

Nov 13 2020, 5:33 AM · Restricted Project
Ayal added a comment to D90558: [VPlan] Add VPDef class..

Looks good to me, adding minor comments, thanks for pushing this forward!

Nov 13 2020, 12:34 AM · Restricted Project

Nov 12 2020

Ayal added a comment to D88380: [VPlan] Extend VPValue to also model sub- & 'virtual' values..

Extending the recipe abstraction to support def/use relations is an important next step forward for VPlan, thanks for pushing this momentum forward!

Nov 12 2020, 3:44 PM · Restricted Project

Oct 12 2020

Ayal added inline comments to D87679: [LV] Unroll factor is expected to be > 0.
Oct 12 2020, 5:55 AM · Restricted Project

Oct 9 2020

Ayal added inline comments to D87679: [LV] Unroll factor is expected to be > 0.
Oct 9 2020, 2:40 PM · Restricted Project

Sep 27 2020

Ayal added inline comments to D87679: [LV] Unroll factor is expected to be > 0.
Sep 27 2020, 6:00 AM · Restricted Project

Sep 22 2020

Ayal accepted D84679: [VPlan] Disconnect VPValue and VPUser..

This looks good to me, thanks!

Sep 22 2020, 3:35 PM · Restricted Project

Sep 21 2020

Ayal added a comment to D84679: [VPlan] Disconnect VPValue and VPUser..

This looks good to me, as part of the effort to support VPlan def-use modeling and traversals.
Note that top-down traversal from VPValue to its VPUsers, will now need to check if each VPUser isa single-def recipe/VPInstruction in order to continue downwards to its VPUsers, etc., facilitating multi-def recipes.

Sep 21 2020, 8:52 AM · Restricted Project

Jul 12 2020

Ayal added a comment to D83470: [LV] Fix versioning-for-unit-stide of loops with small trip count.

LGTM, thanks!

In such cases, the loop vectorizer should either re-run the analysis or bail-out from vectorizing the loop, as done prior to D81345. The latter is chosen for now as the former requires refactoring.

As already discussed in D81345, ideally LV would have more flexibility to drive LAA, but this requires non-trivial refactoring. Which we should do, but until then the patch looks like a reasonable fix to the crash.

Jul 12 2020, 10:48 AM · Restricted Project
Ayal committed rG82a5157ff165: [LV] Fixing versioning-for-unit-stide of loops with small trip count (authored by Ayal).
[LV] Fixing versioning-for-unit-stide of loops with small trip count
Jul 12 2020, 10:42 AM
Ayal closed D83470: [LV] Fix versioning-for-unit-stide of loops with small trip count.
Jul 12 2020, 10:42 AM · Restricted Project
Ayal added a comment to D83288: [LV] Pick vector loop body as insert point for SCEV expansion..

Good catch!

Jul 12 2020, 7:58 AM · Restricted Project
Ayal accepted D75069: [LoopVectorizer] Inloop vector reductions.

This looks good to me, thanks! with last couple of nits.

Jul 12 2020, 7:35 AM · Restricted Project

Jul 9 2020

Herald added a project to D83470: [LV] Fix versioning-for-unit-stide of loops with small trip count: Restricted Project.
Jul 9 2020, 3:29 AM · Restricted Project

Jul 7 2020

Ayal added inline comments to D75069: [LoopVectorizer] Inloop vector reductions.
Jul 7 2020, 3:05 PM · Restricted Project
Ayal added inline comments to D75069: [LoopVectorizer] Inloop vector reductions.
Jul 7 2020, 12:33 PM · Restricted Project
Ayal added a comment to D81416: [LV] Interleave to expose ILP for small loops with scalar reductions..

In the application we try, LV refuse to vectorize due to not profitable, but if we force LV to vectorize and it will crash. Apparently there are some obstacles. There are cases that even if LV fails, SLP could succeed.

Jul 7 2020, 11:29 AM · Restricted Project, Restricted Project
Ayal added a comment to D81416: [LV] Interleave to expose ILP for small loops with scalar reductions..

IIUC, we should add a test under test/Transforms/PhaseOrdering with -O2 to show the cooperative effect of the 2 vectorizers rather than a stand-alone SLP test.
If you can push that test with full baseline CHECK lines and then apply this patch and show test diffs, that would make it much easier to tell what is intended with this patch.

Thanks for the comment. This patch does not intend to change or test phase ordering. In this patch, we interleave for small loops with scalar reductions which cannot be vectorized by LV, and later on SLP captures the opportunities. Interleaving is done by LV, and vectorization is done by SLP.

Jul 7 2020, 7:11 AM · Restricted Project, Restricted Project
Ayal added inline comments to D81345: [LV] Vectorize without versioning-for-unit-stride under -Os/-Oz.
Jul 7 2020, 5:10 AM · Restricted Project
Ayal committed rG7bf299c8d8d5: [LV] Vectorize without versioning-for-unit-stride under -Os/-Oz (authored by Ayal).
[LV] Vectorize without versioning-for-unit-stride under -Os/-Oz
Jul 7 2020, 5:05 AM
Ayal closed D81345: [LV] Vectorize without versioning-for-unit-stride under -Os/-Oz.
Jul 7 2020, 5:05 AM · Restricted Project

Jul 6 2020

Ayal added inline comments to D75069: [LoopVectorizer] Inloop vector reductions.
Jul 6 2020, 1:15 PM · Restricted Project

Jun 13 2020

Ayal added inline comments to D81345: [LV] Vectorize without versioning-for-unit-stride under -Os/-Oz.
Jun 13 2020, 11:26 PM · Restricted Project

Jun 7 2020

Ayal accepted D80446: [NFC][LV][TEST]: extend pr45679-fold-tail-by-masking.ll with a run of -force-vector-width=1 -force-vector-interleave=4.

Looks good to me, thanks for following-up on this suggestion from D79976.

Jun 7 2020, 1:19 PM · Restricted Project
Ayal created D81345: [LV] Vectorize without versioning-for-unit-stride under -Os/-Oz.
Jun 7 2020, 9:34 AM · Restricted Project

Jun 5 2020

Ayal added a comment to D75069: [LoopVectorizer] Inloop vector reductions.

The proposed RecurrenceDescriptor::getReductionOpChain() method identifies horizontal reductions, a subset of the vertical reductions identified by RecurrenceDescriptor::isReductionPHI(). Being two totally independent methods, it's unclear what the latter supports that the former does not. Would it be better to have isReductionPHI() also take care of recognizing horizontal reductions, and record them as in CastsToIgnore? See also TODO commented inline.

Jun 5 2020, 3:43 PM · Restricted Project

Jun 2 2020

Ayal added inline comments to D80787: [VPlan] Support extracting lanes for defs managed in VPTransformState..
Jun 2 2020, 12:05 PM · Restricted Project

Jun 1 2020

Ayal accepted D80870: [LV] Make sure smallest/widest type sizes are powers-of-2..

Thanks!

Jun 1 2020, 2:39 PM · Restricted Project
Ayal added a comment to D80870: [LV] Make sure smallest/widest type sizes are powers-of-2..

D80491 has been breaking our ToT builds for a week now. Can this be submitted soon. If not please consider reverting D80491.

Jun 1 2020, 1:33 PM · Restricted Project

May 30 2020

Ayal added a comment to D80870: [LV] Make sure smallest/widest type sizes are powers-of-2..

Alternatively we could force the computed max VF to the next-lowest power-of-2

May 30 2020, 2:18 PM · Restricted Project

May 26 2020

Ayal accepted D79969: [LAA] We only need pointer checks if there are non-zero checks (NFC)..

Looks good to me. Added a minor nit.

May 26 2020, 2:44 PM · Restricted Project

May 25 2020

Ayal committed rG840450549c91: [LV] Clamp MaxVF to power of 2. (authored by Ayal).
[LV] Clamp MaxVF to power of 2.
May 25 2020, 1:35 AM
Ayal closed D80491: [LV] Clamp MaxVF to power of 2.
May 25 2020, 1:34 AM · Restricted Project

May 24 2020

Ayal added inline comments to D80491: [LV] Clamp MaxVF to power of 2.
May 24 2020, 3:59 PM · Restricted Project
Ayal created D80491: [LV] Clamp MaxVF to power of 2.
May 24 2020, 9:36 AM · Restricted Project
Ayal added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 24 2020, 4:16 AM · Restricted Project
Ayal added inline comments to D80219: [VPlan] Use VPUser for VPWidenSelectRecipe operands (NFC)..
May 24 2020, 1:34 AM · Restricted Project

May 22 2020

Ayal added inline comments to D79976: [LV] Handle Fold-Tail of loops with vectorizarion factor (VF) equal to 1.
May 22 2020, 7:28 AM · Restricted Project

May 20 2020

Ayal added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 20 2020, 1:43 PM · Restricted Project